CN1170959A - 形成快闪存储器的浮置栅极的方法 - Google Patents

形成快闪存储器的浮置栅极的方法 Download PDF

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CN1170959A
CN1170959A CN97105579A CN97105579A CN1170959A CN 1170959 A CN1170959 A CN 1170959A CN 97105579 A CN97105579 A CN 97105579A CN 97105579 A CN97105579 A CN 97105579A CN 1170959 A CN1170959 A CN 1170959A
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金明宣
白善幸
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SK Hynix Inc
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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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Abstract

一种快闪存储器的浮置栅极的制造方法,其可以保持浮栅的预定宽度,避免存储能力损失。该方法包括步骤:在半导体基底上形成场氧化物层;形成栅氧化物层和导电层;在导电层上依次形成第一氧化物层和氮化硅层;形成一光阻材料图形;选择性蚀刻上述氮化硅层、第一氧化物层和导电层;用离子注入法形成源/漏极区;去除上述光阻图形;形成一钝化层,对钝化层进行各向异性蚀刻,在上述浮栅侧壁形成一隔离层;在上述氮化硅层上形成一个第二氧化物层;和形成一个控制栅板。

Description

形成快闪存储器的 浮置栅极的方法
本发明涉及一种用于形成一个在浮置栅极和控制栅极之间包含介电层的快闪存储器(flash memory device)的方法，特别是涉及一种不降低存储器的存储电荷的能力的快闪存储器的一个浮置栅极的形成方法。
通常，一个快闪光存储器的一个叠置栅极是通过以下步骤完成的；在一个硅基底上依次形成一场氧化物层、一栅氧化物层、一用作浮置栅极的多晶硅层、一介电层和一用作控制栅极的多晶硅层；形成上述控制栅极的多晶硅层；对上述介电层和用作控制栅极的多晶硅层进行选择性刻蚀，以便形成叠置栅极图形。其中，上述介电层是由一个叠层组成的，它包含一个氧化硅层、一个氮化硅层和一个氧化硅层。
但是，在形成叠置栅极图形的干蚀刻工艺中，基片遭受破坏，因此存储器特性降低。
图1A至图1C示出了一种为克服上述缺点的形成一个快闪存储器的叠置栅极的常规方法。
首先，参考图1A，在一个硅基底11上，通过热氧化法形成场氧化物层(FOX)12，然后形成一个栅氧化物层13。在上述栅氧化物层13顶部沉积一用作浮置栅极的多晶硅层14，在上述多晶硅层14上依次形成一个氧化硅层15和一个氮化硅层16。在上述氮化硅层16上形成一个光致抗蚀剂图形17，作为离子注入和蚀刻的掩模。
参考图1B，利用上述光致抗蚀剂图形17作为蚀刻掩模，依次对上述氮化硅层16、氧化硅层15和多晶硅层14进行蚀刻。将N型杂质，如砷离子，注入到硅基底11，其采用各向异性干蚀刻法使硅基底11暴露，以光致抗蚀剂图形17作为离子注入掩模，形成源/漏极区(未示出)。
参考图1C，去除上述光致抗蚀剂图形17以后，利用热氧化工艺在上述氮化硅层16上形成一个氧化层18。上述氧化硅层18也可以由一个在高温气氛下形成的氧化物层代替。在上述整个结构上形成一个用作控制栅极的多晶硅层19，并形成一个光致抗蚀剂图形20，用以对控制栅极构图。在形成上述氧化硅层18的过程中，上述暴露的硅基底也被热氧化形成一个氧化硅层18′，其厚度大于在上述氮化硅层16上形成的氧化硅层18的厚度。因此，上述氧化硅层18防止硅基底11在形成控制栅极图形的干蚀刻过程中损坏。另一方面，多晶硅14的暴露侧面14也被迅速氧化，因此在浮置栅极的某个部分也形成一个氧化区域14′。结果，浮置栅极的宽度比所需宽度“A”小被氧化区域14′的宽度。
因此，本发明是鉴于上述问题而作出的。本发明的一个目的是提供一种形成一个快闪存储器的浮置栅极的方法，使得浮置栅极不存在氧化部分。
为实现上述目的，本发明提出了一种形成快闪存储器的浮置栅极的方法，该存储器在所述浮置栅极和一个控制栅极之间包括一个介电层，该方法包括如下步骤：在一个半导体基底上形成场氧化物层；在所述半导体基底上形成一个栅氧化物层和用作所述浮置栅极的一个导电层；在所述导电层上依次形成一个第一氧化层和一个氮化硅层；形成一光致抗蚀剂图形；选择性地蚀刻上述氮化硅层、第一氧化物层和导电层；通过离子注入工艺形成源/漏极区；去除上述光致抗蚀剂图形；在所得结构上形成一个钝化层，采用各向异性蚀刻工艺对上述钝化层进行蚀刻，在上述浮置栅极的一个侧壁形成一个隔离层，以防止所述浮置栅极的侧壁被氧化；在上述氮化硅层上形成一个第二氧化物层；以及在所得结构上形成一个控制栅极。
本发明的这些以及其它目的、特征和优点通过以下结合附图对优选实施例的描述会变得更清楚。附图中：
图1A至1C是形成一个快闪存储器的一个叠置栅极的一种常规方法的截面视图；
图2A至2C是按照本发明形成一个快闪存储器的一个叠置栅极的一种方法的截面视图。
下面结合图2A至2C对本发明的一个优选实施例进行详细描述。
首先参照图2A，用热氧化法在一个硅基底21上形成一个场氧化物层22。在硅基底21上形成一个用作浮置栅极的栅氧化物层23和一个多晶硅层24。再形成一个氧化硅层25和一个氮化硅层26。在上述氮化硅层26上形成一个光致抗蚀剂图形27，作为蚀刻和离子注入的掩模。
再参照图2B，利用光致抗蚀剂图形27作为蚀刻掩模，用各向异性蚀刻工艺依次对上述氮化硅层26、氧化硅层25和多晶硅层24进布选择性蚀刻，直至暴露上述栅氧化物层23。在上述蚀刻过程中，用作浮置栅极的多晶硅层24的侧壁被暴露出来。然后，利用光致抗蚀刻剂图形27作为离子注入掩模向硅基底21注入例如砷离子的N型杂质，硅基底21在各向异性干蚀刻工艺中被选择性地暴露，形成一个源/漏极区(图中未示出)。一个钝化层，在该优选实施例中是一个未掺杂的多晶硅层28，沉积在上述整个结构上，以防止上述多晶硅层的侧壁被氧化。这里，未掺杂多晶硅层28可以被一个掺杂多晶硅层代替，但是在这种情况下，掺杂多晶硅形成为几千埃的厚度。一个低温下形成的氮化硅层或氧化物层也可以代替上述未掺杂多晶硅层。
最后，参照图2C，上述未掺杂多晶硅层28在没有蚀刻掩模的情况下被各向异性蚀刻，从而在上述层24、25和26的侧壁形成一个隔离层28′。采用热氧化法在氮化硅层26上形成一个氧化硅层29，并在所得结构上形成一个用作控制栅极的多晶硅层30。在上述多晶硅层30上形成一个光致抗蚀剂图形31以对控制栅极构图。这里，上述氧化硅层29可以由一个在高温下形成的氧化物层代替。
因为上述未掺杂多晶硅氧化很慢，由未掺杂多晶硅形成的隔离层28′阻止多晶硅层24的侧面在后续氧化过程中被氧化，所以得到了上述浮置栅极的所需图形，且不损失存储能力和降低器件的特性。
特别地，由于隔离层28′有一个斜度，多晶硅层30的残留量可以减少，防止了残留物与金属互连线的接触。因此，消除了电极之间短路的可能性。
尽管为了解释性目的而公开了本发明的优选实施例，但是本领域的技术人员将会认识到，在不背离本发明所附权利要求的范围和精神的情况下，可能对其进行各种修改、增删和替代。

Claims (4)

1.一种形成一快闪存储器的一个浮置栅极的方法，该快闪存储器在所述浮置栅极和控制栅极之间具有一个介电层，其步骤如下：
在一个半导体基底上形成场氧化物层；
在上述基底上形成一个栅氧化物层和一个上述浮置栅极的导电层；
在上述导电层上依次形成一个第一氧化物层和一个氮化硅层；
形成一个光致抗蚀剂图形；
选择性蚀刻上述氮化硅层、上述第一氧化物层、和上述导电层；
用离子注入工艺形成源/漏极区；
去除上述光致抗蚀剂图形；
在所得结构上形成一个钝化层；以及
对上述钝化层采用各向异向蚀刻工艺，在上述浮置栅极的侧壁上形成一个隔离层，以防上述浮置栅极的侧壁被氧化；
在上述氮化硅层上形成一个第二氧化物层；和
在上述所得结构上形成一个控制栅极。
2.根据权利要求1所述的方法，其中上述导电层是掺杂多晶硅层。
3.根据权利要求1所述的方法，其中上述钝化层是未掺杂多晶硅层。
4.根据权利要求1所述的方法，其中上述钝化层是氮化硅层或二氧化硅层。
CN97105579A 1996-06-29 1997-06-18 形成快闪存储器的浮置栅极的方法 Expired - Fee Related CN1106042C (zh)

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6943074B2 (en) 1999-04-27 2005-09-13 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having a two-layer gate structure and method for manufacturing the same
CN1309055C (zh) * 2004-03-25 2007-04-04 力晶半导体股份有限公司 闪速存储器的制造方法
CN1323440C (zh) * 1999-02-23 2007-06-27 西利康存储技术股份有限公司 带自对准栅极的快闪存储单元及其制造方法
CN100399546C (zh) * 2005-03-10 2008-07-02 海力士半导体有限公司 制造快闪存储装置的方法
CN100447953C (zh) * 1999-10-25 2008-12-31 斯班逊有限公司 于二位eeprom装置制造ono浮动栅极的高温氧化物沉淀方法
US8049265B2 (en) 2007-12-03 2011-11-01 Dongbu Hitek Co., Ltd. Semiconductor device and method of fabricating the same
CN102087963B (zh) * 2009-12-04 2013-08-14 无锡华润上华半导体有限公司 多晶硅层的蚀刻方法
CN107946312A (zh) * 2017-11-23 2018-04-20 长江存储科技有限责任公司 防止外围电路受损的方法及结构
CN107968090A (zh) * 2017-11-23 2018-04-27 长江存储科技有限责任公司 防止外围电路受损的方法及结构
US10756113B2 (en) 2017-11-23 2020-08-25 Yangtze Memory Technologies Co., Ltd. Protective structure and fabrication methods for the peripheral circuits of a three-dimensional memory

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7804115B2 (en) * 1998-02-25 2010-09-28 Micron Technology, Inc. Semiconductor constructions having antireflective portions
US6274292B1 (en) * 1998-02-25 2001-08-14 Micron Technology, Inc. Semiconductor processing methods
US6268282B1 (en) 1998-09-03 2001-07-31 Micron Technology, Inc. Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks
US6281100B1 (en) 1998-09-03 2001-08-28 Micron Technology, Inc. Semiconductor processing methods
US6828683B2 (en) 1998-12-23 2004-12-07 Micron Technology, Inc. Semiconductor devices, and semiconductor processing methods
US7235499B1 (en) * 1999-01-20 2007-06-26 Micron Technology, Inc. Semiconductor processing methods
KR20010005001A (ko) 1999-06-30 2001-01-15 김영환 플래쉬 메모리 셀의 제조 방법
US7067414B1 (en) 1999-09-01 2006-06-27 Micron Technology, Inc. Low k interlevel dielectric layer fabrication methods
KR100376270B1 (ko) * 1999-12-28 2003-03-17 주식회사 하이닉스반도체 스플리트 게이트형 플래쉬 메모리 소자의 제조방법
US6440860B1 (en) 2000-01-18 2002-08-27 Micron Technology, Inc. Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride
KR100423064B1 (ko) * 2002-03-21 2004-03-12 주식회사 하이닉스반도체 반도체 소자의 제조 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4722908A (en) * 1986-08-28 1988-02-02 Fairchild Semiconductor Corporation Fabrication of a bipolar transistor with a polysilicon ribbon
US5070032A (en) * 1989-03-15 1991-12-03 Sundisk Corporation Method of making dense flash eeprom semiconductor memory structures
US5026663A (en) * 1989-07-21 1991-06-25 Motorola, Inc. Method of fabricating a structure having self-aligned diffused junctions
US5266509A (en) * 1990-05-11 1993-11-30 North American Philips Corporation Fabrication method for a floating-gate field-effect transistor structure
US4997790A (en) * 1990-08-13 1991-03-05 Motorola, Inc. Process for forming a self-aligned contact structure
KR940010564B1 (ko) * 1991-10-10 1994-10-24 금성일렉트론 주식회사 전계효과 트랜지스터 및 그 제조방법
EP1032034A1 (en) * 1992-01-22 2000-08-30 Macronix International Co., Ltd. Method of making memory device
US5225362A (en) * 1992-06-01 1993-07-06 National Semiconductor Corporation Method of manufacturing a full feature high density EEPROM cell with poly tunnel spacer
US5478767A (en) * 1994-09-30 1995-12-26 United Microelectronics Corporation Method of making a flash EEPROM memory cell comprising polysilicon and textured oxide sidewall spacers

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1323440C (zh) * 1999-02-23 2007-06-27 西利康存储技术股份有限公司 带自对准栅极的快闪存储单元及其制造方法
US6943074B2 (en) 1999-04-27 2005-09-13 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having a two-layer gate structure and method for manufacturing the same
CN100447953C (zh) * 1999-10-25 2008-12-31 斯班逊有限公司 于二位eeprom装置制造ono浮动栅极的高温氧化物沉淀方法
CN1309055C (zh) * 2004-03-25 2007-04-04 力晶半导体股份有限公司 闪速存储器的制造方法
CN100399546C (zh) * 2005-03-10 2008-07-02 海力士半导体有限公司 制造快闪存储装置的方法
US8049265B2 (en) 2007-12-03 2011-11-01 Dongbu Hitek Co., Ltd. Semiconductor device and method of fabricating the same
CN102087963B (zh) * 2009-12-04 2013-08-14 无锡华润上华半导体有限公司 多晶硅层的蚀刻方法
CN107946312A (zh) * 2017-11-23 2018-04-20 长江存储科技有限责任公司 防止外围电路受损的方法及结构
CN107968090A (zh) * 2017-11-23 2018-04-27 长江存储科技有限责任公司 防止外围电路受损的方法及结构
CN107946312B (zh) * 2017-11-23 2019-01-29 长江存储科技有限责任公司 防止外围电路受损的方法及结构
CN107968090B (zh) * 2017-11-23 2019-02-12 长江存储科技有限责任公司 防止外围电路受损的方法及结构
US10756113B2 (en) 2017-11-23 2020-08-25 Yangtze Memory Technologies Co., Ltd. Protective structure and fabrication methods for the peripheral circuits of a three-dimensional memory
US11404442B2 (en) 2017-11-23 2022-08-02 Yangtze Memory Technologies Co., Ltd. Protective structure and fabrication methods for the peripheral circuits of a three-dimensional memory

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US5872035A (en) 1999-02-16

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