CN1169216C - 半导体集成电路器件 - Google Patents

半导体集成电路器件 Download PDF

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Publication number
CN1169216C
CN1169216C CNB981147372A CN98114737A CN1169216C CN 1169216 C CN1169216 C CN 1169216C CN B981147372 A CNB981147372 A CN B981147372A CN 98114737 A CN98114737 A CN 98114737A CN 1169216 C CN1169216 C CN 1169216C
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Prior art keywords
bonding welding
welding pad
semiconductor device
unit
pad
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CNB981147372A
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CN1204153A (zh
Inventor
能登隆行
二
大井英二
宏
盐月八宏
雄
加藤和雄
树
大萩秀树
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Hitachi Ltd
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Hitachi Ltd
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Abstract

在CMOS栅阵列中，对应于信号输入单元和对应于电源电压输入单元的每个键合焊盘由多个导体层构成，而对应于将不被采用的输入/输出单元的每个键合焊盘(未连接的焊盘)例如由最上层导体层构成。所以，与信号键合焊盘和电源电压键合焊盘相比，对应于将不被采用的输入/输出单元的每个键合焊盘(不连接的焊盘)其下的绝缘膜的厚度变得较厚，其与半导体衬底间的距离较远。

Description

半导体集成电路器件
本发明涉及一种半导体集成电路器件，特别涉及一种在应用于防范采用母片法的逻辑LSI(大规模集成电路)的静电损伤时有效的技术。
母片法制造的逻辑LSI是一种按以下方式实现所需逻辑功能的器件，即如MISFET(金属绝缘体半导体场效应晶体管)等构成基本单元和I/O(输入/输出)单元的半导体元件预先形成于半导体衬底上，然后根据逻辑规范由布线互连半导体元件。
关于这种母片法的逻辑LSI，不管实际要用的管脚数量如何，预先在半导体衬底上制造预定数量的I/O单元的键合焊盘和底层(半导体元件)，由此于某逻辑规范中存在不用的管脚。在以下的说明中，称这些不连接到半导体衬底的内部电路上的不用的管脚为“NC(未连接的)管脚”。
一般情况下，这种基于母片法的逻辑LSI中，保护电路插在每个输入管脚和相应的输入电路间，以便吸收过电压，作为防止由于静电放电造成的绝缘膜或内部电路p-n结击穿的防范措施。另外，如下所述，对应于NC管脚的不使用的键合焊盘(此后称为NC焊盘)有与I/O单元键合焊盘相同的结构。
然而，本发明人的研究显示：由于对应NC管脚的NC焊盘与I/O单元间没有设置布线，所以其间不形成保护电路。因此，NC管脚的抗静电损伤强度低于连接到保护电路上的所用管脚。例如，在芯片组装(封装)步骤完成后，在任何原因引起的电荷累积于NC管脚上时，隔离NC焊盘与其正下方的半导体衬底的绝缘膜受到静电损伤，以致于引起NC焊盘和衬底间的短路。
作为防止这种NC管脚静电损伤的防范措施，例如认为在组装封装的步骤中，不在NC管脚和NC焊盘间键合引线，由此可以避免过电压加到NC焊盘上。
除此之外，日本特许公开公报120426/1994记载了一种防范措施，在对应于NC管脚的NC焊盘和不用的I/O单元间也形成保护电路，从而吸收掉NC焊盘上的令人讨厌的过电压。
防范NC管脚的静电损伤的上述措施中，在组装封装的步骤时在NC管脚和NC焊盘间不键合引线的防范措施导致了某些引线无法键合到根据逻辑规范而不同的半导体芯片中存在的NC焊盘。因此，引线键合步骤变得非常复杂，造成了逻辑LSI产量降低的问题。
另一方面，保护电路也形成于NC焊盘和不用的I/O单元间的防范措施导致了不应连接到半导体衬底内部电路的NC管脚具有二极管特性。因此，NC管脚偏离了它们的定义，另外也是导致失效的原因。
本发明的目的是提供能够增强采用母片法的逻辑LSI中NC管脚的抗静电损伤强度的技术。
结合附图进行阅读，可以从本说明书中清楚地得知本发明的上述和其它目的及新特点。
下面简述本发明性能的典型方面：
(1)本发明的半导体集成电路器件包括一个母片法逻辑集成电路，其中半导体元件预先形成于半导体衬底的主表面上，然后这些元件根据逻辑规范借助于至少两层布线互连，由此实现所需的逻辑功能，并且每个对应于根据逻辑规范不用的I/O单元之外的I/O单元的键合焊盘由多个导体层构成，每个对应于不用I/O单元的键合焊盘由与最上层布线层相同的导体层构成，且导体层数少于对应于不用的I/O单元之外的I/O单元的各键合焊盘的多层导体层的层数。
(2)本发明的半导体集成电路器件中，逻辑集成电路中至少电源电压输入单元和与此对应的键合焊盘通过多个布线层电连接。
(3)本发明的半导体集成电路器件中，在形成除不用的I/O单元外的每个I/O单元前级形成输入保护电路，在形成不用的I/O单元前级不形成输入保护电路。
(4)本发明的半导体集成电路器件中，对应于不用的I/O单元的每个键合焊盘只由与最上层布线相同的导体层构成。
(5)本发明的半导体集成电路器件中，设置三层布线层，对应于不用的I/O单元的每个键合焊盘只由与第三层布线相同的导体层构成，对应于除不用的I/O单元外的I/O单元的每个键合焊盘由这三层导体层构成。
(6)本发明的半导体集成电路器件中，逻辑集成电路构成为或者包括栅阵列，或者包括具有栅阵列的微型计算机。
(7)本发明的半导体集成电路器件包括一个封装，其中形成有包括逻辑集成电路的集成电路的半导体芯片通过各金属丝与引线电连接，各金属丝连接到所有的键合焊盘上，所说键合焊盘包括对应于不用的I/O单元的键合焊盘。
(8)本发明的半导体集成电路器件包括一个封装，其中形成有包括逻辑集成电路的集成电路的半导体芯片通过突点电极与引线电连接，各引线连接到所有的键合焊盘上，键合焊盘包括对应于不用的I/O单元的键合焊盘。
图1是根据本发明的一个实施方案的形成有CMOS栅阵列的半导体芯片的完整平面图；
图2是展示根据本发明该实施方案的CMOS栅阵列的基本单元的平面图；
图3是展示形成根据本发明该实施方案的CMOS栅阵列的I/O单元的部分区域的放大平面图；
图4是展示形成根据本发明该实施方案的CMOS栅阵列的信号输入单元和相应键合焊盘的区域的剖面图；
图5是展示形成根据本发明该实施方案的CMOS栅阵列的电源电压输入单元和相应键合焊盘的区域的剖面图；
图6是展示形成根据本发明该实施方案的CMOS栅阵列的未连接I/O单元和相应键合焊盘的区域的剖面图；
图7是根据采用CAD的自动布局布线系统的布线形成工艺的流程图；
图8至14是半导体衬底的基本部分的剖面图，展示了根据本发明该实施方案制造CMOS栅阵列的方法；
图15是包封了由根据本发明该实施方案的CMOS栅阵列形成的半导体芯片的QFP(方形扁平封装)的示意平面图；
图16是展示形成包封于图15所示QFP中的半导体芯片的键合焊盘和I/O单元的部分区域的放大平面图；
图17是展示形成包封于图15所示QFP中的半导体芯片的键合焊盘和I/O单元的部分区域的放大剖面图；
图18是在其上安装图15所示QFP的印刷布线电路板的基本部分的平面图；
图19是在其上安装图15所示QFP的印刷布线电路板的基本部分的剖面图；
图20是包封了根据本发明另一实施方案形成有微型计算机的半导体芯片的TCP(载带式封装)的示意平面图；
图21是展示形成封装于图20所示TCP中的半导体芯片的键合焊盘和I/O单元的部分区域的放大平面图；
图22是展示形成包封于图20所示TCP中的半导体芯片的键合焊盘和I/O单元的部分区域的放大剖面图；
图23是展示形成本发明另一实施方案的CMOS栅阵列的键合焊盘的区域的剖面图；
图24是展示形成本发明再一实施方案的CMOS栅阵列的键合焊盘的区域的剖面图；
图25是展示形成本发明又一实施方案的CMOS栅阵列的键合焊盘的区域的剖面图；
图26是展示形成本发明再一实施方案的CMOS栅阵列的键合焊盘的区域的剖面图；
图27是包封了形成有根据本发明不同实施方案的CMOS栅阵列的半导体芯片的封装的剖面图；
图28是展示形成比较例的未连接的I/O单元和与之相应的键合焊盘区域的剖面图。
下面将结合附图详细说明本发明的实施例。由此，整个用于解释发明实施方案的附图中，相同的符号指相同功能的构件，所以将不再对它们进行描述。
(实施例1)
该实施例的半导体集成电路是一个CMOS(互补金属氧化物半导体)栅阵列。图1是形成有CMOS栅阵列的半导体芯片的整体平面示图。
构成栅阵列的逻辑部分的内部单元阵列CA一般形成于单晶硅制的半导体芯片1A的主表面中心。内部单元阵列CA包括大量基本单元2，基本单元2排列成X方向(横向)和Y方向(纵向)的矩阵形。如图2所示，每个基本单元2包括预定数量的N沟MISFET Qn和p沟MISFET Qp，它们的栅电极单向排列。每个基本单元2中的MISFET和基本单元2自身根据逻辑规范借助以后将解释的第一布线层、第二布线层和第三布线层连接，由此实现所需逻辑功能。
多个I/O单元3围绕内部单元阵列CA排列，以便包围该内部单元阵列CA。与基本单元2类似，每个I/O单元3也由预定数量的N沟MISFET和P沟MISFET构成。依逻辑规范改变第一至第三布线层间的连接图形，以便实现例如输入单元、输出单元、双向单元、根据逻辑规范不采用的I/O单元、及电源电压I/O单元的不同输入/输出电路功能。
建立与外部器件电连接的键合焊盘(外部连接端)BP围绕I/O单元3排列，即，在半导体芯片1A的外围部分排列。键合焊盘BP位于对应于I/O单元3阵列的位置处，并通过以后将说明的引出布线与对应的I/O单元3电连接。
尽管没有特别限制，但本实施方案的CMOS栅阵列具有被由铝(Al)合金膜构成的三层布线(金属布线)覆盖的半导体芯片1A。这些布线中，第一层布线(50)和第二层布线(60)主要形成信号布线，而第三层布线(70)主要形成电源电压布线(Vcc和GND)。这些布线的连接图形例如由采用CAD(计算机辅助设计)的自动布局布线系统产生。第一、第二和第三层布线布设成分别在X方向、Y方向和X方向延伸。
图3是展示形成I/O单元3的部分区域的放大平面示图。图中的符号3a表示信号的输入单元，符号3b表示电源电压(Vcc或GND)的输入单元，符号3c表示根据逻辑规范限定为未连接的I/O单元。
信号的输入单元3a例如包括两级CMOS反相器，它的前级是例如包括保护电阻PR和箝位MISFET Qpr的输入保护电路4。从键合焊盘BP输入的信号通过引出布线70a输到输入保护电路4，并随后通过输入单元3a传输到内部单元阵列CA。由于在输入单元3a的前一级设置了输入保护电路4，甚至在因某种原因而在一个未示出的连接到键合焊盘BP上的信号管脚上积累了电荷，也可以防止绝缘膜的击穿和输入单元3a及内部单元阵列CA中p-n结的击穿。除包括保护电阻PR和箝位MISFET Qpr外，输入保护电路4还可以包括例如带有或不带保护电阻的二极管。
图4是展示形成信号输入单元3a和与之相应的键合焊盘BP的区域的半导体芯片1A的剖面图。顺便提及，图中省略了对形成于输入单元3a前一级的输入保护电路4的说明。除此之外，只示出了输入单元3a的一部分(P沟MISFET Qp)。
在P型单晶硅制造的半导体衬底1的主表面上形成N阱6。在N阱6表面上元件隔离区中形成场氧化膜7，并在N阱6的有源区中形成构成输入单元3a的P沟MISFET Qp。每个P沟MISFET Qp主要由栅氧化膜(栅绝缘膜)8、栅极9、源(P型半导体区10)和漏(P型半导体区10)构成。栅极9例如由多晶硅膜、例如硅化钨等难熔金属硅化物膜堆叠于多晶硅膜上的多晶硅化物(poly-cide)膜、或硅化硅膜得到的硅化物膜构成。此外，源和漏的表面皆形成有利用Ti(钛)之类硅化衬底表面得到的硅化物层(如TiSi)10a。
在P沟MISFET Qp上覆盖氧化硅膜11，氧化硅膜11上又覆盖第一布线层50和构成键合焊盘BP的第一导体层50b。第一布线层50通过设置于氧化硅膜11中的接触孔12与P沟MISFET Qp的P型半导体区10电连接。
在第一布线层50上覆盖氧化硅膜之类构成的第一层间绝缘膜13，第一层间绝缘膜13上又覆盖第二布线层60和构成键合焊盘BP的第二导体层60b。第二导体层60b通过设置于第一层间绝缘膜13中的通孔14与第一导体层50b电连接。
在第二布线层60上覆盖氧化硅膜之类构成的第二层间绝缘膜15，第二层间绝缘膜15上又覆盖第三布线层70、构成键合焊盘BP的第三导体层70b及用于键合焊盘BP和输入单元3a间电连接的引出布线70a。第三导体层70b通过设置于第二层间绝缘膜15中的通孔16与第二导体层60b电连接。
除键合焊盘BP的表面外，半导体衬底1的最上部形成有钝化膜(表面保护膜)17，钝化膜17例如由包括氧化硅膜和氮化硅膜的堆叠膜构成。
以此方式，本实施方案的CMOS栅阵列中，对应于信号输入单元3a的键合焊盘BP由三个导体层(50b、60b和70b)构成，键合焊盘BP和输入单元3a皆通过由与第三布线层70相同的层构成的引出布线70a电连接。
如图3所示，类似于信号输入单元3a，电源电压输入单元3b包括CMOSFET，其前一级是输入保护电路4。从键合焊盘BP输入的电源电压(Vcc或GND)通过引出布线70a传输到输入保护电路4，并随后通过输入单元3b送入内部单元阵列CA。由于在输入单元3b的前一级设置了输入保护电路4，所以甚至在因某种原因而在一个未示出的连接到键合焊盘BP上的电源电压管脚上积累了电荷的情况下，也可以防止绝缘膜的击穿和输入单元3b及内部单元阵列CA中p-n结的击穿。
图5是展示形成电源电压输入单元3b和与之相应的键合焊盘BP的区域的半导体芯片1A的剖面图。顺便提及，图中省略了对形成于输入单元3b前一级的输入保护电路4的说明。除此之外，只示出了输入单元3b的一部分(P沟MISFET Qp)。
构成输入单元3b的P沟MISFET Qp上覆盖有氧化硅膜11，氧化硅膜11上又覆盖有第一布线层50、构成键合焊盘BP的第一导体层50b和用于键合焊盘BP与输入单元3b间电连接的引出布线50a。
第一布线层50上覆盖有第一层间绝缘膜13，第一层间绝缘膜13上又覆盖有第二布线层60、构成键合焊盘BP的第二导体层60b及用于键合焊盘BP和输入单元3b间电连接的引出布线60a。第二导体层60b通过设置于第一层间绝缘膜13中的通孔14与第一导体层50b电连接。
第二布线层60上覆盖有第二层间绝缘膜15，第二层间绝缘膜15上又覆盖有第三布线层70、构成键合焊盘BP的第三导体层70b及用于键合焊盘BP和第三布线层70间电连接的引出布线70a。第三导体层70b通过设置于第二层间绝缘膜15中的通孔16与第二导体层60b电连接。
以此方式，本实施方案的CMOS栅阵列中，对应于电源电压输入单元3b的键合焊盘BP由三个导体层(50b、60b和70b)构成。除此之外，用于电源电压的键合焊盘和输入单元3b皆通过三层引出布线(50a、60a和70a)电连接，从而增强了大电流流过的引出布线(50a、60a和70a)的电迁移电阻。
图6是展示形成未连接I/O单元3c和与之对应的键合焊盘(NC焊盘)BP的区域的半导体芯片1A的剖面图。
如该图所示，对应于I/O单元3c的键合焊盘(NC焊盘)BP只由与第三层布线70相同的第三导体层70b构成。另外，与键合焊盘(NC焊盘)BP连接的引出布线只由引出布线70a构成，而引出布线70a由与第三布线层70相同的层构成。因此，在构成键合焊盘(NC焊盘)BP的第三导体层70b和层70b下的那部分半导体衬底1之间只存在有绝缘膜(场氧化膜7、氧化硅膜11、第一层间绝缘膜13和第二层间绝缘膜15)，而在其间不存在任何导体层。
以此方式，在该实施例的CMOS栅阵列中，对应于信号输入单元3a的每个键合焊盘BP和对应于电源电压输入单元3b的每个键合焊盘BP皆由多个(三个)导体层(50b、60b和70b)构成，而对应于未连接的I/O单元3c的键合焊盘(NC焊盘)BP只由最上层导体层70b构成。
这样一来，与由三个导体层(50b、60b和70b)构成的用于信号和电源电压的各键合焊盘相比，对应于未连接的I/O单元3c的键合焊盘(NC焊盘)BP其底层绝缘膜的总厚度(l1)较大，与半导体衬底1的间隔较长。因此，甚至在因某种原因而在与键合焊盘(NC焊盘)BP连接的未示出的NC管脚上积累了电荷的情况下，介于键合焊盘(NC焊盘)BP和半导体衬底1间的绝缘膜也不容易发生静电损伤。另一方面，如图28所示，在与用于信号和电源电压的各键合焊盘类似，对应于未连接的I/O单元3c的键合焊盘(NC焊盘)BP由三个导体层(50b、60b和70b)构成的情况下，底层绝缘膜的厚度(l2)较小(l2＜l1)，因此，介于键合焊盘(NC焊盘)BP和半导体衬底1间的绝缘膜容易发生静电损伤。
图7是根据采用CAD的自动布局布线系统(设计自动化简称为DA)的布线形成工艺的流程图。下面简单介绍一下此工艺的大概情况。首先，设计构成栅阵列的逻辑电路，然后为检验逻辑功能操作进行逻辑模拟，直到确定最后的逻辑功能(700)。
随后，利用CAD技术，根据上述逻辑功能在X-Y格坐标系中自动布局布线、连接孔及键合焊盘的导体层。此时，根据NC管脚、电源电压管脚和信号管脚的信息(702)确定NC管脚(704)，并从NC焊盘上去掉除最上层外的导体层(706)。
然后，将自动布设于X-Y格坐标系中的布线和连接孔按三种尺寸分类(708)。即，根据自动布局布线系统的程序确定第一至第三层布线(50、60和70)、连接孔(接触孔12、通孔14和16)及导体层(50b、60b和70b)(710)。
然后，检查自动布局步骤形成的相对于连接图形的版图规则的任何偏差(712)。对偏差的检查确定了布线是否主要在晶片工艺中没有任何问题的情况下可以根据连接图形进行布局。在通过偏差的检查发现连接图形的故障时，替换这些图形，并再进行偏差的检查。
然后，根据自动布局布线系统的信息产生掩模图形(714)。所以下面说明的是根据自动布局布线系统(DA)的布线形成工艺的概况。此后，根据上述掩模图形信息，利用电子束平版印刷设备等形成两种光掩模，一种是形成有第一至第三布线层(50、60和70)和各导体层(50b、60b和70b)的图形的光掩模，另一种是形有连接孔(接触孔12、通孔14和16)图形的光掩模(716)。利用这些光掩模，在半导体衬底上形成第一至第三布线层(50、60和70)、连接孔(接触孔12、通孔14和16)和各导体层(50b、60b和70b)(718)。
下面将结合附图8-14简要说明制造CMOS栅阵列的工艺过程。
首先，如图8所示，提供半导体衬底1，其上根据已知CMOS工艺已预先形成了未示出的P沟MISFET Qp和N沟MOSFET，用CVD法(化学汽相淀积)在各MISFET上淀积氧化硅膜11。
然后，如图9所示，通过利用光刻胶作掩模的腐蚀，在覆盖每个电源电压输入单元3b的那部分氧化硅膜11上形成接触孔12。然后，通过溅射在氧化硅膜11上淀积Al(铝)合金膜并构图。于是，形成输入单元3b的第一布线层50、构成每个键合焊盘BP的第一导体层50b及连接它们的引出布线50a。此时，每个信号输入单元3a上皆覆盖有输入单元3a的第一布线层50(未示出)和构成键合焊盘BP的第一导体层50b。相反，如图10所示，在将形成未用的每个I/O单元3c的区域上不形成第一布线层50、第一导体层50b和引出布线50a中的任何一层。
然后，在半导体衬底1上CVD淀积氧化硅膜构成的第一层间绝缘膜13。然后，如图11所示，利用光刻胶作掩模进行腐蚀，在位于将形成键合焊盘BP的区域的那部分第一层间绝缘膜13上形成通孔14。随后，通过溅射在第一层间绝缘膜13上淀积Al合金膜并构图。于是，形成电源电压输入单元3b的第二布线层60、构成键合焊盘BP的第二导体层60b及连接它们的引出布线60a。此时，信号输入单元3a上覆盖有输入单元3a的第二布线层60及构成键合焊盘BP的第二导体层60b(未示出)。相反，如图12所示，在将形成未用的每个I/O单元3c的区域上不形成第二布线层60、第二导体层60b和引出布线60a中的任何一层。
随后，在半导体衬底1上CVD淀积氧化硅膜构成的第二层间绝缘15。然后，如图13所示，利用光刻胶作掩模进行腐蚀，在位于将形成键合焊盘BP的区域的那部分第二层间绝缘膜15上形成通孔16。随后，通过溅射在第二层间绝缘膜15上淀积Al合金膜并构图。于是，形成电源电压输入单元3b的第三布线层70、构成键合焊盘BP的第三导体层70b及连接它们的引出布线70a。此时，信号输入单元3a上覆盖有输入单元3a的第三布线层70及构成键合焊盘BP的第三导体层70b(未示出)。除此之外，如图14所示，在将形成未用的I/O单元3c的区域上形成构成键合焊盘BP的第三导体层70b和与之连接的引出布线70a。
图15是包封了形成有CMOS栅阵列的半导体芯片1A的QFP(方形扁平封装)的平面示意图，图16是展示形成包封于QFP中的半导体芯片1A的键合焊盘BP和I/O单元3的部分区域的放大平面示图，图17是展示形成NC焊盘BP的区域的半导体芯片1A的剖面图。图中数字20表示构成QFP的外部连接端的每根引线，数字21表示电连接引线20和半导体芯片1A的每根Au(金)丝，数字22表示由合成树脂构成的QFP的封装壳体。
如这些图所示，QFP是一种将许多Au丝21键合到所有半导体芯片1A的键合焊盘BP的封装，所说的键合焊盘中包括对应于未用的I/O单元3c的键合焊盘(NC焊盘)BP。即，在不考虑根据逻辑规范设置于半导体芯片1A的不同位置处的对应于未用I/O单元3c的键合焊盘的位置的情况下，进行引线键合。以此方式，所有不同逻辑规范的半导体芯片1A的引线键合步骤可以是相同的，因此，可以提高引线键合步骤的产出率。
图18和19分别是其上装有QFP的印刷布线电路板30的基本部分的平面图和剖面图。图中的符号20c表示与上布线层31或下布线层32相连的QFP的NC管脚，符号20a表示其信号管脚，符号20b表示其电源电压管脚。
如图所示，在印刷布线电路板30上安装QFP时，根据印刷布线电路板30的规格，印刷布线电路板30的上布线层31和下布线层32有时通过QFP的NC管脚22c电连接。例如，外围电路器件PH1、PH2和如RAM或ROM等存储器MC1通过NC管脚20C连接，由此可以增强布线设计的通用性。
这种情况下，有时过电压通过NC管脚20C加于半导体芯片1A的键合焊盘(NC焊盘)BP上。然而，根据本实施例的CMOS栅阵列，键合焊盘(NC焊盘)BP下的绝缘膜被加厚，所以可以有效防止对介于键合焊盘(NC焊盘)BP和半导体衬底1间的绝缘膜的静电损伤。除此之外，在NC管脚20C在这种连接情况下有二极管性能时，它构成了造成外围电路器件PH1、PH2和存储器MC1的误动作的因素，因此，不能配备保护电路。
(实施例2)
该实施例的半导体集成电路器件是一包括实施例1的CMOS栅阵列的微型计算机。
图20是包封了形成有微型计算机的半导体芯片1B的TCP(载带封装)的示意平面图，图21是形成包封于TCP中的半导体芯片1B的键合焊盘BP和I/O单元3的部分区域的放大平面图，图22是其剖面图。图中的数字23表示TCP的绝缘带(聚酰亚胺带)，数字24表示形成于绝缘带23的一个表面上的每个引线，25表示形成于半导体芯片1B的键合焊盘BP上的每个Au(金)突点电极。
如这些图所示，TCP是一种将引线24键合于半导体芯片1B的所有键合焊盘BP上的封装，所说所有键合焊盘中包括对应于未用的I/O单元3c的键合焊盘(NC焊盘)BP。即，在不考虑根据逻辑规范设置于半导体芯片1B的不同位置处的对应于未用I/O单元3a的键合焊盘的位置，进行引线24的键合。以此方式，可以节省制造不同逻辑规范的单个半导体芯片1B中的不同绝缘带23引线图形的劳动，并可以节省花在带设计上的时间和制造带的步骤，从而削减制造TCP的成本。
尽管以上结合实施例对本发明人的发明进行了准确描述，但显然本发明不限于上述实施例，在不背离本说明书的支持的范围内可以进行不同替换。
上述实施例中，是参考具有三层布线的CMOS阵列进行说明的。然而，本发明也适用于有四层或更多层布线的栅阵列、包括该栅阵列的微型计算机等等。例如，如图23和24右边部分所示，在有五层布线的CMOS栅阵列中，对应于未用的I/O单元的每个NC焊盘BP(NC)只由最上层导体层构成(第五层导体层90b)，所以可以增强NC管脚的抗静电损伤强度。这种情况下，对应于除未用I/O单元之外的I/O单元的每个键合焊盘BP例如由五个导体层构成(第一导体层50b至第五导体层90b)(图23中左边部分所示)或三个导体层构成(第三导体层70b至第五导体层90b)(图24中左边部分所示)。
或者，对应于未用的I/O单元的每个NC焊盘BP可以形成有包括与最上层布线相同的导体层的几个导体层，且其数量小于对应于与未用I/O单元不同的I/O单元的每个键合焊盘的导体层数。图25展示了由两个导体层(第四导体层80b和第五导体层90b)构成的NC焊盘BP(NC)，而其它焊盘BP由五个导体层(第一导体层50b至第五导体层90b)构成。此外，图26展示了由三个导体层(第三导体层70b、第四导电导层80b和第五导体层90b)构成的NC焊盘BP(NC)，其它键合焊盘BP由五个导体层(第一导体层50b至第五导体层90b)构成。如些实施例所述，在每个NC焊盘BP(NC)由多个导体层构成的情况下，NC焊盘BP(NC)的强度提高，因此其与Au(金)丝的键合能力增强。
包封形成有本发明逻辑LSI的半导体芯片的封装不限于引线键合式(实施例1)或TCP式(实施例2)。例如，本发明可以应用于图27所示的封装，其中通过形成于半导体芯片1A键合焊盘BP上的焊料突点26，半导体芯片1A安装成印刷布线电路板33上的倒装芯片。这种情况下，包括NC焊盘的所有半导体芯片1A的键合焊盘BP皆形成有焊料突点26。以此方式，可以节省在不同逻辑规范的各半导体芯片1A的不同位置处形成焊料突点26的劳动，所以可以削减制造封装的成本。
尽管每个实施例皆参考了包括栅阵列的半导体集成电路器件，但本发明也可以应用于包括各种专用IC的半导体集成电路器件，例如嵌埋式阵列和单元基IC。本发明还可扩展应用于每个具有至少两层的多层布线的母片法半导体集成电路器件，其中的布线皆由自动布局布线系统布设。
下面简单说明一下本发明效果。
根据本发明，对应于未用的I/O单元的每个NC焊盘下的绝缘膜皆被加厚，所以可以增强NC管脚的抗静电损伤强度。而且，不同逻辑规范的半导体芯片间，键合焊盘与封装的外部连接端的连接可以相同，所以可以降低制造封装的成本。

Claims (20)

1.一种半导体集成电路器件，包括：对应于根据逻辑规范将采用的I/O单元的第一键合焊盘，每个第一键合焊盘由多个导体层构成；及对应于根据逻辑规范将不被采用的I/O单元的第二键合焊盘，每个第二键合焊盘由包括与多个导体层中最上层布线相同的导体层的至少一层导体层构成，且导体层数小于构成各所述第一键合焊盘的所述多个导体层的数目。
2.如权利要求1的半导体集成电路器件，其中逻辑集成电路中至少电源电压输入单元和与之对应的键合焊盘通过多个布线层电连接。
3.如权利要求1的半导体集成电路器件，其中输入保护电路形成于将采用的每个I/O单元的前一级，而不形成于将不被采用的I/O单元的前一级。
4.如权利要求1的半导体集成电路器件，其中各第二所说键合焊盘只由作为所说最上层布线的所述同一导体层构成。
5.如权利要求1的半导体集成电路器件，其中布设三层布线，每个第二所说键合焊盘只由与三个布线层中的第三布线层相同的导体层构成，每个第一所说键合焊盘由这三层导体层构成。
6.如权利要求1的半导体集成电路器件，其中所述半导体集成电路器件通过采用栅阵列设计构成。
7.一种封装，其中，如权利要求1的半导体集成电路器件和引线通过金属丝电连接，并被包封，其中各金属丝与包括第二所说键合焊盘的所有所说键合焊盘相连。
8.一种封装，其中，如权利要求1的半导体集成电路器件和引线通过突点电极电连接，并被包封，其中各引线与包括第二所说键合焊盘的所有所说键合焊盘相连。
9.如权利要求1的半导体集成电路器件，其中介于第二所说键合焊盘和半导体衬底间的绝缘膜的厚度大于介于所说第一键合焊盘和半导体衬底间的绝缘膜的厚度。
10.一种半导体集成电路器件，包括：
形成于半导体衬底主表面上的绝缘膜；
覆盖于所说绝缘膜上的第一键合焊盘，它们分别对应于将不被采用的各输入/输出单元；及
覆盖于所说绝缘膜上的第二键合焊盘，它们分别对应于除将不被采用的各输入/输出单元之外的输入/输出单元；
主表面和所说第一键合焊盘间的绝缘膜厚于所说主表面和所说第二键合焊盘间的绝缘膜。
11.如权利要求10的半导体集成电路器件，其中每个所说第一键合焊盘由层数小于每个所说第二键合焊盘的导体层数的导体层构成。
12.如权利要求10或11的半导体集成电路器件，其中所说第一键合焊盘和引线分别电连接构成未连接的管脚。
13.如权利要求10或12的半导体集成电路器件，其中所说半导体集成电路器件采用栅设计构成。
14.一种电子器件，包括包封了权利要求10的所说半导体集成电路器件和多根引线的第一半导体封装，以及第二半导体封装及印刷布线电路板；
所说第一键合焊盘和所说引线分别电连接构成未连接的管脚；
所说第二半导体封装的未连接的管脚和信号管脚电连接于所说印刷布线电路板的布线上。
15.如权利要求10半导体集成电路器件，其中电源电压被加在所述第二键合焊盘上。
16.如权利要求15的半导体集成电路器件，其中每个所说第一键合焊盘由层数小于每个所说第二键合焊盘的导体层数的导体层构成。
17.如权利要求16的半导体集成电路器件，其中所说第一键合焊盘和引线分别电连接构成未连接的管脚。
18.如权利要求10半导体集成电路器件，其中所述第二键合焊盘被电连接到信号输入/输出单元。
19.如权利要求18的半导体集成电路器件，其中每个所说第一键合焊盘由层数小于每个所说第二键合焊盘的导体层数的导体层构成。
20.如权利要求19的半导体集成电路器件，其中所说第一键合焊盘和引线分别电连接构成未连接的管脚。
CNB981147372A 1997-06-13 1998-06-12 半导体集成电路器件 Expired - Fee Related CN1169216C (zh)

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