CN116884946A - 嵌入式的无通孔桥接 - Google Patents

嵌入式的无通孔桥接 Download PDF

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CN116884946A
CN116884946A CN202310814085.6A CN202310814085A CN116884946A CN 116884946 A CN116884946 A CN 116884946A CN 202310814085 A CN202310814085 A CN 202310814085A CN 116884946 A CN116884946 A CN 116884946A
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substrate
horizontal
embedded
microelectronic
conductors
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贝尔格森·哈巴
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Adeia Semiconductor Technologies LLC
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Invensas LLC
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Abstract

本揭示所提供的是嵌入式的无通孔桥接。在实作中，在三维桥接部件中含有多个传导线路或导线的离散部件被嵌入于在主要基板中于主要基板的表面下方提供由讯号、电力和电性接地导线所组成的密集数组所需要的地方。到达主要基板的表面平面的垂直传导竖管亦被包括在离散部件中，用以连接至基板的表面上的晶粒，并且因而经由在离散部件中的由导线所组成的密集数组将晶粒彼此互连。要被嵌入的离散部件本身可具有呈规则间隔的由导体所组成的平行平面，且因而可呈现出均匀地覆盖有垂直导体的末端的工作表面，垂直导体可用于将表面构件彼此连接并且沿着嵌入式部件将表面构件连接至在多个地方处的接地和电力。

Description

嵌入式的无通孔桥接
本申请是申请日为2016年12月5日，优先权日为2015年12月14日，申请号为201680069890.9的发明专利申请的分案申请。
背景技术
随着微电子构件变得更小，必须缩小更多的布线和更多的讯号迹线以适配于封装基板的愈来愈小的表面区域覆盖区。这个趋势已导致在习知基板的表面上有非常细的传导线路和高密度的布线。但是当迹线非常细时会影响讯号精确度。当线路之间的间距为了表面平面上的高密度互连而非常细时，也可能发生干扰和其它衰减。除了讯号层，亦可能需要在基板的相同水平面上实施电力和电性接地的连接。当基板的该面积“占用配置(realestate)”变得拥挤时，可能存在有将高的导体数目集中在基板的给定顶部表面或底部表面上的理论极限。需要用以在基板的给定顶部或底部表面区域上达成高密度的传导迹线的习知的小型化制程亦是昂贵的。
发明内容
本揭示描述嵌入式的无通孔桥接。在实作中，在三维桥接中含有多个传导线路或导线的离散部件被嵌入于在主要基板中于主要基板的表面下方提供由讯号、电力和电性接地导线所组成的密集数组所需要的地方。到达主要基板的表面平面的垂直传导竖管亦被包括在离散部件中，用以连接至基板的表面上的晶粒且因而经由在离散部件中的由导线所组成的密集数组将晶粒彼此互连。要被嵌入的离散部件本身可具有呈规则间隔的由导体所组成的平行平面，且因而可呈现出均匀地覆盖有垂直导体的末端的工作表面，垂直导体可用于将表面构件彼此连接并且沿着嵌入式的部件连接至在多处的接地和电力。
本发明内容并不旨在指明所要求保护的主题的关键或必要特征，也不旨在使用以作为限制所要求保护的主题的范围的辅助。
附图说明
将在下文参考随附图式而描述本揭示的某些实施例，其中相同参考数字表示相同组件。然而，应该理解的是，随附图式解释在此处所描述的各种实作并且不打算限制在此处所描述的各种技术的范围。
图1是包括由导体所组成的整合式密集数组用以互连微电子装置而可嵌入作为主要第一基板中的第二基板的范例性无通孔桥接部件的示意图。
图2是被嵌入于第一基板中以互连晶粒的图1的范例性第二基板和无通孔桥接部件的示意图。
图3是由多个范例性第二基板的实例所提供的范例性讯号层和范例性电力或接地层的示意图。
图4是用以嵌入包括由导体所组成的整合式密集数组的范例性第二基板作为用于微电子装置的第一基板中的讯号层的多个制造阶段的示意图。
图5是用以嵌入包括由导体所组成的整合式密集数组的范例性第二基板作为用于微电子装置的第一基板中的电力或接地层的多个制造阶段的示意图。
图6是嵌入第二基板在用于微电子装置的第一基板中以在第一基板的表面之下提供由宽导线所组成的密集数组来互连微电子装置的范例性方法的流程图。
具体实施方式
本揭示描述范例性嵌入式的无通孔桥接。在实作中，在三维桥接部件中含有多个传导线路或导线的离散部件被嵌入于在主要基板中于主要基板的表面下方提供由讯号、电力和电性接地导线所组成的密集数组所需要的地方。当离散部件中的传导线路被嵌入于主要基板的表面之下时，到达主要基板的表面平面的垂直导体或“竖管(riser)”亦被包括在离散部件中，例如，用以连接至基板表面上的晶粒和它们的衬垫且因而经由在离散部件中的由导线所组成的密集数组将晶粒彼此互连。要被嵌入的离散部件本身可具有呈规则间隔的由导体所组成的平行平面，且因而可呈现出均匀地覆盖有垂直导体的末端的工作表面，垂直导体可用于将表面构件彼此连接并且沿着被嵌入的部件将表面构件连接至在多个地方的接地和电力。
插入或嵌入范例性离散部件(其将晶粒彼此连接)解决了互连要非常高密度的需求，而不需要采用习知基板的水平顶部表面上所必需的非常细线路外形。范例性嵌入式的无通孔桥接可(举例而言)替3D-ICs提供一种能够在利用垂直度的密集数组中放置连接的能力，而没有被习知细间距或高密度导线接合的设计所强加的严格周长限制。
在范例性离散部件(以下称“第二基板”或“嵌入式基板”)中的由导体所组成的密集数组是被制作以与离散部件(或第二基板)整合。因为含有导体的第二基板是在主要基板(第一基板)的形成期间被嵌入，所以没有建立通孔的需要，亦即(举例而言)在主要基板中藉由钻孔所制成的个别垂直孔洞。习知通孔的建立是因此藉由在此处所描述的嵌入式的无通孔桥接的范例性系统而被避免。
因为嵌入式基板的嵌入式导体可利用深度，并且不仅限于只在主要基板的表面平面，所以嵌入式基板部件的个别导线或迹线与可能要用以传统的方式连接晶粒的非常细的表面迹线相比可以是更宽和/或更厚的。被嵌入在主要基板的表面之下的范例性第二基板中的较宽迹线与习知基板的表面上的习知细迹线和导线绕线相比，提供更可靠的操作、更高的信号精确度、较高的电流、电压以及电力运载能力。再者，嵌入式第二基板的较宽迹线和导线的实现与习知高密度表面迹线相比更便宜。
含有要被嵌入的传导线路的第二基板或离散桥接部件可用多种厚度被制成，并且同样也可被嵌入在不同深度处，甚至是在相同的主要基板内。举例而言，因为第二基板可在制造的时间点被嵌入，所以第二基板和传导线路可被建立在基板的核心内部或作为核心本身的一部分。另一方面，在实作中，含有传导线路的薄形第二基板可被嵌入在基板的外层中，甚至是在诸如基板的外部介电层或其他外层的额外层中。
范例性嵌入式第二基板可具有多个垂直传导竖管以到达主要基板的表面平面。这可允许沿着线路延伸以在多个表面位置处表面连接至给定嵌入式线路。根据嵌入式第二基板的结构，可能有多个由垂直竖管所组成的垂直平面，以用于讯号、电力和电性接地。在实作中，这可在主要基板的表面上在多个地方处连接至的想要的嵌入式线路。
作为制造优势，第二基板可在不需要过度考虑表面公差的情况下被嵌入。第二基板的范例嵌入件可允许一部分的第二基板从主要基板的表面突出或“伸出”。因为仅有第二基板的垂直竖管到达此主要基板的表面平面，所以基板的表面可在不需要考虑到在抛光期间减去多少嵌入式第二基板的叠层厚度的情况下用便宜的方式被研磨或抛光。无论主要基板表面的最终布置如何，垂直竖管皆为它们的嵌入式传导线路提供相同的路径。这是与研磨会剥离、括伤或破坏表面迹线的习知做法进行对比。在此处的范例性系统中，在主要基板的表面平面处可取用的第二基板的仅有导体是垂直竖管，垂直竖管可藉由抛光它们在不损坏的情况下来缩短。
具有整合式电性导体的第二基板可相对于第一基板以一角度(诸如，90度或其他各种角度)被嵌入，以便取代非常细的习知表面导体以及此类习知表面导体的细间距的绕线。
第二基板可以由印刷电路板(PCB)材料、玻璃、环氧树脂、复合材料、FR-4、塑料、聚合物、玻璃强化的环氧树脂层合物薄片、具有环氧树脂黏合剂的编织玻璃纤维布等等所构成。在实作中，由平行导体所组成的平面是在第二基板自身的制造期间被嵌入在第二基板中。
代替了被放置在基板表面(且平行于该表面)的顶部上的非常细且非常高密度的习知布线，嵌入式第二基板(其具有相对于主要基板的表面旋转90度的由导体所组成的平面)含有垂直导体，其利用嵌入物的深度来让想要的布线与互连有较宽的导线以及坚固的平行电力和电性接地面。这些坚固的垂直导体可在与习知布局相同或较小的覆盖区中将表面构件与较佳的导体连接，从而取代习知高密度表面布线和习知精细间隔的线路。
因为嵌入式导体可利用垂直维度以在主要基板的表面之下具有多个平面的水平和垂直导体，所以嵌入式第二基板可利用较佳的导体制造更好的连接，并且与习知基板表面上的习知细线路和高密度布线相比可桥接更小的构件。再者，范例性嵌入式基板是明显地比习知细传导线路便宜，同时提供更高密度的布线连接。
图1示出具有整合式导体102的范例第二基板100。在实作中，要被嵌入有其整合式导体102的第二基板可以由多个层所组成，或是由所选择的基板材料所制成的多个平板104所组成，其插入有与基板材料整合(并且因此无通孔)的由导体102所组成的多个平行平面。
在实作中，具有整合式导体102的可嵌入的第二基板100的范例可以藉由以下来制成：将彼此平行的导体排列在介电材料、绝缘层、绝缘体平板或其他合适的基板材料的一或多个平坦表面上；堆栈或穿插多个此类平板；接合平板与经插入的导体，以汇整出具有内置平行导体的平面的层合块体；以及接着与平行导体呈90度切割层合块体，以形成具有无通孔的嵌入式垂直导体的基板，用以桥接微电子装置的构件。在实作中，范例性第二基板100的每一层是平板104，其具有传导通过平板104的传导迹线102。
图2示出在微电子封装的主要基板200中的可嵌入式第二基板100和100’的范例性嵌入件。在此范例中，第二基板100和100’是被嵌入在主要基板200中相对浅的外层202中。第二基板200可被嵌入更深，举例而言在基板200的核心中，或作为核心本身的一部分。第二基板100和100’的垂直导体204在主要基板200的顶部表面上提供电性接点或衬垫。第二基板100和100’在晶粒之间提供桥接连接，诸如被安装在主要基板200表面上的晶粒206和208以及晶粒208和210。每一个第二基板100(或离散部件)藉由在主要基板的表面下方的高密度布线将晶粒(诸如晶粒206和208)彼此连接。
图3示出具有连接主要基板200表面上的晶粒206和208的整合式的嵌入式导体102的范例第二基板100的嵌入。嵌入式第二基板100可提供高密度的传导线路102或讯号层302导线以连接晶粒(例如，206和208)。嵌入式第二基板100亦可与在主要基板200中的导体304连接，因而与主要基板100的相对侧(例如，底部)进行通信。给定第二基板100可选择性地仅嵌入于主要基板200上制作互连所需要的地方。
嵌入式第二基板100’亦可提供电力或电性接地层306(或两者)给晶粒206和208，并且一般而言可接连至主要基板200的表面上的电力和接地导体308。具有整合式导体102的给定嵌入式第二基板100亦可在主要基板100的表面之下提供电性总线(electricalbus)或高密度的电性轭(electrical yoke)。嵌入式第二基板100亦可取代或构成微电子封装的再分布层或扇入/扇出区域的部分。
图4示出嵌入范例性可嵌入的基板100以在主要基板200内提供讯号层的多个范例性阶段。首先选择合适的基板材料以用于主要基板200。主要基板200的挖除(displacement)402可被规划在制程中，用以嵌入可嵌入的第二基板100。主要基板的表面平面和嵌入式第二基板100可被抛光(polished)或研磨(lapped)以实现平坦性404，如同上面所述的。传导衬垫406、球、导体等等可(举例而言)藉由焊接被添加至嵌入式第二基板100的垂直导体204的暴露末端，用以与晶粒206和208连接。
图5示出嵌入范例性可嵌入的基板100以在主要基板200内提供电力或电性接地层(或两者)的多个范例性阶段。在实作中，可嵌入的第二基板100被切割出或被形成，并且黏着剂可在一实作中被使用以将可嵌入的基板100接合至主要基板200。如果嵌入式基板100的顶部突出于主要基板200的表面平面上方，则整个表面可被加以研磨或抛光而达到平坦性404。电力总线504或线路(或接地总线或线路)可被连接至嵌入式基板100的导体102。传导衬垫406、球、导体等等可(举例而言)藉由焊接被添加至暴露的电力或接地总线504，用以与晶粒206和208连接。
范例性方法
图6示出在用于微电子装置的第一基板中嵌入第二基板以在第一基板的表面之下提供由宽导线所组成的密集数组而互连微电子装置的范例性方法600。在图6的流程图中，范例性方法600的操作是被示于个别区块中。
在区块602，第二基板(其包括由导体所组成的密集数组)是被嵌入于用于微电子装置的第一基板中。
在区块604，微电子装置藉由将微电子装置附接到嵌入式第二基板的垂直导体而互连，垂直导体与嵌入式第二基板中的由导体所组成的密集数组进行通信。
在范例性方法600中，嵌入式第二基板可包括与嵌入式第二基板整合的电性导体，以提供无通孔的嵌入式第二基板。
范例性方法600可进一步包括在制造期间嵌入第二基板在第一基板的核心内部或作为第一基板的核心的一部分。
范例性方法600可进一步包括以浅层的方式嵌入第二基板在第一基板的外层中，或是以更深的方式嵌入在第一基板中，例中在第一基板的核心内部或作为第一基板的核心的一部分。
嵌入可包括施加黏着剂以将嵌入式第二基板(其包括由导体所组成的密集数组)接合至第一基板。
嵌入第二基板在第一基板中可使第二基板突出于第一基板的表面平面上方；以及范例性方法600可包括研磨或抛光第二基板和第一基板至与第一基板一致的平坦性，其中垂直导体在不同研磨或抛光的深度处仍可取用。
范例性方法600可包括在第二基板中整合多个宽导线以构成由导体所组成的密集数组，并且嵌入第二基板在第一基板中以取代第一基板中的非常细路外形的表面迹线。
范例性方法600可进一步包括在第二基板的不同深度整合多个宽导线，以提供由导体所组成的密集数组。
传导衬垫或球可被附接至垂直导体，用以将晶粒连接至垂直导体。
范例性方法600可包括嵌入包括由导体所组成的密集数组的第二基板在第一基板中，以互连第一基板的顶部表面和底部表面。
范例性方法600亦可包括以不同深度嵌入多个第二基板在相同的第一基板中，以在第一基板的表面平面之下提供讯号、电力和接地层。
在说明书和随附的权利要求书中：用语“将…连接(connect)”、“连接(connection)”、“被连接(connected)”、“与…连接(in connection with)”和“其连接…(connecting)”是用来表示“与...直接连接(in direction connection with)”或“通过一个或多个组件与…连接(in connection with via one or more elements)”；并且，用语“集合(set)”是用来表示“一个组件(one element)”或“一个以上的组件(more than oneelement)”。再者，用语“将...耦合(couple)”，“其耦合...(coupling)”，“被耦合(coupled)”，“耦合在一起(coupled together)”和“与…耦合(coupled with)”是被用来表示“直接耦合在一起(directly coupled together)”或“通过一个或多个组件耦合在一起(coupled together via one or more elements)”。如在此处所使用的，用语“上(up)”和“下(down)”、“上方(upper)”和“下方(lower)”、“向上(upwardly)”和“向下(downwardly)”、“上游(upstream)”和“下游(downstream)”、“上面(above)和下面(below)”以及表示在一给定点或组件上面或下面的相对位置的其他类似的用语是在此描述中被使用以更清楚地描述本揭示的一些实施例。
虽然已相对于有限数目的实施例来揭露本揭示，但是该领域中习知此技术者在领会本揭示的优势后将知道由此所做出的许多修改和变化。随附的权利要求书意图如同落入本揭示的真实精神和范围内那样涵盖此些修改和变化。

Claims (14)

1.一种微电子构件，其包括：
第一基板，其用于微电子装置，所述第一基板具有第一侧和相对的第二侧；
第二基板，其用于电连接所述微电子装置，所述第二基板包括：
平行且交错的导体层和绝缘体层的层合物堆叠；以及
水平讯号线路，其被嵌入于所述绝缘体层中，其中：
所述第二基板被嵌入于所述第一基板的所述第一侧中；
所述第一基板与所述第二基板定义水平基板表面；
所述交错层垂直于所述水平基板表面；
所述水平讯号线路平行于所述水平基板表面；
所述水平讯号线路通过设置在其间的所述绝缘体层的部分与所述水平基板表面分开；以及
所述导体层在所述水平基板表面和所述第二基板的平行底表面之间延伸以形成多个垂直导体。
2.如权利要求1所述的微电子构件，其中所述导体层中的两个或更多个导体层各自包括多个个别的垂直导体。
3.如权利要求2所述的微电子构件，其中所述多个垂直导体和所述水平讯号线路互连以提供嵌入所述第一基板中的无通孔桥接。
4.如权利要求3所述的微电子构件，其中所述无通孔桥接通信地连接设置在所述水平基板表面上的两个或更多个微电子装置。
5.如权利要求1所述的微电子构件，其中：
所述导体层中的一个或多个导体层包括多个个别的垂直导体；以及
所述个别的垂直导体中的一个或多个垂直导体经由设置在其间的导电互连与所述第一基板的所述第二侧电通信。
6.如权利要求1所述的微电子构件，其中所述水平讯号线路共同地提供经由所述垂直导体从所述水平基板表面可取用的高密度的讯号传导层。
7.如权利要求1所述的微电子构件，其中所述导体层中的一个或多个导体层包括垂直接地或电力平面。
8.如权利要求1所述的微电子构件，其中所述第二基板包括用于互连所述第一基板的部分及/或所述微电子装置的封装的再分布层。
9.一种制造微电子构件的方法，所述微电子构件包括用于微电子装置的第一基板以及用于电连接所述微电子装置的第二基板，所述第一基板具有第一侧和相对的第二侧，所述方法包括：
通过以下方式制造所述第二基板：
布置平行且交错的导体层和绝缘体层的层合物堆叠；
将水平讯号线路嵌入所述绝缘体层中；以及
将所述第二基板嵌入所述第一基板的所述第一侧中，其中：
所述第一基板与所述第二基板定义水平基板表面；
所述交错层垂直于所述水平基板表面；
所述水平讯号线路平行于所述水平基板表面；
所述水平讯号线路通过设置在其间的所述绝缘体层的部分与所述水平基板表面分开；以及
所述导体层在所述水平基板表面和所述第二基板的平行底表面之间延伸以形成多个垂直导体。
10.如权利要求9所述的方法，其进一步包括施加粘着剂，以将所述第二基板接合至所述第一基板。
11.如权利要求9所述的方法，其进一步包括
研磨或抛光所述第二基板和所述第一基板以定义所述水平基板表面。
12.如权利要求9所述的方法，其进一步包括将所述水平讯号线路嵌入所述绝缘体层中的不同深度处。
13.如权利要求9所述的方法，其进一步包括将传导衬垫或球附接至所述垂直导体，用以将微电子装置连接至所述垂直导体。
14.如权利要求9所述的方法，其进一步包括嵌入多个所述第二基板在所述第一基板中的不同深度处。
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US10083909B2 (en) 2018-09-25
US20190019754A1 (en) 2019-01-17
US10347582B2 (en) 2019-07-09
KR20220066185A (ko) 2022-05-23
US20180108612A1 (en) 2018-04-19
KR102397319B1 (ko) 2022-05-11
WO2017105893A1 (en) 2017-06-22
CN108369937A (zh) 2018-08-03
US20170170121A1 (en) 2017-06-15
US9852994B2 (en) 2017-12-26
KR20180084839A (ko) 2018-07-25
TW201732960A (zh) 2017-09-16

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