CN116631953A - 半导体封装体及其制造方法 - Google Patents

半导体封装体及其制造方法 Download PDF

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Publication number
CN116631953A
CN116631953A CN202310495529.4A CN202310495529A CN116631953A CN 116631953 A CN116631953 A CN 116631953A CN 202310495529 A CN202310495529 A CN 202310495529A CN 116631953 A CN116631953 A CN 116631953A
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semiconductor chip
support
wall
semiconductor
semiconductor package
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Inventor
稻冈俊幸
吉川雄一郎
浦辻淳广
吉光克司
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Rely On Technology Japan Co
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Rely On Technology Japan Co
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    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

本发明的目的是提供减小密封树脂的体积、即使半导体芯片的厚度、相邻的半导体芯片间的距离窄小也容易进行树脂填埋的半导体封装体、以及最终产品不含支承用平板的薄型的半导体封装体。一种半导体封装体，其特征在于，具有在支承体的凹腔部内收纳了半导体芯片的结构，所述支承体包含镀铜层，且具有容纳半导体芯片的所述凹腔部。

Description

半导体封装体及其制造方法
技术领域
本发明涉及半导体封装体及其制造方法，更详细而言，涉及以大型的面板尺度进行薄膜布线工序和组装工序的、具有Panel Level Package(板级封装，以下称为PLP)结构的半导体封装体及其制造方法。
背景技术
伴随着近年来的电子设备的高功能化和轻薄短小化的要求，电子部件的高密度集成化、进而高密度安装化发展起来，在这些电子设备中使用的半导体装置胜过以往地不断推进着小型化。
在专利文献1中记载了以电子部件的高密度化、轻薄短小化为目的的半导体封装体的制造方法的例子。
在图4中示出专利文献1中记载的半导体装置的基本结构，并且以下对该半导体装置进行说明。
半导体装置20具备由树脂固化体或金属构成的支承板1，在其一个主表面上使元件电路面(表侧的面)朝上来配置半导体芯片2，与元件电路面相反侧的面(背侧的面)通过粘接剂3固定在支承板1上。并且，在支承板1的主表面整体以覆盖半导体芯片2的元件电路面的方式形成有仅一层的绝缘材料层4。在该单层的绝缘材料层4之上形成有由铜等导电性金属构成的布线层5，其一部分被引出到半导体芯片2的周边区域。另外，在形成于半导体芯片2的元件电路面上的绝缘材料层4中，形成有将半导体芯片2的电极焊盘(electrode pad)与布线层5电连接的导电部(通路部)6。该导电部6与布线层5共同地形成从而被一体化。另外，在布线层5的规定的位置，形成有多个作为外部电极的焊料球7。进而，在绝缘材料层4之上、以及除了焊料球7的接合部以外的布线层5之上，形成有布线保护层(阻焊层)8。
基于图5来说明以往的PLP的制造方法。
图5所示的图是表示制造在一个封装体中装载有3个半导体芯片2的封装体的方法的概要的图。再者，实际上在大尺寸的面板上会同时组装多个封装体，但在图5中仅示出了一个封装体。
封装体的制造方法包括下面的(A)、(B)和(C)工序。
(A)半导体元件装载工序(参照图5A)
在由树脂固化体、或者不锈钢、42号合金等的金属构成的支承板1的一个主表面上，采用粘接剂以使元件电路面朝上的方式来固定半导体元件2。
(B)密封工序(参照图5B)
用绝缘树脂4密封支承体1的半导体元件2装载面。
(C)布线层形成工序(参照图5C)
形成采用通路导体6与半导体芯片2的电极进行了通路连接的布线层5。
在先技术文献
专利文献
专利文献1：日本特开2010－219489号公报
发明内容
在图4所示的以往的PLP中，由于在附有支承板1的状态下成为最终产品，因此当半导体芯片2的装载率变高时，存在在制造中发生面板翘曲、干扰到PLP的制造装置的问题。
另外，当半导体芯片2的厚度厚、且相邻的半导体芯片2间的距离变近时，存在绝缘树脂没有进入到其间的问题。而且，当为了改善该问题而使树脂材料厚度变厚时，存在不能实现半导体封装体本身的薄型化的问题。
而且，当半导体芯片的厚度变厚时，由于支承板1与布线层5之间的距离变长，因此存在用于将支承板1与布线层5连接的使用激光的通路开孔加工、和通过镀铜进行的连接变得困难的问题。
本发明的目的是提供减小密封树脂的体积，即使半导体芯片的厚度、相邻的半导体芯片间的距离狭窄也容易进行树脂填埋的半导体封装体、以及提供最终产品不含支承用平板的薄型的半导体封装体。
本发明人发现，通过制成向利用镀铜层形成的凹腔部埋入半导体芯片的结构，能够解决上述的课题，从而完成了本发明。
即，本发明涉及以下记载的半导体封装体及其制造方法。
(1)一种半导体封装体，其特征在于，具有在支承体的凹腔部内收纳了半导体芯片的结构，所述支承体包含镀铜层，且具有容纳半导体芯片的所述凹腔部。
(2)根据上述(1)所述的半导体封装体，为了避免半导体芯片装载夹具与形成所述凹腔部的凹腔壁之间的干扰而使所述凹腔的高度低于半导体芯片的高度。
(3)根据上述(1)所述的半导体封装体，半导体封装体的外周部的凹腔壁具有上部扩大的台阶部，为了避免半导体芯片装载夹具与所述凹腔壁之间的干扰而使该台阶部的高度低于半导体芯片的高度。
(4)一种半导体封装体，其特征在于，具备：
支承体；
半导体芯片，其介由粘接层以使元件电路面朝上的方式装载在所述支承体的一个面上；
绝缘材料层，其将所述半导体芯片及其周边密封；
开口，其在所述绝缘材料层上形成于配置于所述半导体芯片的所述元件电路面上的电极上方；
导电部，其以与所述半导体芯片的所述电极连接的方式形成于所述开口内；
布线层，其以与所述导电部连接的方式形成于所述绝缘材料层上，且一部分延伸到所述半导体芯片的周边区域；和
形成于所述布线层上的外部电极，
所述支承体由在所述一个面具有能容纳半导体芯片的凹腔部的镀铜体构成，半导体芯片被收纳于所述凹腔部内，
在所述支承体的另一个面具有绝缘材料层。
(5)一种半导体封装体的制造方法，其特征在于，依次包括以下各工序：
在支承用平板的一个主表面层叠铜箔的工序；
通过电镀在所述铜箔上形成镀铜层的工序；
通过电镀在所述镀铜层上形成凹腔部的工序；
利用粘接剂在所述凹腔部中固定半导体芯片的与元件电路面相反侧的面的工序；
用绝缘树脂对所述半导体芯片进行树脂密封从而形成密封树脂层的工序；
在所述绝缘材料层上，在配置于所述半导体芯片的所述元件电路面上的电极的上方的位置形成开口的工序；
在所述绝缘材料层上形成一部分延伸到所述半导体芯片的周边区域的布线层，并且，在所述绝缘材料层的所述开口内形成与所述半导体芯片的所述电极连接的导电部的工序；
在所述布线层上留有开口部地形成阻焊层的工序；
在所述开口部的布线层上形成外部电极的工序；
从所述铜箔分离所述支承用平板的工序；和
在进行分离后的铜箔上形成绝缘材料层的工序。
(6)一种半导体封装体的制造方法，所述半导体封装体具有支承用平板，该制造方法的特征在于，依次包括以下各工序：
在所述支承用平板的一个主表面层叠铜箔的工序；
通过电镀在所述铜箔上形成镀铜层的工序；
通过电镀在所述镀铜层上形成凹腔部的工序；
利用粘接剂在所述凹腔部中固定半导体芯片的与元件电路面相反侧的面的工序；
用绝缘树脂对所述半导体芯片进行树脂密封从而形成密封树脂层的工序；
在所述绝缘材料层上，在配置于所述半导体芯片的所述元件电路面上的电极的上方的位置形成开口的工序；
在所述绝缘材料层上形成一部分延伸到所述半导体芯片的周边区域的布线层，并且，在所述绝缘材料层的所述开口内形成与所述半导体芯片的所述电极连接的导电部的工序；
在所述布线层上留有开口部地形成阻焊层的工序；和
在所述开口部的布线层上形成外部电极的工序。
(7)根据上述(5)或(6)所述的半导体封装体的制造方法，其特征在于，所述凹腔部是通过采用使用了抗蚀剂的图案镀敷来形成没有析出镀铜层的部分而形成的。
(8)一种半导体封装体的制造方法，其特征在于，依次包括以下各工序：
对支承用平板的两面的每一面实施
层叠铜箔的步骤、
通过电镀在所述铜箔上形成镀铜层的步骤、
通过电镀在所述镀铜层上形成凹腔部的步骤、
利用粘接剂在所述凹腔部中固定半导体芯片的与元件电路面相反侧的面的步骤、
用绝缘树脂对所述半导体芯片进行树脂密封从而形成密封树脂层的步骤、
在所述绝缘材料层上，在配置于所述半导体芯片的所述元件电路面上的电极的上方的位置形成开口的步骤、
在所述绝缘材料层上形成一部分延伸到所述半导体芯片的周边区域的布线层，并且，在所述绝缘材料层的所述开口内形成与所述半导体芯片的所述电极连接的导电部的步骤、
在所述布线层上留有开口部地形成阻焊层的步骤、和
在所述开口部的布线层上形成外部电极的步骤，
从而在支承用平板的两面的每一面形成封装部，并将所述支承用平板从每个所述封装部的铜箔分离，得到两个封装部的工序；和
在所述两个封装部的铜箔上形成绝缘材料层的工序。
本发明的半导体封装体获得了以下效果。
·由于在具有凹腔部的包含镀铜层的支承体的凹腔部中收纳半导体芯片，因此用密封树脂进行密封的体积变小，即使半导体芯片的厚度、相邻的半导体芯片间的距离窄小，树脂埋入也变得容易。
·由于最终产品成为用包含镀铜层的支承体支承的结构，因此用通常的层间连接通路与包含镀铜层的支承体进行接地连接(ground connection)，能够使EMI屏蔽效应提高。
·由于能够设为半导体封装体的最终产品不包含支承用平板的结构，因此能够使半导体封装体变薄，可移动产品等的产品应用范围变宽。
附图说明
图1-1中的图1A～图1D是表示在支承用平板上形成具有凹腔部的包含镀铜层的支承体的工序的图。
图1-2中的图1E～图1H是表示在包含镀铜层的支承体的凹腔部装载半导体芯片并形成密封树脂层，在该密封树脂层的表面形成布线层的工序的图。
图1-3中的图1I～图1L是表示在布线层的表面形成具有开口部的阻焊层，在阻焊层的开口部形成外部电极，将支承用平板和半导体封装体分离，在分离了的半导体封装体的背面形成绝缘层的工序的图。
图2中的图2A是表示在支承用平板的两面形成了半导体封装部的状态的图，图2B是表示将支承用平板和半导体封装部分离了的状态的图，图2C是表示在半导体封装部的一个面形成了绝缘材料层的状态的图。
图3是图2A中所示的半导体封装部的局部放大图。
图4是表示以往的PLP的结构的图。
图5是表示以往的PLP的制造工序的概略的图。
附图标记说明(关于图1～3)
1：支承用平板
2：包含镀铜层的支承体
5：粘接层
6：铜箔
6a：极薄铜箔
6b：铜箔载体
7：镀铜层
8：凹腔部
8a：凹腔壁
8b：凹腔底面
9：半导体芯片
10：密封树脂层
11：铜箔
12：布线层
13：阻焊层(solder resist)
14：阻焊层、绝缘材料层
15：开口部
16：凹腔部
16a：凹腔
16b：凹腔
17：外部电极、焊料球
20、20’：封装部
21：支承用平板部
30、30’：半导体封装体(semiconductor package)
(关于图4、图5)
1：支承板
2：半导体芯片
3：粘接剂
4：绝缘材料层
5：布线层
6：导电部
7：焊料球
20：半导体装置
具体实施方式
以下，说明用于实施本发明的实施方式。再者，在以下的记载中基于附图来说明实施方式，但这些附图是用于图解的图，本发明并不被这些附图所示的内容限定。
本发明的半导体封装体，其特征在于，具有在支承体的凹腔部内收纳了半导体芯片的结构，所述支承体包含镀铜层，且具有容纳半导体芯片的所述凹腔部。
以下，基于附图来说明具有上述结构的半导体封装体的具体例。
(实施方式1)
基于图1－1、图1－2、图1－3来说明本实施方式。
图1A是表示支承用平板1的图。支承用平板1是具有均匀的厚度的平坦的板，可以使用使绝缘树脂固化而成的树脂固化体、SUS(不锈钢)和42号合金等的刚性高的金属。支承用平板1起到对面板给予刚性、防止制造工序中的翘曲的作用，因此支承用平板1的厚度只要是不发生翘曲的程度的厚度即可。
另外，在将支承用平板保留于最终产品中的情况下，支承用平板1起到作为加强板(stiffener)、散热板、以及电磁屏蔽板的功能，并且在制造工序中也担负作为产品运送载体的作用，因此从面板的操作容易性、翘曲抑制、单片化的容易性的目的出发，优选使用不锈钢。
图1B是表示在支承用平板1上介由粘接层5层叠了铜箔6的状态的图。
如图1B的X部分的放大图所示，铜箔6是通常的带有载体的铜箔，成为极薄铜箔6a与铜箔载体6b的双层结构。
载体表面可以根据用途在层叠时进行正背面的改变，在要将支承用平板1保留到最终产品中的情况下，可以在该工序中剥除铜箔载体。
以下，对将支承用平板1最终从产品剥除的情况进行说明。
图1C是表示通过电解镀铜在铜箔6上以面内均匀的厚度形成了镀铜层7的状态的图。镀铜层7成为载置半导体芯片9的面。
图1D是表示采用使用一般的电镀的布线形成工艺，在镀铜层7上形成凹腔壁8a，形成了包含镀铜层的支承体2的状态的图。包含镀铜层的支承体2的凹腔部8，利用由镀铜层构成的凹腔壁8a、和作为镀铜层7的表面的凹腔底面8b形成。
所谓使用一般的电镀的布线形成工艺，是下述的工艺：例如，在镀铜层7上层压感光性干膜抗蚀剂，实施曝光、显像来进行图案化，在通过图案化而形成的开口部，通过电镀形成了由镀铜层构成的凹腔壁8a后，除去抗蚀剂。
优选所述凹腔部8的高度低于半导体芯片9的高度。再者，在本发明中，将凹腔部8的深度称为凹腔的高度。
图1E是表示在凹腔部8内装载了半导体芯片9的状态的图。
半导体芯片9的装载通过以下过程来进行：在半导体芯片9的背面或凹腔部8的凹腔底面涂布粘接剂，利用芯片粘接(die attach)装置拾取半导体芯片9而固定于凹腔底面8b。此时，当凹腔部8的高度比半导体芯片9的高度高时，有可能半导体芯片装载用的夹具(夹头等)与凹腔壁8a接触。因而，优选凹腔部8的高度设为半导体芯片9的高度以下。
图1F是表示形成了密封半导体芯片9的由绝缘树脂构成的密封树脂层10的状态的图。
作为密封方法，可使用层压方式、传递模塑(transfer molding)方式、压缩模塑(compression molding)方式等。
图1G是表示在密封树脂层10上层叠了铜箔11的状态的图。
铜箔11是为了在密封树脂层10的表面形成布线层而设置的。但是，也可以替代铜箔11的使用，通过无电解镀敷(electroless plating)、溅射、PVD等在密封树脂层10的表面设置种子层(seed layer)后，通过电镀来形成镀铜膜。
图1H是表示在密封树脂层10的表面形成了布线层12的状态的图。
该布线层12例如可以根据需要对铜箔11实施了黑化处理、蚀刻处理等的预处理后，实施使用激光的开口形成处理、去沾污(desmear)处理等，然后采用使用一般的电镀的布线形成工艺来形成。
图1I是表示在布线层12上形成了阻焊层13的状态的图。
使用热固性环氧树脂等绝缘材料，仅使需要钎焊的布线部分通过开口部15露出，用绝缘材料被覆不需要钎焊的部分，从而形成阻焊层13。
图1J是表示在开口部15形成了作为外部电极的焊料球17的状态的图。
图1K是表示将封装部20和支承用平板部21分离了的状态的图。
在本实施方式中，作为最终产品的半导体封装体是不具有支承用平板的结构，因此将封装部20和支承用平板部21分离。具体而言，从阻焊层13的面侧向铜箔6的材料端切入，在极薄铜箔6a与铜箔载体6b之间进行分离。
切入是考虑切割设备、铜箔贴合精度，切入铜箔材料尺寸的内侧来进行的。
图1L是表示在将支承用平板部21分离了的封装部20的镀铜层7侧附着的极薄铜箔6a上形成了阻焊层或者绝缘材料层14的状态的图。
可以根据需要在开口部15的布线层12上实施镀金等的表面处理，进行单片化，来得到半导体封装体30。
再者，在图1B的工序中已经剥除了铜箔载体6b的情况下，即，制作最终产品具备支承用平板1的产品的情况下，在所述图1I所示的形成了阻焊层13的状态的结构中，如果需要则可以在开口部15的露出的布线层12之上实施镀金等的表面处理，并进行单片化，来得到带有支承用平板的半导体封装体。
(实施方式2)
基于图2来说明本实施方式。本实施方式是实施方式1的应用例。
在本实施方式中，在实施方式1的图1B所示的结构中，在支承用平板1的两面上介由树脂5而层叠铜箔6，从而得到支承用平板部21。
图2A是表示对支承用平板1的两面实施与在实施方式1中进行的工序同样的工序，从而在支承用平板部21的两面形成了封装部20、20’的状态的图。
在支承用平板部21的两面形成封装部20、20’的情况，需要下述工序：首先，在一个面(称为表侧的面)的凹腔部8装载半导体芯片9从而进行固定，然后，将支承用平板部21翻过来，在相反的面(称为背侧的面)的凹腔部8装载半导体芯片9。
在该情况下，如果如实施方式1那样形成具有比半导体芯片1的高度低的凹腔壁8a的凹腔部16，则在背侧的面装载半导体芯片9时，先前装载在表侧的面上的半导体芯片9的表面会与装置工作台接触从而成为成品率恶化的主要原因。
为此，在本实施方式中，形成高度为半导体芯片9的高度以上的凹腔部16。
图3是将图2A所示的封装部中的凹腔部16的部分放大地示出的图。
凹腔部16的凹腔壁具有台阶部17，凹腔部16成为宽度窄的凹腔16a与宽度大的凹腔16b的2阶结构。
另外，凹腔16a的高度设为半导体芯片装载时的夹具不会干扰到凹腔16b的凹腔壁的高度，凹腔16b的开口尺寸设为半导体芯片装载时的夹具不会干扰到凹腔16b的凹腔壁的尺寸。
再者，这样的2阶结构的凹腔部也可用于实施方式1的凹腔部。
图2B是表示将封装部20和封装部20’与支承用平板部21分离了的状态的图。
图2C是表示在将支承用平板部21分离了的封装部20和封装部20’的镀铜层7上附着的极薄铜箔6a上形成了阻焊层或者绝缘材料层14的状态的图。
再者，可以根据需要在开口部15的布线层12上实施镀金等的表面处理，进行单片化，来得到半导体封装体30、30’。
列举本发明的半导体封装体的优点如下。
·由于半导体封装体的最终产品能够设为不含支承用平板的结构，因此能够使半导体封装体变薄，可移动产品等的产品应用范围扩大。
·由于作为最终产品能够剥除支承用平板，因此即使半导体封装体变薄也能够抑制制造中的面板翘曲。
·由于能够在凹腔部埋入半导体芯片，因此用绝缘树脂填埋的体积变小，即使半导体芯片的厚度、相邻的半导体芯片间的距离狭窄，树脂填埋也变得容易。另外，半导体芯片上的树脂厚度的偏差降低，通过特性、特性阻抗等的电特性优异。
·由于通过镀铜而形成了凹腔部，因此与蚀刻法不同，深度方向的尺寸精度优异。
·由于最终产品成为以镀铜体为支承体的结构，因此通过通常的层间连接通路与镀铜支承板建立了接地连接(ground connection)，能够使EMI屏蔽效应提高。
·通过设为凹腔结构，即使半导体芯片厚度厚，也能够缩短包含镀铜层的支承体与布线层的距离，因此通路的激光开孔加工、和通过镀铜进行的连接变得容易。

Claims (30)

1.一种半导体封装体，其特征在于，包括：
第一支承体，包括第一基底和在所述第一支承体的顶侧处从所述第一基底延伸的第一壁；
第一半导体芯片，其耦合到在所述第一基底上方的所述第一支承体的所述顶侧，并且与所述第一壁相邻；
密封件，其接触所述第一半导体芯片的横向侧；
第一导电结构，其在所述密封件的顶侧上方并且与所述第一半导体芯片的顶侧处的芯片端子耦合；以及
绝缘材料，其在所述第一半导体芯片的所述顶侧上方和在所述密封件的所述顶侧上方，其中所述绝缘材料接触所述密封件的顶侧。
2.根据权利要求1所述的半导体封装体，其特征在于，所述第一支承体包含铜。
3.根据权利要求1所述的半导体封装体，其特征在于，所述第一壁包括铜。
4.根据权利要求1所述的半导体封装体，其特征在于，还包括：
第二壁，其从所述第一基底延伸并且邻近与所述第一壁相对的所述第一半导体芯片。
5.根据权利要求4所述的半导体封装体，其特征在于：
所述第一壁、所述第二壁和所述第一支承体的所述第一基底限定空腔，并且
所述第一半导体芯片在所述空腔中。
6.根据权利要求1所述的半导体封装体，其特征在于，所述第一导电结构包括接触所述绝缘材料的布线层。
7.根据权利要求1所述的半导体封装体，其特征在于，所述密封件在所述第一壁和所述第一半导体芯片之间。
8.根据权利要求1所述的半导体封装体，其特征在于，还包括：
第二支承体，其与所述第一支承体相邻并且包括第二基底，以及
第二半导体芯片，其位于所述第二支承体的底侧下方。
9.根据权利要求8所述的半导体封装体，其特征在于，所述第二支承体的所述底侧与所述第一支承体的所述顶侧相对。
10.根据权利要求8所述的半导体封装体，其特征在于，还包括：
第二壁，其从所述第二支承体的所述底侧延伸，其中所述第二半导体芯片邻近所述第二壁。
11.根据权利要求8所述的半导体封装体，其特征在于，还包括：
第二导电结构，其耦合到在所述第二半导体芯片的第一侧处的芯片端子。
12.根据权利要求1所述的半导体封装体，其特征在于：
所述第一基底和所述第一壁是整体的。
13.一种半导体封装体的制造方法，其特征在于，所述制造方法包括：
提供第一支承体，其包括第一基底和在所述第一支承体的顶侧处从所述第一基底延伸的第一壁；
提供第一半导体芯片，其耦合到所述第一基底上方的所述第一支承体的所述顶侧，并且邻近所述第一壁；
提供与所述第一半导体芯片的横向侧接触的密封件；
在所述密封件的顶侧上方提供第一导电结构并且耦合到所述第一半导体芯片的所述顶侧处的芯片端子；以及
在所述第一半导体芯片的所述顶侧上方和所述密封件的所述顶侧上方提供绝缘材料；
其中所述绝缘材料接触所述密封件的顶侧。
14.根据权利要求13所述的制造方法，其特征在于，所述第一支承体包含铜。
15.根据权利要求13所述的制造方法，其特征在于，所述第一壁包括铜。
16.根据权利要求13所述的制造方法，其特征在于，还包括：
提供第二壁，所述第二壁从所述第一基底延伸并且邻近与所述第一壁相对的所述第一半导体芯片。
17.根据权利要求16所述的制造方法，其特征在于：
所述第一壁、所述第二壁和所述第一支承体的所述第一基底限定空腔，并且
所述第一半导体芯片在所述空腔中。
18.根据权利要求13所述的制造方法，其特征在于，所述第一导电结构包括接触所述绝缘材料的布线层。
19.根据权利要求13所述的制造方法，其特征在于，所述密封件在所述第一壁和所述第一半导体芯片之间。
20.根据权利要求13所述的制造方法，其特征在于，还包括：
提供与所述第一支承体相邻并且包括第二基底的第二支承体，以及
提供位于所述第二支承体的底侧下方的第二半导体芯片。
21.根据权利要求20所述的制造方法，其特征在于，所述第二支承体的所述底侧与所述第一支承体的所述顶侧相对。
22.根据权利要求20所述的制造方法，其特征在于，还包括：
提供从所述第二支承体的所述底侧延伸的第二壁，其中所述第二半导体芯片邻近所述第二壁。
23.根据权利要求20所述的制造方法，其特征在于，还包括：
提供第二导电结构，所述第二导电结构耦合到在所述第二半导体芯片的第一侧处的芯片端子。
24.根据权利要求13所述的制造方法，其特征在于：
所述第一基底和所述第一壁是整体的。
25.一种半导体封装体，其特征在于，包括：
第一支承体，包括第一基底和在所述第一支承体的顶侧处从所述第一基底延伸的第一壁；
第一半导体芯片，其耦合到在所述第一基底上方的所述第一支承体的所述顶侧，并且与所述第一壁相邻；
密封件，其接触所述第一半导体芯片的横向侧；以及
第一导电结构，其在所述密封件的顶侧上方并且与所述第一半导体芯片的顶侧处的芯片端子耦合。
26.根据权利要求25所述的半导体封装体，其特征在于，所述密封件接触所述第一壁的顶侧。
27.根据权利要求25所述的半导体封装体，其特征在于，所述第一导电结构接触所述密封件的顶侧。
28.根据权利要求25所述的半导体封装体，其特征在于，还包括：
第二支承体，其与所述第一支承体相邻并且包括第二基底，以及
第二半导体芯片，其位于所述第二支承体的底侧下方。
29.根据权利要求28所述的半导体封装体，其特征在于，还包括：
第二壁，其从所述第二支承体的所述底侧延伸，其中所述第二半导体芯片邻近所述第二壁。
30.根据权利要求28所述的半导体封装体，其特征在于，还包括：
第二导电结构，其耦合到在所述第二半导体芯片的第一侧处的芯片端子。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10083888B2 (en) * 2015-11-19 2018-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package
CN108493150A (zh) * 2018-02-02 2018-09-04 中国电子科技集团公司第五十五研究所 一种半导体金属化层阻焊的方法
CN112967932A (zh) * 2021-02-03 2021-06-15 复旦大学 一种板级GaN半桥功率器件及其制备方法
JP7317176B1 (ja) 2022-04-26 2023-07-28 株式会社アドバンテスト 試験方法および製造方法
JP7281579B1 (ja) 2022-04-26 2023-05-25 株式会社アドバンテスト 試験方法、製造方法、パネルレベルパッケージおよび試験装置

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990071466A (ko) * 1995-11-20 1999-09-27 휴버트 마이어 금속 전자 패키지용 접지 링
US6919508B2 (en) 2002-11-08 2005-07-19 Flipchip International, Llc Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
CN100508701C (zh) * 2004-10-22 2009-07-01 株式会社村田制作所 复合多层基板及其制造方法
JP2006128229A (ja) * 2004-10-26 2006-05-18 Murata Mfg Co Ltd 複合多層基板
US7816769B2 (en) * 2006-08-28 2010-10-19 Atmel Corporation Stackable packages for three-dimensional packaging of semiconductor dice
JP5267987B2 (ja) * 2006-11-06 2013-08-21 日本電気株式会社 半導体装置およびその製造方法
JP4343962B2 (ja) 2007-01-19 2009-10-14 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法及び半導体装置
US7759777B2 (en) 2007-04-16 2010-07-20 Infineon Technologies Ag Semiconductor module
JP4950743B2 (ja) * 2007-04-17 2012-06-13 株式会社フジクラ 積層配線基板及びその製造方法
TW200901409A (en) * 2007-06-22 2009-01-01 Nan Ya Printed Circuit Board Corp Packaging substrate with embedded chip and buried heatsink
WO2009014126A1 (ja) * 2007-07-23 2009-01-29 Murata Manufacturing Co., Ltd. 多層配線基板
US7718901B2 (en) * 2007-10-24 2010-05-18 Ibiden Co., Ltd. Electronic parts substrate and method for manufacturing the same
JP5224845B2 (ja) * 2008-02-18 2013-07-03 新光電気工業株式会社 半導体装置の製造方法及び半導体装置
JP5233338B2 (ja) * 2008-03-17 2013-07-10 富士電機株式会社 半導体装置及び半導体装置の製造方法
US7863096B2 (en) 2008-07-17 2011-01-04 Fairchild Semiconductor Corporation Embedded die package and process flow using a pre-molded carrier
US7982292B2 (en) 2008-08-25 2011-07-19 Infineon Technologies Ag Semiconductor device
US8354304B2 (en) 2008-12-05 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant
JP2010219489A (ja) * 2009-02-20 2010-09-30 Toshiba Corp 半導体装置およびその製造方法
US7989270B2 (en) 2009-03-13 2011-08-02 Stats Chippac, Ltd. Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors
JP5522172B2 (ja) 2009-07-30 2014-06-18 日亜化学工業株式会社 発光装置及びその製造方法
KR101104210B1 (ko) * 2010-03-05 2012-01-10 삼성전기주식회사 전자소자 내장형 인쇄회로기판 및 그 제조방법
US8847376B2 (en) * 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
JP2012146963A (ja) * 2010-12-20 2012-08-02 Shinko Electric Ind Co Ltd 半導体パッケージの製造方法及び半導体パッケージ
US8598694B2 (en) 2011-11-22 2013-12-03 Infineon Technologies Ag Chip-package having a cavity and a manufacturing method thereof
KR101874992B1 (ko) * 2011-12-30 2018-07-06 삼성전기주식회사 부품 내장형 인쇄회로기판 및 이의 제조방법
US9799627B2 (en) 2012-01-19 2017-10-24 Semiconductor Components Industries, Llc Semiconductor package structure and method
US8597979B1 (en) * 2013-01-23 2013-12-03 Lajos Burgyan Panel-level package fabrication of 3D active semiconductor and passive circuit components
CN104851812B (zh) 2014-02-19 2017-10-20 钰桥半导体股份有限公司 半导体元件及其制作方法
KR102186148B1 (ko) * 2014-02-28 2020-12-03 삼성전기주식회사 임베디드 기판 및 임베디드 기판의 제조 방법
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9941219B2 (en) * 2014-09-19 2018-04-10 Intel Corporation Control of warpage using ABF GC cavity for embedded die package
DE102014114982B4 (de) 2014-10-15 2023-01-26 Infineon Technologies Ag Verfahren zum Bilden einer Chip-Baugruppe
US20160240452A1 (en) 2015-02-18 2016-08-18 Semiconductor Components Industries, Llc Semiconductor packages with sub-terminals and related methods

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JP2018006408A (ja) 2018-01-11
US20170373012A1 (en) 2017-12-28
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JP6716363B2 (ja) 2020-07-01
KR20180002025A (ko) 2018-01-05
CN107546184A (zh) 2018-01-05
TWI781735B (zh) 2022-10-21
US10079161B2 (en) 2018-09-18
TW202303874A (zh) 2023-01-16
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