TWI740938B - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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TWI740938B
TWI740938B TW106115284A TW106115284A TWI740938B TW I740938 B TWI740938 B TW I740938B TW 106115284 A TW106115284 A TW 106115284A TW 106115284 A TW106115284 A TW 106115284A TW I740938 B TWI740938 B TW I740938B
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layer
forming
sealing resin
semiconductor
resin layer
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TW106115284A
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TW201801204A (zh
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稲岡俊幸
吉川雄一郎
浦辻淳広
吉光克司
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日商安靠科技日本公司
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Abstract

本發明之目的在於提供一種半導體封裝，係縮小密封樹脂的體積，而在半導體晶片的厚度厚且相鄰的半導體晶片間的距離較窄時亦可容易地進行樹脂埋入，以及提供一種薄型半導體封裝，係最終製品不包含支撐用平板。

本發明之解決手段為一種半導體封裝，其特徵在於具有在由鍍銅所構成之支撐體的凹槽部內收容半導體晶片之構造，該支撐體係具有收容半導體晶片之凹槽部。

Description

半導體封裝及其製造方法
本發明係關於半導體封裝及其製造方法，更詳細而言係關於一種半導體封裝及其製造方法，該半導體封裝係以大型的面板尺寸進行薄膜配線製程及組裝製程之具有Panel Level Package(面板級封裝，以下稱為PLP)構造者。
隨著近年來電子機器的高功能化及輕薄短小化之要求，電子零件的高密度積體化及高密度安裝化更加進展，使用於該等電子機器之半導體裝置相較於以往小型化亦更加進展。
以電子零件的高密度化、輕薄短小化之半導體封裝的製造方法之例子係記載於專利文獻1。
於第4圖顯示專利文獻1所記載之半導體裝置的基本構造，並針對該半導體裝置說明如下。
半導體裝置1020係具備由樹脂硬化體或金屬所構成之支撐板101，並於其一方之主面以元件電路面(表側面)為上配置有半導體晶片102，與元件電路面為相反 側之面(背面側)係藉由黏接劑103固定黏接於支撐板101。並且，於支撐板101的主面整面係以覆蓋半導體晶片102的元件電路面之方式形成僅一層之絕緣材料層104。該單層之絕緣材料層104之上方係形成有由銅等導電性金屬所構成之配線層105，且其一部分被拉出至半導體晶片102之的周邊區域。再者，於形成於半導體晶片102的元件電路面上之絕緣材料層104係形成有將半導體晶片102的電極墊與配線層105電性連接之導電部(貫孔部)106。該導電部106係與配線層105一併形成而一體化。再者，於配線層105的預定位置形成有複數個屬於外部電極之焊球107。並且，在絕緣材料層104及焊球107的接合部以外之配線層105之上方，形成有配線保護層(阻焊層)108。
依據第5圖說明以往的PLP的製造方法。
第5圖所示者為一種製造封裝的方法之概要，該封裝係於一個封裝搭載有三個半導體晶片102。另外，雖在實際上係在大尺寸的面板上同時複數組裝複數個封裝，惟於第5圖中係僅顯示一個封裝。
封裝的製造方法係由下述之(A)、(B)及(C)之步驟構成。
(A)半導體元件搭載步驟(參閱第5A圖)
於由樹脂硬化體或不鏽鋼鋼材或42合金(42 Alloy)等金屬所構成之支撐板101的一方之主面藉由黏接劑將半導體晶片102以元件電路面朝上之方式予以固定黏接。
(B)密封步驟(參閱第5B圖)
以絕緣樹脂104密封支撐板101的半導體晶片102的 搭載面。
(C)配線形成步驟(參閱第5C圖)
形成配線層105，該配線層105係藉由導電部106而與半導體晶片102的電極貫孔連接。
[先前技術文獻] [專利文獻]
專利文獻1：日本特開2010-219489號公報。
在如第4圖所示之以往的PLP中，由於係在付有支撐板101之狀態下成為最終製品，故若半導體晶片102的搭載率變高，則在製造中會產生面板曲翹，而有會干涉PLP的製造裝置之問題。
再者，在半導體晶片102的厚度變厚，且相鄰的半導體晶片102間的距離變短時，會有絕緣樹脂不會進入該間隙之問題。並且為了改善該問題而將樹脂材料厚度加厚時，則會有半導體封裝本身的薄型化無法達成之問題。
並且，在半導體晶片的厚度變厚時，由於支撐板101與配線層105之距離會變長，故會有難以進行用以連接支撐板101與配線層105之雷射之貫孔開孔加工、鍍銅連接之問題。
本發明之目的在於提供一種半導體封裝，係縮小密封樹脂的體積，而在半導體晶片的厚度厚且相鄰 的半導體晶片間的距離較窄時亦可容易地進行樹脂埋入，以及提供一種薄型半導體封裝，係最終製品不包含支撐用平板。
本發明之諸發明人係發現藉由做成將半導體晶片埋入藉由鍍銅而形成之凹槽部之構造能夠解決上述課題，從而完成本發明。
亦即本發明係關於如下述記載之半導體封裝及其製造方法者。
(1)一種半導體封裝，其具有在由鍍銅所構成之支撐體的凹槽部內收容半導體晶片之構造，該支撐體係具有收容半導體晶片之前述凹槽部。
(2)如上述(1)所記載之半導體封裝，前述凹槽部的高度係設為比半導體晶片的高度更低，以避免半導體晶片搭載輔助具與形成前述凹槽部之凹槽壁干涉。
(3)如上述(1)所記載之半導體封裝，半導體封裝的外周部的凹槽壁係具有上部寬廣之段差部，且該段差部的高度係設為比半導體晶片的高度更低，以避免半導體晶片搭載輔助具與前述凹槽壁干涉。
(4)一種半導體封裝，係包括：支撐體；半導體晶片，係隔著黏接層以元件電路面朝上之方式被搭載於前述支撐體的一方之表面；絕緣材料層，係將前述半導體晶片及其周邊予以密封；開口，係於前述絕緣材料層中，形成於被 配置在前述半導體晶片的前述元件電路面之電極上；導電部，係以與前述半導體晶片的前述電極連接之方式形成於前述開口內；配線層，係以在前述絕緣材料層上與前述導電部連接之方式形成，且一部分係延伸至前述半導體晶片的周邊區域；以及外部電極，係形成於前述配線層上；前述支撐體係由在前述一方之表面具有收容半導體晶片之凹槽部之鍍銅體所構成，且半導體晶片係收容於前述凹槽部內；於前述支撐體的另一方之表面具有絕緣材料層。
(5)一種半導體封裝的製造方法，係依序包括以下步驟：在支撐用平板的一方之主面積層銅箔之步驟；在前述銅箔上藉由電鍍而形成鍍銅層之步驟；在前述鍍銅層上藉由電鍍形成凹槽部之步驟；藉由黏接劑將與半導體晶片的元件電路面為相反側之表面黏接固定於前述凹槽部之步驟；將前述半導體晶片藉由絕緣樹脂進行樹脂密封而形成密封樹脂層之步驟；在配置於前述半導體晶片的前述元件電路面之電極上之位置，於前述絕緣材料層形成開口之步驟；於前述絕緣材料層上形成配線層，且在前述絕緣材料層的前述開口內形成導電部之步驟，該配線層係一部分延伸至前述半導體晶片的周邊區域，該導電部係與前述半導體晶片的前述電極連接；於前述配線層上留下開口部而形成阻焊層之步驟；於前述開口部的配線層上形成外部電極之步驟；將前述支撐用平板從前述銅箔分離之步驟；以及於已分離之銅箔上形成絕緣材料層之步驟。
(6)一種具有支撐用平板之半導體封裝的製造方法， 係依序包括以下步驟：於前述支撐用平板的一方之主面積層銅箔之步驟；在前述銅箔上藉由電鍍而形成鍍銅層之步驟；在前述鍍銅層上藉由電鍍形成凹槽部之步驟；藉由黏接劑將與半導體晶片的元件電路面為相反側之表面黏接固定於前述凹槽部之步驟；將前述半導體晶片藉由絕緣樹脂進行樹脂密封而形成密封樹脂層之步驟；在配置於前述半導體晶片的前述元件電路面之電極上之位置，於前述絕緣材料層形成開口之步驟；於前述絕緣材料層上形成配線層，且在前述絕緣材料層的前述開口內形成導電部之步驟，該配線層係一部分延伸至前述半導體晶片的周邊區域，該導電部係與前述半導體晶片的前述電極連接；於前述配線層上留下開口部而形成阻焊層之步驟；以及於前述開口部的配線層上形成外部電極之步驟。
(7)如上述(5)或(6)所記載之半導體封裝的製造方法，前述凹槽部係藉由利用阻障層之圖案鍍而形成未析出銅之部分來形成。
(8)一種半導體封裝的製造方法，係特徵在於：對支撐用平板的兩面分別進行以下步驟而在支撐用平板的兩面分別形成封裝部：積層銅箔之步驟；在前述銅箔上藉由電鍍而形成鍍銅層之步驟；在前述鍍銅層上藉由電鍍形成凹槽部之步驟；藉由黏接劑將與半導體晶片的元件電路面為相反側之表面黏接固定於前述凹槽部之步驟；將前述半導體晶片藉由絕緣樹脂進行樹脂密封而形成密封樹脂層之步驟；在配置於前述半導體晶片的前述元件電路面之電極上 之位置，於前述絕緣材料層形成開口之步驟；於前述絕緣材料層上形成配線層，且在前述絕緣材料層的前述開口內形成導電部之步驟，該配線層係一部分延伸至前述半導體晶片的周邊區域，該導電部係與前述半導體晶片的前述電極連接；於前述配線層上留下開口部而形成阻焊層之步驟；以及於前述開口部的配線層上形成外部電極之步驟；並且依序包含以下步驟：將前述支撐用平板從前述各個封裝部分離，而獲得二個封裝部之步驟；以及於前述二個封裝部的銅箔上形成絕緣材料層之步驟。
本發明之半導體封裝係可達成以下功效。
‧由於在具有凹槽部之由鍍銅構成之支撐體的凹槽部收容半導體晶片，因此以密封樹脂密封之體積變小，即便半導體晶片的厚度厚且相鄰之半導體晶片間的距離狹窄亦可容易地埋入樹脂。
‧由於最終製品會成為被由鍍銅構成之支撐體所支撐之構造，故可藉由一般的層間連接貫孔與由鍍銅構成之支撐體接地連接，並使EMI屏障效應提升。
‧由於可做成半導體封裝的最終製品不包含支撐用平台之構造，故可將半導體封裝做薄，而擴大行動製品等製品應用範圍。
1‧‧‧支撐用平板、支撐板
2‧‧‧支撐體、半導體晶片
3‧‧‧黏接劑
4‧‧‧絕緣材料層
5‧‧‧黏接層、配線層
6‧‧‧銅箔、導電部
6a‧‧‧極薄銅箔
6b‧‧‧銅箔載體
7‧‧‧鍍銅層、焊球
8、16‧‧‧凹槽部、配線保護層
8a‧‧‧凹槽壁
8b‧‧‧凹槽底面
9‧‧‧半導體晶片
10‧‧‧密封樹脂層
11‧‧‧銅箔
12‧‧‧配線層
13‧‧‧阻焊層
14‧‧‧阻焊層或絕緣材料層
15‧‧‧開口
16a、16b‧‧‧凹槽
17‧‧‧外部電極、焊球
20、20’‧‧‧封裝部、半導體裝置
21‧‧‧支撐用平板部
30、30’‧‧‧半導體封裝
37‧‧‧段差部
101‧‧‧支撐板
102‧‧‧半導體晶片
103‧‧‧黏接劑
104‧‧‧絕緣材料層
105‧‧‧配線層
106‧‧‧導電部(貫孔部)
107‧‧‧焊球
108‧‧‧配線保護層(阻焊層)
1020‧‧‧半導體裝置
第1A圖至第1D圖係顯示於支撐用平板上形成具有凹 槽部之由鍍銅所構成之支撐體之步驟之圖。
第1E圖至第1H圖係顯示於由鍍銅所構成之支撐體的凹槽部搭載半導體晶片並形成密封樹脂層，且於該密封樹脂層的表面形成配線層之步驟之圖。
第1I圖至第1L圖係於配線層的表面形成具有開口部之阻焊層，並於阻焊層的開口部形成外部電極，將支撐用平板與半導體封裝分離，且在分離出的半導體封裝的背面形成絕緣層之步驟之圖。
第2A圖係顯示於支撐用平板的兩面形成半導體封裝部之狀態之圖，第2B圖係顯示將支撐用平板與導體封裝部分離之狀態之圖。第2C圖係顯示於半導體封裝部的一方之表面形成絕緣材料層之狀態之圖。
第3圖係將第2A圖所示之半導體封裝部的部分擴大之圖。
第4圖係顯示以往的PLP的構造之圖。
第5A圖至第5C圖係顯示以往的PLP的製造步驟之概略之圖。
以下，針對用以實施本發明之形態進行說明。另外，在以下之記載中雖依據圖式說明實施形態，惟該等圖式係用於圖解者，本發明並不限於該等圖式所示者。
本發明之半導體封裝之特徵在於具有：在具有收容半導體晶片之凹槽部之由鍍銅所構成之支撐體的前述凹槽內收容半導體晶片之構造。
在以下說明中，依據圖式說明具有上述構造之半導體裝置的具體例。
(實施形態1)
依據圖式第1A-1L圖進行說明。
第1A圖係顯示支撐用平板1之圖。支撐用平板1係具有均勻厚度之平坦的板，可使用使絕緣樹脂硬化之樹脂硬化體、SUS或42合金等高剛性之金屬。由於支撐用平板1係發揮對平板賦予剛性並防止製造步驟中之曲翹的功能，因此支撐用平板1的厚度只要為不會產生曲翹之程度的厚度即可。
再者，在將支撐用平板留到最終製品時，支撐用平板1係作為防撓材、散熱板及電磁屏障而發揮功能，並且於製造步驟中亦發揮作為製品搬送載體而發揮功能，故就平板的操作容易性、曲翹抑制、單片化之容易性的目的而言，較佳係利用不鏽鋼鋼材。
第1B圖係顯示在支撐用平板1上隔著黏接層5積層銅箔6之狀態之圖。
如第1B圖的X部分之放大圖所示，銅箔6係一般的附載體銅箔，形成為極薄銅箔6a與銅箔載體6b之二層構造。
載體面可因應用途而在積層時改變其表裡，在將支撐用平板1保留到最終製品之情形時可在本步驟剝去銅箔載體。
以下係針對在最終從製品剝去支撐用平板1之情形進 行說明。
第1C圖係顯示在銅箔6上藉由電解鍍銅而以面內均勻之厚度形成鍍銅層7之狀態之圖。鍍銅層7係載置半導體晶片9之面。
第1D圖係顯示於鍍銅層7上利用一般的電鍍之配線形成製程來形成凹槽壁8a從而形成由鍍銅所構成之支撐體2之狀態之圖。由鍍銅構成之支撐體2的凹槽部8係以由鍍銅所構成之凹槽壁8a，以及屬於鍍銅層7的表面之凹槽底面8b所形成。
由一般的電鍍進行之配線形成製程係例如以下製程：於鍍銅層7疊合感光性乾式阻障層膜，實施曝光、顯影而進行圖形化，並在於藉由圖形化而形成之開口部藉由電鍍而形成由鍍銅所構成之凹槽壁8a後，去除阻障層。
前述凹槽部8的高度較佳係比半導體晶片9的高度更低。另外在本發明中係將凹槽部8的深度稱為凹槽的高度。
第1E圖係顯示於凹槽部8內搭載半導體晶片9之狀態之圖。
半導體晶片9的搭載係藉由在半導體晶片9的背面或凹槽部8的凹槽底面塗敷黏接劑，並藉由晶圓構裝(die attach)裝置揀取(pick-up)半導體晶片9並予以黏接固定於凹槽底面8b而進行。此時，凹槽部8的高度若比半導體晶片9的高度更高就會有半導體晶片搭載用之輔助具(夾頭等)接觸凹槽壁8a之虞。因此，凹槽部8的高度較佳係為半導體晶片9的高度以下。
第1F圖係顯示形成將半導體晶片9密封之由絕緣樹脂構成之密封樹脂層10之狀態之圖。
就密封方式而言係採用可疊合方式、轉移模製方式、壓縮模方式等。
第1G圖係顯示於密封樹脂層10積層銅箔11之狀態之圖。
銅箔11係為了在密封樹脂層10的表面形成配線層而設置者。然而，亦可替代使用銅箔11，在密封樹脂層10的表面藉由無電解鍍覆、濺鍍、PVD等設有晶種層後，藉由電鍍而形成鍍銅膜。
第1H圖係顯示在密封樹脂層10的表面形成配線層12之狀態之圖。
該配線層12係例如可在對銅箔11因應需要而實施黑化處理或蝕刻處理等前處理後，實施以雷射進行之開口形成處理、表面去汙處理等，然後使用以一般的電鍍進行之配線形成製程而形成。
第1I圖係顯示在配線層12上形成阻焊層13之狀態之圖。
使用熱硬化性環氧樹脂等絕緣材料，藉由開口15僅使需要焊料之配線部分露出，並藉由絕緣材料被覆不需要焊料之部分而形成阻焊層13。
第1J圖係顯示於開口15形成屬於外部電極之焊球17之狀態之圖。
第1K圖係顯示將封裝部20與支撐用平板 部21予以分離之狀態之圖。在本實施形態中，屬於最終製品之半導體封裝由於為不具有支撐用平板之構造，故將封裝部20與支撐用平板部21分離。具體而言，從阻焊層13的表面側對銅箔6的材料端開出切縫，而在極薄銅箔6a與銅箔載體6b之間分離。
切縫係考慮切斷設備、銅箔貼合精確度而藉由切開比銅箔材料更內側而進行。
第1L圖係顯示在將支撐用平板部21分離後之封裝部20的鍍銅層7側附著之極薄銅箔6a上形成阻焊層或絕緣材料層14之狀態之圖。
因應需要對開口部15的配線層12上實施鍍金等表面處理，並藉由予以單片化而可獲得半導體封裝30。
另外，在第1B圖之步驟中已將銅箔載體6b剝離時，亦即在製作最終製品為具備有支撐用平板1者時，係於前述第1I圖所示之形成有阻焊層13之狀態中，若有需要則於開口部15之露出之配線層12上實施鍍金等表面處理，並藉由單片化而可獲得付有支撐用平板之半導體封裝。
(實施形態2)
依據第2圖說明本實施形態。本實施形態係實施形態1之應用例。
於本實施形態中，係於實施形態1之第1B圖所示者中，於支撐用平板1的兩面隔著樹脂5積層銅箔6而獲得支撐用平板21。
第2A圖係顯示對於支撐用平板1的兩面實施與於實施形態1中進行過之相同之步驟，而在支撐用平板21的兩面形成封裝部20、20’之狀態之圖。
在於支撐用平板21的兩面形成封裝部20、20’之情形時，需要以下步驟：首先在一方之表面(又稱表側面)之凹槽部8搭載並固定黏接半導體晶片9之後，將支撐用平板部21翻面並在相反側之表面(背側面)之凹槽部8搭載半導體晶片9。
此時，如實施形態1所示者，若形成具有比半導體晶片1的高度更低之凹槽壁8a之凹槽部16，則在背側面搭載半導體晶片9時，先搭載於表面側之半導體晶片9的表面會與裝置台接觸而成為良率不佳之原因。
因此，在本實施形態中，係形成具有比半導體晶片9的高度更高之凹槽部16。
第3圖係顯示將第2A圖所示之封裝部之凹槽部16的部分放大之圖。
凹槽部16的高溝壁係具有段差部37，凹槽部16係成為寬度較窄之凹槽16a與寬度較寬之凹槽16b之二段構造。
另外，凹槽16a的高度係設為半導體晶片搭載時之輔助具不會干涉凹槽16b的凹槽壁之高度，凹槽16b的開口尺寸係設為半導體晶片搭載時之輔助具不會干涉凹槽16b的凹槽壁之尺寸。
另外，該種二段構造之凹槽部亦可於實施形態1之凹槽部中採用。
第2B圖係顯示將封裝部20及封裝部20’與支撐用平板部21予以分離之狀態之圖。
第2C圖係在將支撐用平板部21分離後之封裝部20及封裝部20’的鍍銅層7附著之極薄銅箔6a上形成阻焊層或絕緣材料層14之狀態之圖。
接著，因應需要對開口部15的配線層12上實施鍍金等表面處理，並藉由單片化而可獲得半導體封裝30、30’。
本發明之半導體封裝之優點可舉例如下。
‧由於可做成半導體封裝的最終製品為不包含支撐用平板之構造，故可使半導體封裝變薄，而可擴大行動製品的製品應用範圍。
‧由於作為最終製品可剝去支撐用平板，故即便半導體封裝變薄亦可抑制製造中的平板曲翹。
‧由於可在凹槽部內埋入半導體晶片，故以絕緣樹脂埋入之體積變小，即便半導體晶片厚度厚且相鄰之半導體晶片間的距離變窄也可使樹脂埋入變得容易。再者，由於減低半導體晶片上的樹脂厚度之不均，通過特性或特性阻抗等電性特性優異。
‧由於藉由鍍銅等形成凹槽部，故與蝕刻工法不同，深度方向之尺寸精確度優異。
‧由於最終製品為將鍍銅體做成支撐體之構造，故可藉由一般的層間連接貫孔與鍍銅支撐板接地連接，而可使EMI屏障效應提升。
‧由於藉由做成為凹槽構造而即便是在半導體晶片厚 度較厚，亦可縮短由鍍銅構成之支撐體與配線層之距離，故可容易進行雷射貫孔開孔加工、鍍銅之連接。
由於本案的圖為製造步驟圖，並非本案的代表圖。故本案無指定代表圖。

Claims (14)

  1. 一種半導體封裝，係包括：支撐體，包括凹槽和凹槽壁，其中所述凹槽沒有完全穿透所述支撐體；半導體晶片，係以元件電路面的電極朝上之方式被搭載於前述支撐體的所述凹槽中；密封樹脂層，係將前述半導體晶片及其周邊予以密封；配線層，係在前述密封樹脂層上與前述電極連接，且一部分係延伸至前述半導體晶片的周邊區域，以及其中前述半導體晶片係收容於前述凹槽內，其中所述半導體晶片在兩個側面和底側上以所述支撐體為界；以及絕緣材料層，其與所述密封樹脂層和所述配線層接觸，並且至少部分與所述半導體晶片的所述元件電路面重疊。
  2. 如申請專利範圍第1項所述之半導體封裝，其中所述密封樹脂層接觸所述半導體晶片的側面。
  3. 如申請專利範圍第1項所述之半導體封裝，其中所述密封樹脂層接觸所述半導體晶片的所述元件電路面。
  4. 如申請專利範圍第1項所述之半導體封裝，其中所述元件電路面的 高度至少等於或大於所述凹槽的外部之所述支撐體的表面的高度。
  5. 如申請專利範圍第1項所述之半導體封裝，其中所述元件電路面的高度至少等於或大於所述凹槽壁的高度。
  6. 如申請專利範圍第1項所述之半導體封裝，其中所述絕緣材料層在所述封裝樹脂層和所述半導體晶片上方。
  7. 如申請專利範圍第1項所述之半導體封裝，其中所述支撐體包括金屬。
  8. 如申請專利範圍第1項所述之半導體封裝，其包括與所述半導體晶片的所述電極和所述配線層耦接的導電部分。
  9. 如申請專利範圍第1項所述之半導體封裝，其包括與所述配線層耦接的外部電極。
  10. 如申請專利範圍第1項所述之半導體封裝，其中所述半導體晶片透過黏接劑被附著在所述支撐體的所述凹槽中。
  11. 一種半導體封裝的製造方法，係依序包括以下步驟：在支撐用平板的一方之主面積層銅箔之步驟；在前述銅箔上藉由電鍍而形成鍍銅層之步驟；在前述鍍銅層上藉由電鍍形成凹槽部之步驟；藉由黏接劑將與半導體晶片的元件電路面為相反側之表面黏接 固定於前述凹槽部之步驟；將前述半導體晶片藉由絕緣樹脂進行樹脂密封而形成密封樹脂層之步驟；在配置於前述半導體晶片的前述元件電路面之電極上之位置，於前述密封樹脂層中形成開口之步驟；於前述密封樹脂層上形成配線層，且在前述密封樹脂層的前述開口內形成導電部之步驟，該配線層係一部分延伸至前述半導體晶片的周邊區域，該導電部係與前述半導體晶片的前述電極連接；於前述配線層上留下開口部而形成阻焊層之步驟；於前述開口部的配線層上形成外部電極之步驟；將前述支撐用平板從前述銅箔分離之步驟；以及形成絕緣材料層之步驟，所述絕緣材料層與所述密封樹脂層和所述配線層接觸，並且至少部分與所述半導體晶片的所述元件電路面重疊。
  12. 一種具有支撐用平板之半導體封裝的製造方法，係依序包括以下步驟：於支撐用平板的一方之主面積層銅箔之步驟；在前述銅箔上藉由電鍍而形成鍍銅層之步驟； 在前述鍍銅層上藉由電鍍形成凹槽部之步驟；藉由黏接劑將與半導體晶片的元件電路面為相反側之表面黏接固定於前述凹槽部之步驟；將前述半導體晶片藉由絕緣樹脂進行樹脂密封而形成密封樹脂層之步驟；在配置於前述半導體晶片的前述元件電路面之電極上之位置，於前述密封樹脂層中形成開口之步驟；於前述密封樹脂層上形成配線層，且在前述密封樹脂層的前述開口內形成導電部之步驟，該配線層係一部分延伸至前述半導體晶片的周邊區域，該導電部係與前述半導體晶片的前述電極連接；於前述配線層上留下開口部而形成阻焊層之步驟，所述阻焊劑接觸所述密封樹脂層和所述配線層並且至少部分地與所述半導體晶片的所述元件電路面重疊；以及於前述開口部的配線層上形成外部電極之步驟。
  13. 如申請專利範圍第11或12項所述之半導體封裝的製造方法，其中，前述凹槽部係藉由利用阻障層之圖案鍍而形成未析出鍍銅之部分來形成。
  14. 一種半導體封裝的製造方法，係包括以下步驟： 對支撐用平板的兩面分別進行以下步驟而在所述支撐用平板的兩面分別形成封裝部：積層銅箔之步驟；在前述銅箔上藉由電鍍而形成鍍銅層之步驟；在前述鍍銅層上藉由電鍍形成凹槽部之步驟；藉由黏接劑將與半導體晶片的元件電路面為相反側之表面黏接固定於前述凹槽部之步驟；將前述半導體晶片藉由絕緣樹脂進行樹脂密封而形成密封樹脂層之步驟；在配置於前述半導體晶片的前述元件電路面之電極上之位置，於前述密封樹脂層中形成開口之步驟；於前述密封樹脂層上形成配線層，且在前述密封樹脂層的前述開口內形成導電部之步驟，該配線層係一部分延伸至前述半導體晶片的周邊區域，該導電部係與前述半導體晶片的前述電極連接；於前述配線層上留下開口部而形成阻焊層之步驟；以及於前述開口部的配線層上形成外部電極之步驟；並且依序包含以下步驟：將前述支撐用平板從前述各個封裝部分離，而獲得二個封裝部之 步驟；以及形成密封樹脂層之步驟，其中，所述密封樹脂層接觸所述密封樹脂層和所述配線層並且至少部分地與所述半導體晶片的所述元件電路面重疊。
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