CN1162906C - 堆叠式影像感测器及其制造方法 - Google Patents

堆叠式影像感测器及其制造方法 Download PDF

Info

Publication number
CN1162906C
CN1162906C CNB011042265A CN01104226A CN1162906C CN 1162906 C CN1162906 C CN 1162906C CN B011042265 A CNB011042265 A CN B011042265A CN 01104226 A CN01104226 A CN 01104226A CN 1162906 C CN1162906 C CN 1162906C
Authority
CN
China
Prior art keywords
integrated circuit
substrate
sensing wafer
image sensor
image sensing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB011042265A
Other languages
English (en)
Other versions
CN1372322A (zh
Inventor
何孟南
杜修文
蔡孟儒
吴志成
陈文铨
陈立桓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kingpak Technology Inc
Original Assignee
Kingpak Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kingpak Technology Inc filed Critical Kingpak Technology Inc
Priority to CNB011042265A priority Critical patent/CN1162906C/zh
Publication of CN1372322A publication Critical patent/CN1372322A/zh
Application granted granted Critical
Publication of CN1162906C publication Critical patent/CN1162906C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

一种堆叠式影像感测器及其制造方法。为提供一种构件少、体积小、制造简单、封装及测试成本低的影像感测器及其制造方法,提出本发明,感测器包括基板、集成电路、封装层、影像感测晶片及透光层;以封装层封装集成电路设置于基板上,影像感测晶片叠置于集成电路的封装层上;制造方法包括将集成电路固定于基板上;将封装层覆盖于集成电路上;将影像感测晶片设置于封装层上以与集成电路形成堆叠;将透光层覆设于影像感测晶片上方。

Description

堆叠式影像感测器及其制造方法
技术领域
本发明属于影像感测器及其制造方法,特别是一种堆叠式影像感测器及其制造方法。
背景技术
一般感测器系用来感测接收光或声音的讯号,本发明系用来接收影像讯号,并将影像讯号转换为电讯号传递至印刷电路板上。
一般影像感测器用以接收影像讯号,并将影像讯号转换为电讯号传递至印刷电路板上,再与其他集成电路进行电连接,使其具有不同的功能需求。诸如,其与数位讯号处理器(Digital signal Processor)电连接,用以处理影像感测器所产生的讯号,或可与微控制器(Micro Controller)或中央处理器(CPU)等电连接,而产生不同的功能需求。
然而,习知影像感测器皆单独封装制成,因此,与其搭配的各种集成电路亦必须单独进行封装,再将封装完成的影像感测器及各种集成电路电连接于印刷电路板上,并藉由导线将其电连接整合使用。如此,各单独封装的集成电路与影像感测器必须分别使用基板及封装制成,造成生产成本无法有效地降低,且将各单独封装的集成电路设置于印刷电路板上时,所需印刷电路板的面积必须较大,而无法达到轻、薄、短小的需求。
发明内容
本发明的目的是提供一种的构件少、体积小、制造简单、封装及测试成本低的堆叠式影像感测器及其制造方法。
本发明堆叠式影像感测器包括形成讯号输入、输出端的基板、集成电路、封装层、以复数条导线与基板讯号输入端电连接的影像感测晶片及盖设于影像感测晶片上的透光层;以封装层封装并以复数条导线与基板讯号输入端电连接的集成电路设置于基板上,影像感测晶片叠置于集成电路的封装层上。
本发明堆叠式影像感测器制造方法包括将集成电路固定于基板上,并与基板讯号输入端形成电连接;将封装层覆盖于集成电路上;将影像感测晶片设置于封装层上以与集成电路形成堆叠;将使影像感测晶片得以透过透光层接收影像讯号的透光层覆设于影像感测晶片上方。
其中:
基板上表面周缘形成将集成电路、封装层及影像感测晶片围绕住的凸缘层;透光层设置于凸缘层上方。
透光层为覆盖集成电路、封装层及影像感测晶片的透明胶体。
为透明胶体的透光层呈冂形。
集成电路为数位讯号处理器(digital signal processor)、微处理器(microprocessor)或中央处理器(central processor unit)。
在将影像感测晶片上方覆设透光层前,先于基板周缘形成凸缘层。
在将封装层覆盖于集成电路上后,再将凸缘层设置于基板周缘。
覆盖于集成电路上的封装层与凸缘层同时形成于基板上。
覆设透光层为将呈冂形的透明胶体覆盖于基板的上表面上。
由于本发明堆叠式影像感测器包括形成讯号输入、输出端的基板、集成电路、封装层、影像感测晶片及透光层;以封装层封装集成电路设置于基板上,影像感测晶片叠置于集成电路的封装层上;本发明堆叠式影像感测器制造方法包括将集成电路固定于基板上;将封装层覆盖于集成电路上;将影像感测晶片设置于封装层上以与集成电路形成堆叠;将透光层覆设于影像感测晶片上方。组装时,藉由封装层覆盖住集成电路,使影像感测晶片可直接置放于封装层上,而与集成电路形成堆叠,如此,便可将影像感测晶片堆叠于任何尺寸的集成电路上。不仅构件少、体积小,而且制造简单、封装及测试成本低,从而达到本发明的目的。
附图说明
图1、为本发明堆叠式影像感测器结构示意剖视图。
图2、为本发明堆叠式影像感测器制造方法示意图(于基板上组接及封装集成电路)。
图3、为本发明堆叠式影像感测器制造方法示意图(设置凸缘层)。
图4、为本发明堆叠式影像感测器制造方法示意图(组接影像感测晶片)。
图5、为本发明堆叠式影像感测器结构示意剖视图(透光层为透明胶体)。
图6、为本发明堆叠式影像感测器结构示意剖视图(透光层为呈冂形透明胶体)。
具体实施方式
如图1所示,本发明堆叠式影像感测器包括基板10、集成电路12、封装层14、影像感测晶片16、凸缘层18、透光层20及复数条导线22。
基板10包括上表面24及下表面26,上表面24形成有讯号输入端28,下表面26形成有讯号输出端30,用以电连接于印刷电路板上,讯号输出端30为球栅阵列金属球。
集成电路12,其可为数位讯号处理器(digital signal processor)、微处理器(micro processor)或中央处理器(central processor unit),其系设于基板10的上表面24上,并藉由复数条导线22电连接于讯号输入端28上,使集成电路12上的讯号传递至基板10上。
封装层14其系以压模方式覆盖于集成电路12上,以将集成电路12及复数条导线22包覆住,用以保护集成电路12及复数条导线22,以避免当影像感测晶片16与集成电路12堆叠时,影像感测晶片16压损复数条导线22。
影像感测晶片16,系置于封装层14上方,而与集成电路12形成堆叠,并藉由复数条导线22电连接于基板10的讯号输入端28。
透光层20系为透光玻璃,其系盖设于影像感测晶片16上方,用以使影像感测晶片16透过透光层20接收影像讯号。本实施例中,系将凸缘层18先行设置于基板10的上表面24周缘,而透光层20系设置于凸缘层18上方,以将影像感测晶片16覆盖住。
如图2、图3、图4所示,本发明堆叠式影像感测器制造方法包括如下步骤:
于基板上组接集成电路
将集成电路12固定于基板10的上表面24上,并以复数条导线22电连接于基板10的讯号输入端28,使集成电路12与基板10形成电连接;
设置凸缘层
将用以承载透光层20的凸缘层18设置于基板10的上表面24周缘;使透光层20覆盖住影像感测晶片16。
封装集成电路
将封装层14覆盖于集成电路12上,以保护集成电路12及复数条导线22。
亦可于集成电路12固定于基板10的上表面24上,并以复数条导线22完成基板10与集成电路12的电连接后,封装层14与凸缘层18可同时以压模方式形成于基板10的上表面24上,封装层14则系覆盖住集成电路12及复数条导线22,而凸缘层18则系形成于基板10的周缘,用以承载透光层20。如此,可减化生产制程,降低生产成本。
组接影像感测晶片
如图4所示,将影像感测晶片16设置于封装层14上方,并藉由复数条导线22电连接于基板10的讯号输入端,而与集成电路12形成堆叠。
固定透光层
如图1所示,将透光层20固定于凸缘层18上方,用以将影像感测晶片16覆盖住,使影像感测晶片16得以透过透光层20接收影像讯号。
如图5所示,透光层20为透明胶体,当将集成电路12与影像感测晶片16堆叠于基板10的上表面24,并与基板10形成电连接后,再行将透明胶体直接覆盖住影像感测晶片16、集成电路12及复数条导线22,使影像感测晶片16透过该透明胶体接收影像感测讯号。
如图6所示,透光层20亦可为ㄇ形透明胶体,系覆盖于基板10的上表面24上,以将影像感测晶片16、集成电路12及复数条导线22覆盖住。藉由ㄇ形透明胶体的透光率较佳,可使影像感测晶片16接收较佳的影像讯号。
本发明具有如下的优点:
1、藉由封装层14覆盖住集成电路12,使影像感测晶片16可直接置放于封装层14上,而与集成电路12形成堆叠,如此,便可将影像感测晶片16堆叠于任何尺寸的集成电路12上。
2、本发明的封装层14与凸缘层18可同时形成于基板10上,可使堆叠封装的制程更为简便。

Claims (10)

1、一种堆叠式影像感测器,它包括形成讯号输入、输出端的基板、以复数条导线与基板讯号输入端电连接的影像感测晶片及盖设于影像感测晶片上的透光层;其特征在于所述的基板上设有以封装层封装并以复数条导线与基板讯号输入端电连接的集成电路;影像感测晶片叠置于集成电路的封装层上。
2、根据权利要求1所述的堆叠式影像感测器,其特征在于所述的基板上表面周缘形成将集成电路、封装层及影像感测晶片围绕住的凸缘层;透光层设置于凸缘层上方。
3、根据权利要求1所述的堆叠式影像感测器,其特征在于所述的透光层为覆盖集成电路、封装层及影像感测晶片的透明胶体。
4、根据权利要求3所述的堆叠式影像感测器,其特征在于所述的为透明胶体的透光层呈冂形。
5、根据权利要求1所述的堆叠式影像感测器,其特征在于所述的集成电路为数位讯号处理器(digital signal processor)、微处理器(micro processor)或中央处理器(central processor unit)。
6、一种堆叠式影像感测器制造方法,其特征在于它包括:
将集成电路固定于基板上,并与基板讯号输入端形成电连接;
将封装层覆盖于集成电路上;
将影像感测晶片设置于封装层上以与集成电路形成堆叠;
将使影像感测晶片得以透过透光层接收影像讯号的透光层覆设于影像感测晶片上方。
7、根据权利要求6所述的堆叠式影像感测器制造方法,其特征在于在将影像感测晶片上方覆设透光层前,先于基板周缘形成凸缘层。
8、根据权利要求7所述的堆叠式影像感测器制造方法,其特征在于在将封装层覆盖于集成电路上后,再将凸缘层设置于基板周缘。
9、根据权利要求7所述的堆叠式影像感测器制造方法,其特征在于所述的覆盖于集成电路上的封装层与凸缘层同时形成于基板上。
10、根据权利要求6所述的堆叠式影像感测器制造方法,其特征在于所述的覆设透光层为将呈冂形的透明胶体覆盖于基板的上表面上。
CNB011042265A 2001-02-26 2001-02-26 堆叠式影像感测器及其制造方法 Expired - Fee Related CN1162906C (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB011042265A CN1162906C (zh) 2001-02-26 2001-02-26 堆叠式影像感测器及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB011042265A CN1162906C (zh) 2001-02-26 2001-02-26 堆叠式影像感测器及其制造方法

Publications (2)

Publication Number Publication Date
CN1372322A CN1372322A (zh) 2002-10-02
CN1162906C true CN1162906C (zh) 2004-08-18

Family

ID=4653769

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB011042265A Expired - Fee Related CN1162906C (zh) 2001-02-26 2001-02-26 堆叠式影像感测器及其制造方法

Country Status (1)

Country Link
CN (1) CN1162906C (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100531310C (zh) 2006-01-14 2009-08-19 鸿富锦精密工业(深圳)有限公司 数码相机模组
US9375440B2 (en) 2006-11-03 2016-06-28 Medtronic, Inc. Compositions and methods for making therapies delivered by viral vectors reversible for safety and allele-specificity
US8324367B2 (en) 2006-11-03 2012-12-04 Medtronic, Inc. Compositions and methods for making therapies delivered by viral vectors reversible for safety and allele-specificity
TWI607223B (zh) * 2017-03-24 2017-12-01 Press-measuring mechanism for stacked package electronic components and test classification equipment for application thereof

Also Published As

Publication number Publication date
CN1372322A (zh) 2002-10-02

Similar Documents

Publication Publication Date Title
CN1606158A (zh) 互补金属氧化物半导体器件型图像传感器模块
CN103579216A (zh) 光学元件封装模块
CN1206727C (zh) 芯片封装及其制造方法
CN1913164A (zh) 影像感测芯片封装结构及应用该结构的数码相机模组
CN1956178A (zh) 光电芯片封装构造、制造方法及其芯片承载件
CN1162906C (zh) 堆叠式影像感测器及其制造方法
CN1206728C (zh) 芯片封装及其制造方法
CN1272854C (zh) 影像感测器及其封装方法
CN2470959Y (zh) 堆叠式影像感测器
CN2459831Y (zh) 一种影像感测器
CN1130767C (zh) 具有高辐射特性的半导体器件及其制造方法
CN2599757Y (zh) 影像感测器堆叠构造
CN2598146Y (zh) 影像感测器堆叠装置
CN2599758Y (zh) 堆叠式影像感测器模组构造
CN1532940A (zh) 光检测器以及光检测器的制造方法
CN2465329Y (zh) 一种影像感测器
CN1369905A (zh) 高准确度及灵敏度霍尔感测元件及集成电路的封装方法
CN1184867C (zh) 影像感测器的封装构造及其封装方法
CN1152429C (zh) 封装影像感测芯片及其封装方法
JP3502063B2 (ja) イメージセンサのスタックパッケージ構造
CN1306575C (zh) 射出成型影像感测器封装方法
CN100350619C (zh) 影像感测器及其封装方法
CN2461227Y (zh) 一种影像感测器
CN200962417Y (zh) 封装盖板与芯片封装结构
CN2638242Y (zh) 影像感测器模组封装构造

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20040818

Termination date: 20190226