CN114784105A - 半导体器件与半导体封装体 - Google Patents

半导体器件与半导体封装体 Download PDF

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Publication number
CN114784105A
CN114784105A CN202111587696.9A CN202111587696A CN114784105A CN 114784105 A CN114784105 A CN 114784105A CN 202111587696 A CN202111587696 A CN 202111587696A CN 114784105 A CN114784105 A CN 114784105A
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semiconductor device
region
gate
view
gate electrode
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CN202111587696.9A
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中柴康隆
下村彰宏
泽田雅己
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN114784105A publication Critical patent/CN114784105A/zh
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Abstract

本公开涉及半导体器件和半导体封装体。根据一个实施例的半导体器件包括：具有第一表面和在第一表面的相对侧上的第二表面的半导体衬底、形成在第一表面上的栅极绝缘膜、经由栅极绝缘膜形成在第一表面上的栅极，形成在半导体衬底的第一表面侧的源极区、形成为与源极区接触并包括沟道区的体区、形成在半导体衬底的第二表面侧的漏极区，以及形成为与体区的第二表面侧和漏极区的第一表面侧接触的漂移区。该半导体衬底具有形成在所述第二表面中且朝向第一表面凹陷的至少一个凹部部分。

Description

半导体器件与半导体封装体
相关应用的交叉引用
于2021年1月22日提交的日本专利申请号2021-008604的公开内容(包括说明书、附图和摘要)，通过整体引用并入本文。
技术领域
本发明涉及一种半导体器件和半导体封装体。
背景技术
[专利文件1]美国专利号5998833
专利文件1公开了一种具有半导体衬底、栅极绝缘膜和栅极的半导体器件。半导体衬底具有第一表面和第二表面。第二表面是与第一表面相对的表面。半导体衬底具有位于第一表面中的源极区、位于第二表面中的漏极区、与漏极区的第一表面侧接触的漂移区、以及包括被夹在源极区和漂移区之间的沟道区的基极区。
栅极沟槽被形成在第一表面中。栅极沟槽的底壁位于漂移区。沟道区从栅极沟槽的侧壁露出。栅极绝缘膜形成在栅极沟槽的侧壁和底壁上。栅极被布置在栅极沟槽内部以面对沟道区，栅极绝缘膜介于栅极和沟道区之间。
发明内容
在专利文献1中公开的半导体器件中，作为降低导通电阻的措施，考虑了通过从第二表面侧抛光半导体衬底来形成薄漏极区。然而，在这种情况下，整个半导体衬底会变薄，结果是制造过程中的处理能力恶化。
本发明提供一种半导体器件，其能够在降低导通电阻的同时保持制造过程中的处理能力。
根据一个实施例的半导体器件包括：具有第一表面和在第一表面的相对侧上的第二表面的半导体衬底、形成在第一表面上的栅极绝缘膜、经由栅极绝缘膜形成在第一表面上的栅极，形成在半导体衬底的第一表面侧的源极区、形成为与源极区接触并包括沟道区的体区、形成在半导体衬底的第二表面侧的漏极区，形成为与体区的第二表面侧和漏极区的第一表面侧接触的漂移区。该半导体衬底具有形成在所述第二表面中且朝向第一表面凹陷的至少一个凹部部分。
根据一个实施例的半导体器件，可以在降低导通电阻的同时保持制造过程中的处理能力。
附图说明
图1是半导体器件DEV1的平面图。
图2是沿图1的线II-II截取的截面图。
图3是图2的区域III的放大图。
图4是沿图1的线IV-IV截取的截面图。
图5是半导体器件DEV1的制造方法的流程图。
图6是制备步骤S1中半导体器件DEV1的截面图。
图7是外延生长步骤S2中半导体器件DEV1的截面图。
图8是第一离子注入步骤S3中半导体器件DEV1的截面图。
图9是第二离子注入步骤S4中半导体器件DEV2的截面图。
图10是沟槽形成步骤S5中半导体器件DEV1的截面图。
图11是栅极绝缘膜形成步骤S6中半导体器件DEV1的截面图。
图12是栅极形成步骤S7中半导体器件DEV1的截面图。
图13是层间绝缘膜形成步骤S8中半导体器件DEV1的截面图。
图14是衬底抛光步骤S10中半导体器件DEV1的截面图。
图15是在凹部部分形成步骤S11中半导体器件DEV1的截面图。
图16在第一电极形成步骤S12中半导体器件DEV1的截面图。
图17是第二电极形成步骤S13中半导体器件DEV1的截面图。
图18是根据第一修改示例的半导体器件DEV1的截面图。
图19是根据第二修改示例的半导体器件DEV1的截面图。
图20是根据第三修改示例的半导体器件DEV1的截面图。
图21是半导体器件DEV2的底视图。
图22是沿图21的线XXII-XXII截取的截面图。
图23是根据第一修改示例的半导体器件DEV2的底视图。
图24是根据第二修改示例的半导体器件DEV2的底视图。
图25是根据第三修改示例的半导体器件DEV2的底视图。
图26是半导体器件DEV3的底视图。
图27是沿图26的线XXVII-XXVII截取的截面图。
图28是半导体器件DEV4的截面图。
图29是半导体封装体PKG1的截面图。
图30是半导体封装体PKG2的截面图。
具体实施方式
在下文中，将参考附图来描述本发明的实施例的细节。在所有附图中，相同或对应的构件由相同的参考符号标示，并且适当地省略其冗余描述。
(第一实施例)
在下文中，将描述根据第一实施例的半导体器件(以下称为“半导体器件DEV1”)。
<半导体器件DEV1的配置>
图1是半导体器件DEV1的平面图。图2是沿图1的线II-II截取的截面图。图3是图2的区域III的放大图。图4是沿图1的线IV-IV截取的截面图。如图1至图4中所示，半导体器件DEV1具有半导体衬底SUB、栅极绝缘膜GI、栅极GA、层间绝缘膜ILD、源极电极EL1、栅极电极EL2和漏极电极EL3。
半导体衬底SUB具有第一表面FS和第二表面SS。第二表面SS是与第一表面FS相对的表面。
在平面图中(或当从与第一表面FS和第二表面SS正交的方向看时)，半导体衬底SUB具有外围区R1和单元区R2。外围区R1是平面图中位于半导体衬底外围的部分。在平面图中，单元区R2位于外围区R1的内部。单元区R2是在其中形成MOSFET(金属氧化物场效应晶体管)的单元结构的部分。
在单元区R2中，半导体衬底SUB具有源极区SR、漏极区DRA、漂移区DRI和体区BR。源极区SR、漏极区DRA和漂移区DRI中每一个的导电类型是第一导电类型。体区BR的导电类型是第二导电类型。第二导电类型是与第一导电类型相反的导电类型。例如，在第一导电类型为n型的情况下，第二导电类型为p型。源极区SR和漏极区DRA中的每一个中的杂质浓度高于漂移区DRI中的杂质浓度。
源极区SR位于第一表面FS中。漏极区DRA位于第二表面SS中。漂移区DRI形成在漏极区DRA上。即，漂移区DRI与漏极区DRA的第一表面FS侧接触。体区BR被夹在源极区SR和漂移区DRI之间。
在单元区R2中，在第一表面FS中形成栅极沟槽GTR。栅极沟槽GTR朝向第二表面SS延伸。栅极沟槽GTR的底壁位于漂移区DRI中。源极区SR、体区BR和漂移区DRI从栅极沟槽GTR的侧壁露出。从栅极沟槽GTR露出的体区BR的一部分被定义为沟道区CH。
在单元区R2中，在第二表面SS中形成凹部部分RP。在凹部部分RP中，第二表面SS朝向第一表面FS侧凹陷。如图3中所示，凹部部分RP的一部分可以形成在位于单元区R2外部的第二表面SS中。然而，凹部部分RP不形成在位于外围区R1中的第二表面SS中。
半导体衬底SUB例如由单晶硅形成。第一表面FS和第二表面SS优选地正交于单晶硅的<100>方向。凹部部分RP的侧壁与第二表面SS成角度θ。角度θ优选地是50度以上且60度以下。凹部部分RP的侧壁优选地与单晶硅的<111>方向正交。在单晶硅中，<100>方向和<111>方向之间的角度约为55度，更具体地说是54.7度。
漂移区DRI的厚度被定义为厚度T1。在其中形成凹部部分RP的部分中的漏极区DRA的厚度被定义为厚度T2。在其中未形成凹部部分RP的部分(即，外围区R1)中的漏极区DRA的厚度被定义为厚度T3。厚度T2小于厚度T3。即，半导体衬底SUB在外围区R1中具有足够的厚度。
栅极绝缘膜GI被布置在栅极沟槽GTR的侧壁和底壁上。栅极绝缘膜GI例如由氧化硅形成。栅极GA被布置在栅极沟槽GTR中。栅极绝缘膜GI介于栅极GA与栅极沟槽GTR的侧壁和底壁之间。即，栅极GA面对沟道区CH，同时被栅极绝缘膜GI绝缘。栅极GA例如由多晶硅形成。
层间绝缘膜ILD被布置在第一表面FS上。层间绝缘膜ILD例如由氧化硅形成。
源极电极EL1和栅极电极EL2被布置在层间绝缘膜ILD上。源极区SR和栅极GA通过在层间绝缘膜ILD中形成的接触插塞(未示出)，分别电连接到源极电极EL1和栅极电极EL2。源极电极EL1被布置为与单元区R2重叠。栅极电极EL2被布置为不与单元区R2重叠。漏极电极EL3形成在第二表面SS上。源极电极EL1、栅极电极EL2和漏极电极EL3例如由铝形成。
<半导体器件DEV1的制造方法>
图5是半导体器件DEV1的制造方法的流程图。如图5中所示，半导体器件DEV1的制造方法包括制备步骤S1、外延生长步骤S2、第一离子注入步骤S3、第二离子注入步骤S4、沟槽形成步骤S5、栅极绝缘膜形成步骤S6、栅极形成步骤S7，层间绝缘膜形成步骤S8和接触插塞形成步骤S9。半导体器件DEV1的制造方法进一步包括衬底抛光步骤S10、凹部部分形成步骤S11、第一电极形成步骤S12、第二电极形成步骤S13、和单片化步骤S14。第一离子注入步骤S3和第二离子注入步骤S4可在沟槽形成步骤S5、栅极绝缘膜形成步骤S6和栅极形成步骤S7之后执行。
在制备步骤S1中，制备半导体衬底SUB。图6是制备步骤S1中的半导体器件DEV1截面图。如图6中所示，在制备步骤S1中制备的半导体衬底SUB只有漏极区DRA。
在外延生长步骤S2中，形成外延层EPI。图7是外延生长步骤S2中半导体器件DEV1的截面图。如图7中所示，外延层EPI形成在漏极区DRA上。外延层EPI具有第一导电类型。外延层EPI通过例如CVD(化学气相沉积)方法形成。
图8是第一离子注入步骤S3中半导体器件DEV1的截面图。如图8中所示，在第一离子注入步骤S3中，形成体区BR。图9是第二离子注入步骤S4中半导体器件DEV2的截面图。如图9中所示，在第二离子注入步骤S4中，形成源极区SR。体区BR和源极区SR通过执行离子注入形成。在外延层EPI的未形成体区BR和源极区SR的部分成为漂移区DRI。
图10是沟槽形成步骤S5中半导体器件DEV1的截面图。如图10中所示，在沟槽形成步骤S5中，形成栅极沟槽GTR。栅极沟槽GTR通过例如执行诸如RIE(反应离子蚀刻)之类的干蚀刻形成。图11是在栅极绝缘膜形成步骤S6中的半导体器件DEV1的截面图。如图11中所示，在栅极绝缘膜形成步骤S6中，形成栅极绝缘膜GI。栅极绝缘膜GI通过执行例如热氧化而形成。
图12是栅极形成步骤S7中的半导体器件DEV1的截面图。如图12中所示，在栅极形成步骤S7中，形成栅极GA。当形成栅极GA时，首先，构成栅极GA的材料被嵌入栅极沟槽GTR中。接下来，构成栅极GA并从栅极沟槽GTR溢出的材料通过回蚀、CMP(化学机械抛光)等被去除。
图13是层间绝缘膜形成步骤S8中半导体器件DEV1的截面图。如图13中所示，在层间绝缘膜形成步骤S8中，形成层间绝缘膜ILD。层间绝缘膜ILD例如通过执行CVD方法形成。
在接触插塞形成步骤S9中，形成接触插塞。当形成接触插塞时，首先，在层间绝缘膜ILD中形成接触孔。接触孔沿厚度方向穿透层间绝缘膜ILD。例如，通过执行诸如RIE之类的干蚀刻来形成接触孔。接下来，通过CVD方法将构成接触插塞的材料嵌入接触孔中。然后，构成接触插塞并从接触孔溢出的材料通过回蚀、CMP等被去除。
图14是衬底抛光步骤S10中半导体器件DEV1的截面图。如图14中所示，在衬底抛光步骤S10中，在半导体衬底SUB的第二表面SS侧执行抛光。结果，漏极区DRA的厚度成为厚度T3。
图15是凹部部分形成步骤S11中半导体器件DEV1的截面图。如图15中所示，在凹部部分形成步骤S11中，形成凹部部分RP。当形成凹部部分RP时，首先，在第二表面SS上形成掩模。例如通过CVD等在第二表面SS上形成氧化硅膜，并图案化所形成的氧化硅膜，形成了掩模。
接下来，从掩模中的开口蚀刻半导体衬底SUB以形成凹部部分RP。优选地，通过使用四甲基氢氧化铵(TMAH)进行湿蚀刻来执行蚀刻。在使用TMAH对单晶硅执行湿蚀刻的情况下，晶体取向之间的蚀刻速率有显著不同。因此，在第二表面SS与单晶硅的<100>方向正交的情况下，与单晶硅的<111>方向正交的表面从凹部部分RP的侧壁露出，并且角度θ变成50度以上且60度以下。
作为凹部部分形成步骤S11的结果，在其中形成凹部部分RP的部分中，漏极区DRA变薄，并且漏极区DRA的厚度T3变成厚度T2。即，作为凹部部分形成步骤S11的结果，在形成凹部部分RP的位置处的漏极区DRA的厚度变得比在未形成凹部部分RP的位置处(即，外围区R1)的厚度更薄。
图16是第一电极形成步骤S12中半导体器件DEV1的截面图。如图16中所示，在第一电极形成步骤S12中，形成源极电极EL1和栅极电极EL2。
当形成源极电极EL1和栅极电极EL2时，首先，通过溅射等将构成源极电极EL1(栅极电极EL2)的材料沉积在层间绝缘膜ILD上。接下来，对构成源极电极EL1(栅极电极EL2)的沉积材料进行图案化以形成源极电极EL1和栅极电极EL2。
图17是第二电极形成步骤S13中半导体器件DEV1的截面图。如图17中所示，在第二电极形成步骤S13中，形成漏极电极EL3。通过执行例如溅射方法、电镀方法等形成漏极电极EL3。在单片化(singulation)步骤S14中，执行半导体器件DEV1的单片化。例如，通过使用切割刀片来执行分离。以这种方式，制造出具有图1到图4中所示结构的半导体器件DEV1。
<半导体器件DEV1的效果>
在半导体器件DEV1中，由于在其中形成凹部部分RP的部分中漏极区DRA的厚度薄，导通电阻降低。例如，当漂移区DRI的厚度是5μm时，漂移区DRI的电阻率是0.12Ω·cm，漏极区DRA的电阻率是0.8mΩ·cm，并且凹部部分RP被形成以使漏极区DRA的厚度从150μm到5μm，可以将导通电阻降低约20％(在漏极区DRA的厚度是150μm的情况下，导通电阻变成0.12Ω·cm×5μm+0.8mΩ·cm×150μm≈7.2mΩ·mm2，并且在漏极区DRA的厚度减至5μm的情况下，导通电阻变成0.12Ω·cm×5μm+0.8mΩ×5μm≈6.0mΩ·mm2)。
另一方面，由于漏极区DRA的厚度在其中未形成凹部部分RP的部分中(即，在外围区R1中)被保持，因此保持了制造过程中的处理能力。
即，在外围区R1中的凹部部分RP的厚度较薄的情况下，在单片化步骤S14中难以使用切割刀片切割半导体衬底SUB。然而，在半导体器件DEV1中，由于保持了外围区R1中的漏极区DRA的厚度，因此可以使用切割刀片切割半导体衬底SUB。因此，根据半导体器件DEV1，可以在降低导通电阻的同时保持制造过程中的处理能力。
在第二表面SS与单晶硅的<100>方向正交的情况下，可以通过在凹部部分RP上使用TMAH进行湿蚀刻，使角度θ为50度以上且60度以下。即，在这种情况下，可以形成锥形凹部部分RP。结果，当形成漏极电极EL3时，可以抑制漏极电极EL3变得局部较薄(在该步骤中，漏极电极EL3中发生断开)。
<第一修改示例>
图18是根据第一修改示例的半导体器件DEV1的截面图。如图18中所示，栅极沟槽GTR不需要形成在半导体衬底SUB中。即，半导体器件DEV1可以是平面栅型MOSFET而不是沟槽栅型MOSFET。在第一修改示例中，栅极绝缘膜GI被布置在第一表面FS上露出的沟道区CH上，并且栅极GA被布置在栅极绝缘膜GI上。
图19是根据第二修改示例的半导体器件DEV1的截面图。如图19中所示，半导体衬底SUB可以具有柱状区PR。柱状区PR从体区BR朝向第二表面SS侧延伸。柱状区PR的导电类型为第二导电类型(p型)。即，半导体器件DEV1可以是具有超级结结构的MOSFET。在这种情况下，由于漂移区DRI的杂质浓度被设置得相对较高，因此通过在凹部部分RP变得相对较大的位置具有薄漏极区DRA来降低导通电阻的效果变差。
第一表面FS和第二表面SS与单晶硅的<110>方向正交。图20是根据第三修改示例的半导体器件DEV1的截面图。在这种情况下，如图20中所示，通过在凹部部分RP上使用TMAH执行湿蚀刻，角度θ变成大约90度。
(第二实施例)
在下文中，将描述根据第二实施例的半导体器件(以下称为“半导体器件DEV2”)。在此，将主要描述与半导体器件DEV1不同的点，并且将适当地省略冗余描述。
<半导体器件DEV2的配置>
图21是半导体器件DEV2的底视图。图22是沿图21的线XXII-XXII截取的截面图。如图21和图22中所示，半导体器件DEV2具有半导体衬底SUB、栅极绝缘膜GI、栅极GA、层间绝缘膜ILD、源极电极EL1、栅极电极EL2和漏极电极EL3。在单元区R2中，凹部部分RP形成在第二表面SS中。在这方面，半导体器件DEV2的配置与半导体器件DEV1的配置相同。
半导体器件DEV2具有多个凹部部分RP。在平面图中，半导体器件DEV2中的多个凹部部分RP以网格状布置。例如，这种网格状布置是正方形网格状布置。就此而言，半导体器件DEV2的配置不同于半导体器件DEV1的配置。在平面图中，凹部部分RP例如具有矩形形状。
两个相邻凹部部分RP之间的间距被定义为间距P。凹部部分RP的相对侧壁之间的最小距离被定义为宽度W。间距P优选地大于宽度W。通过将宽度W除以间距P获得的值优选地是0.1以上且0.4以下。凹部部分RP优选地形成在平面图中不与栅极电极EL2重叠的位置。栅极电极EL2位于其在平面图中不与单元区重叠的位置。
<半导体器件DEV2的效果>
可能存在这样的情况，即在源极电极EL1和栅极电极EL2上执行引线键合。由于在半导体器件DEV1中形成一个相对较大的凹部部分RP，因此当执行引线键合时，负载被施加到半导体衬底SUB以使得半导体衬底SUB弯曲，并且半导体衬底SUB有开裂的风险。
另一方面，由于在半导体器件DEV2中以网格状布置形成相对较小的凹部部分，所以在引线键合时施加的负载可以由凹部部分RP之间的第二表面SS支撑。因此，根据半导体器件DEV2，可以抑制由在引线键合时施加的负载引起的半导体衬底SUB的开裂。
在通过将宽度W除以间距P而获得的值是0.1或更大和0.4或更小的情况下，可以在降低与凹部部分RP形成相关联的导通电阻的同时，确保抵抗在引线键合时施加的负载的强度。
在凹部部分RP被布置在平面图中不与栅极电极EL2重叠的位置的情况下，可以抑制由在栅极电极EL2上执行线键合时施加的负载引起的半导体衬底SUB的开裂。由于栅极电极EL2位于其在平面图中不与单元区R2重叠的位置，因此即使在其在平面图中与栅极电极EL2重叠的位置未形成凹部部分RP，导通电阻也几乎不增加。
<第一修改示例>
图23是根据第一修改示例的半导体器件DEV2的底视图。如图23中所示，凹部部分RP不需要以正方形网格方式进行布置。例如，凹部部分RP可以交错方式来布置。
图24是根据第二修改示例的半导体器件DEV2的底视图。图25是根据第三修改示例的半导体器件DEV2的底视图。如图24和图25中所示，凹部部分RP的平面形状不必是矩形。如图24中所示，凹部部分RP的平面形状可以是除矩形以外的多边形形状，并且如图25中所示，凹部部分RP的平面形状可以是圆形(或椭圆形)。
(第三实施例)
在下文中，将描述根据第三实施例的半导体器件(以下称为“半导体器件DEV3”)。在此，将主要描述与半导体器件DEV1不同的点，并且将适当地省略冗余描述。
<半导体器件DEV3的配置>
图26是半导体器件DEV3的底视图。图27是沿图26的线XXVII-XXVII截取的截面图。如图26和图27中所示，半导体器件DEV3具有半导体衬底SUB、栅极绝缘膜GI、栅极GA、层间绝缘膜ILD、源极电极EL1、栅极电极EL2和漏极电极EL3。就此而言，半导体器件DEV3的配置与半导体器件DEV1的配置相同。
半导体器件DEV3具有形成为凹部部分RP的多个凹槽TR。就此而言，半导体器件DEV3的配置不同于半导体器件DEV1的配置。
在平面图中，凹槽TR沿第一方向DR1延伸。多个凹槽TR被布置为在第二方向DR2上彼此间隔开。第二方向DR2是与第一方向DR1正交的方向。每个凹槽TR优选地形成在其在平面图中不与栅极电极EL2重叠的位置处。
在平面图中，栅极沟槽GTR的延伸方向优选地沿第一方向DR1延伸。即，栅极沟槽GTR的延伸方向优选地平行于每个沟槽TR的延伸方向。然而，栅极沟槽GTR的延伸方向可以沿第二方向DR2延伸。
<半导体器件DEV3的效果>
由于在半导体器件DEV3中形成了多个凹槽TR，因此在引线键合时施加的负载可以由凹槽TR之间的第二表面SS支撑。因此，根据半导体器件DEV3，可以抑制由在引线键合时施加的负载引起的半导体衬底SUB的开裂。在每个凹槽TR的延伸方向沿栅极沟槽GTR的延伸方向延伸的情况下，可以进一步降低导通电阻。
(第四实施例)
在下文中，将描述根据第四实施例的半导体器件(以下称为“半导体器件DEV4”)。在此，将主要描述与半导体器件DEV1不同的点，并且将适当地省略冗余描述。
<半导体器件DEV4的配置>
图28是半导体器件DEV4的截面图。如图28中所示，半导体器件DEV4具有半导体衬底SUB、栅极绝缘膜GI、栅极GA、层间绝缘膜ILD、源极电极EL1、栅极电极EL2和漏极电极EL3。在单元区R2中，凹部部分RP形成在第二表面SS中。就此而言，半导体器件DEV3的配置与半导体器件DEV1的配置相同。
半导体器件DEV4还具有导体CB。就此而言，半导体器件DEV4的配置不同于半导体器件DEV1的配置。导体CB被嵌入凹部部分RP中。导体CB例如由银粒子的烧结体形成。然而，导体CB不限于由这种烧结体形成。
<半导体器件DEV4的效果>
由于导体CB被嵌入半导体器件DEV3中的凹部部分RP中，因此在引线键合时施加的负载也由导体CB支撑。因此，根据半导体器件DEV4，可以抑制由在引线键合时施加的负载引起的半导体衬底SUB的开裂。
(第五实施例)
在下文中，将描述根据第五实施例的半导体封装体(下文中称为“半导体封装体PKG1”)。
<半导体封装体PKG1的配置>
图29是半导体封装体PKG1的截面图。如图29中所示，半导体封装体PKG1具有半导体器件DEV1和引线框架LF。引线框架LF具有管芯焊盘DP。管芯焊盘DP具有凸出部分PP。引线框架LF例如由铜、铜合金等形成。
半导体器件DEV1被布置为使得第二表面SS面对引线框架LF(管芯焊盘DP)。作为结果，凸出部分PP被插入凹部部分RP中。尽管未示出，但漏极电极EL3和引线框架LF(管芯焊盘DP)例如通过焊料被连接。键合引线BW被连接到源极电极EL1和栅极电极EL2中每一个。
<半导体封装体PKG1的效果>
在半导体封装体PKG1中，由于在对源极电极EL1和栅极电极EL2中每一个进行键合引线BW的引线键合时施加的负载也由凸起部分PP支撑，因此可以抑制由在线键合时施加的负载引起的半导体衬底SUB的开裂。
(第六实施例)
在下文中，将描述根据第六实施例的半导体封装体(以下称为“半导体封装体PKG2”)。
<半导体封装体PKG2的配置>
图30是半导体封装体PKG2的截面图。如图30中所示，半导体封装体PKG2具有半导体器件DEV1和引线框架LF。引线框架LF具有管芯焊盘DP。管芯焊盘DP被分为第一部分DP1和第二部分DP2。
半导体器件DEV1被布置为使得第一表面FS面对引线框架LF(管芯焊盘DP)。源极电极EL1和栅极电极EL2分别被连接到第一部分DP1和第二部分DP2。源极电极EL1和第一部分DP1以及栅极电极EL2和第二部分DP2例如通过焊料(未示出)被连接。键合引线BW被连接到位于凹部部分RP的底壁上的漏极电极EL3的一部分。
<半导体封装体PKG2的效果>
在半导体封装体PKG2中，由于未在源极电极EL1和栅极电极EL2上执行引线键合，因此可以抑制由引线键合时施加的负载引起的半导体衬底SUB的开裂。
在前述内容中，已经基于实施例具体地描述了由本发明人做出的发明。然而，无需多言，本发明不限于上述实施例，并且可以在本发明的范围内进行各种修改和改变。

Claims (15)

1.一种半导体器件，包括：
半导体衬底，具有第一表面和第二表面，所述第二表面在所述第一表面的相对侧上；
栅极绝缘膜，形成在所述第一表面上；
栅极，经由所述栅极绝缘膜形成所述第一表面上；
源极区，形成在所述半导体衬底的第一表面侧；
体区，形成为与所述源极区接触并且包括沟道区；
漏极区，形成在所述半导体衬底的第二表面侧；和
漂移区，形成为与所述体区的第二表面侧和所述漏极区的第一表面侧接触，
其中所述栅极面对所述沟道区，所述栅极绝缘膜介于所述栅极和所述沟道区之间，并且
其中所述半导体衬底具有至少一个凹部部分，所述至少一个凹部部分形成在所述第二表面中并且朝向所述第一表面凹陷。
2.根据权利要求1所述的半导体器件，
其中所述半导体衬底由单晶硅形成，并且
其中所述第一表面和所述第二表面与所述单晶硅的<100>方向正交。
3.根据权利要求2所述的半导体器件，
其中所述至少一个凹部部分的侧壁与所述第二表面成50度以上且60度以下的角度。
4.根据权利要求2所述的半导体器件，
其中所述至少一个凹部部分的侧壁是与所述单晶硅的<111>方向正交的表面。
5.根据权利要求1所述的半导体器件，
其中所述至少一个凹部部分是在平面图中以网格状布置进行布置的多个凹部部分。
6.根据权利要求5所述的半导体器件，
其中所述多个凹部部分在平面图中各自具有多边形形状或圆形形状。
7.根据权利要求5所述的半导体器件，还包括：
栅极电极，所述栅极电极形成在所述第一表面上并且被电连接到所述栅极，
其中所述多个凹部部分位于在平面图中所述多个凹部部分不与所述栅极电极重叠的位置处。
8.根据权利要求5所述的半导体器件，
其中通过将所述多个凹部部分的相对的侧壁之间的最小距离除以两个相邻凹部部分之间的间距而获得的值是0.1以上且0.4以下。
9.根据权利要求1所述的半导体器件，
其中所述至少一个凹部部分是多个凹槽，所述多个凹槽沿第一方向延伸并且被布置为在与所述第一方向相交的第二方向上彼此间隔开。
10.根据权利要求9所述的半导体器件，
其中在平面图中沿所述第一方向延伸的栅极沟槽形成在所述第一表面中，
其中所述沟道区从所述栅极沟槽的侧壁露出，并且
其中所述栅极形成在所述栅极沟槽内部以面对所述沟道区，所述栅极绝缘膜介于所述栅极和所述沟道区之间。
11.根据权利要求9所述的半导体器件，还包括：
栅极电极，形成在所述第一表面上并且被电连接到所述栅极，
其中所述多个凹槽位于在平面图中所述多个凹槽不与所述栅极电极重叠的位置。
12.根据权利要求1所述的半导体器件，还包括：
导体，被填充在所述至少一个凹部部分中。
13.根据权利要求1所述的半导体器件，
其中在所述至少一个凹部部分被形成的位置处，所述漏极区的厚度小于所述漂移区的厚度。
14.一种半导体封装体，包括：
引线框架；和
根据权利要求1所述的半导体器件，所述半导体器件被布置为使得所述第二表面面对所述引线框架，以及
其中所述引线框架具有被插入所述至少一个凹部部分中的至少一个凸出部分。
15.一种半导体封装体，包括：
引线框架；和
根据权利要求1所述的半导体器件，所述半导体器件被布置为使得所述第一表面面对所述引线框架侧。
CN202111587696.9A 2021-01-22 2021-12-23 半导体器件与半导体封装体 Pending CN114784105A (zh)

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