TW202245189A - 半導體裝置及半導體封裝 - Google Patents

半導體裝置及半導體封裝 Download PDF

Info

Publication number
TW202245189A
TW202245189A TW111100420A TW111100420A TW202245189A TW 202245189 A TW202245189 A TW 202245189A TW 111100420 A TW111100420 A TW 111100420A TW 111100420 A TW111100420 A TW 111100420A TW 202245189 A TW202245189 A TW 202245189A
Authority
TW
Taiwan
Prior art keywords
semiconductor device
gate
region
view
concave portion
Prior art date
Application number
TW111100420A
Other languages
English (en)
Inventor
中柴康隆
下村彰宏
沢田雅己
Original Assignee
日商瑞薩電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商瑞薩電子股份有限公司 filed Critical 日商瑞薩電子股份有限公司
Publication of TW202245189A publication Critical patent/TW202245189A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0886—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08245—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/08258—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the bonding area connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8336—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/83365—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

根據一項實施例之半導體裝置包含：一半導體基板，其具有一第一表面及在該第一表面之一相對側上之一第二表面；一閘極絕緣膜，其形成於該第一表面上；一閘極，其經由該閘極絕緣膜形成於該第一表面上；一源極區，其形成於該半導體基板之第一表面側中；一本體區，其形成以與該源極區接觸且包含一通道區；一汲極區，其形成於該半導體基板之第二表面側中；及一漂移區，其形成以與該本體區之第二表面側及該汲極區之第一表面側接觸。該半導體基板具有形成於該第二表面中且朝向該第一表面凹陷之至少一個凹入部分。

Description

半導體裝置及半導體封裝
本發明係關於一種半導體裝置及一種半導體封裝。
存在下文列出的所揭示技術。[專利文件1]美國專利第5,998,833號
專利文件1揭示具有一半導體基板、一閘極絕緣膜及一閘極之一半導體裝置。該半導體基板具有一第一表面及一第二表面。該第二表面係與該第一表面相對之一表面。該半導體基板具有定位於該第一表面中之一源極區、定位於該第二表面中之一汲極區、與該汲極區之第一表面側接觸之一漂移區及包含夾置於該源極區與該漂移區之間之一通道區之一基極區。
一閘極溝槽形成於第一表面中。該閘極溝槽之一底壁定位於漂移區中。從該閘極溝槽之一側壁曝露一通道區。一閘極絕緣膜形成於該閘極溝槽之該側壁及該底壁上。閘極經配置於該閘極溝槽內部以面向通道區且該閘極絕緣膜插置於其間。
在專利文件1中揭示之半導體裝置中，作為減小一接通電阻之一措施，考慮藉由從第二表面側拋光半導體基板而形成一薄汲極區。然而，在此情況中，整個半導體基板將變薄，且因此，製程中之處置能力劣化。
本發明提供能夠維持製程中之處置能力同時減小接通電阻之一半導體裝置。
根據一項實施例之半導體裝置包括：一半導體基板，其具有一第一表面及在該第一表面之一相對側上之一第二表面；一閘極絕緣膜，其形成於該第一表面上；一閘極，其經由該閘極絕緣膜形成於該第一表面上；一源極區，其形成於該半導體基板之第一表面側上；一本體區，其形成以與該源極區接觸且包含一通道區；一汲極區，其形成於該半導體基板之第二表面側上；及一漂移區，其形成以與該本體區之該第二表面側及該汲極區之該第一表面側接觸。閘極面向通道區且閘極絕緣膜插置於其間。半導體基板具有形成於第二表面中且朝向第一表面凹陷之至少一個凹入部分。
根據一項實施例之半導體裝置，可維持製程中之處置能力同時減小接通電阻。
下文中，將參考圖式來描述本發明之實施例之細節。在全部隨附圖式中，藉由相同元件符號表示相同或對應部件，且適當地省略其等之冗餘描述。
(第一實施例) 下文中，將描述根據一第一實施例之一半導體裝置(下文中被稱為「半導體裝置DEV1」)。
＜半導體裝置DEV1之組態＞ 圖1係半導體裝置DEV1之一平面圖。圖2係沿著圖1之一線II-II截取之一橫截面視圖。圖3係圖2之一區III之一放大圖。圖4係沿著圖1之一線IV-IV截取之一橫截面視圖。如圖1至圖4中展示，半導體裝置DEV1具有一半導體基板SUB、一閘極絕緣膜GI、一閘極GA、一層間絕緣膜ILD、一源極電極EL1、一閘極電極EL2及一汲極電極EL3。
半導體基板SUB具有一第一表面FS及一第二表面SS。第一表面FS及第二表面SS係半導體基板SUB之一厚度方向上之端面。第二表面SS係與第一表面FS相對之一表面。
在平面圖中(或當從正交於第一表面FS及第二表面SS之一方向觀看時)，半導體基板SUB具有一外周邊區R1及一單元區R2。外周邊區R1係在平面圖中定位於半導體基板SUB之一外周邊處之一部分。在平面圖中，單元區R2定位於外周邊區R1內部。單元區R2係形成一MOSFET (金屬氧化物場效應電晶體)之一單元結構之一部分。
在單元區R2中，半導體基板SUB具有一源極區SR、一汲極區DRA、一漂移區DRI及一本體區BR。源極區SR、汲極區DRA及漂移區DRI之各者之一導電性類型係一第一導電性類型。本體區BR之一導電性類型係一第二導電性類型。第二導電性類型係與第一導電性類型相反之一導電性類型。舉例而言，在第一導電性類型係n型之情況中，第二導電性類型係p型。源極區SR及汲極區DRA之各者中之一雜質濃度高於漂移區DRI中之一雜質濃度。
源極區SR定位於第一表面FS中。汲極區DRA定位於第二表面SS中。漂移區DRI形成於汲極區DRA上。即，漂移區DRI與汲極區DRA之第一表面FS側接觸。本體區BR夾置於源極區SR與漂移區DRI之間。
在單元區R2中，一閘極溝槽GTR形成於第一表面FS中。閘極溝槽GTR延伸朝向第二表面SS。閘極溝槽GTR之一底壁定位於漂移區DRI中。從閘極溝槽GTR之一側壁曝露源極區SR、本體區BR及漂移區DRI。從閘極溝槽GTR曝露之本體區BR之一部分被定義為一通道區CH。
在單元區R2中，一凹入部分RP形成於第二表面SS中。在凹入部分RP中，第二表面SS朝向第一表面FS側凹陷。如圖3中展示，凹入部分RP之一部分可形成於定位於單元區R2外部之第二表面SS中。然而，凹入部分RP未形成於定位於外周邊區R1中之第二表面SS中。
半導體基板SUB係由舉例而言單晶矽形成。第一表面FS及第二表面SS較佳地正交於單晶矽之一＜100＞方向。凹入部分RP之一側壁相對於第二表面SS成一角度θ。角度θ較佳地係50度或更大及60度或更小。凹入部分RP之側壁較佳地正交於單晶矽之一＜111＞方向。在單晶矽中，＜100＞方向與＜111＞方向之間之一角度係近似55度，且更明確言之係54.7度。
漂移區DRI之一厚度被定義為一厚度T1。形成凹入部分RP之一部分中之汲極區DRA之一厚度被定義為一厚度T2。未形成凹入部分RP之一部分(即，外周邊區R1)中之汲極區DRA之一厚度被定義為一厚度T3。厚度T2小於厚度T3。即，半導體基板SUB在外周邊區R1中具有一足夠厚度。
閘極絕緣膜GI經配置於閘極溝槽GTR之側壁及底壁上。閘極絕緣膜GI係由舉例而言氧化矽形成。閘極GA經配置於閘極溝槽GTR中。閘極絕緣膜GI插置於閘極GA與閘極溝槽GTR之側壁及底壁之間。即，閘極GA面向通道區CH同時藉由閘極絕緣膜GI絕緣。閘極GA係由舉例而言多晶矽形成。
層間絕緣膜ILD經配置於第一表面FS上。層間絕緣膜ILD係由舉例而言氧化矽形成。
源極電極EL1及閘極電極EL2經配置於層間絕緣膜ILD上。源極區SR及閘極GA藉由形成於層間絕緣膜ILD中之接觸插塞(未展示)分別且電連接至源極電極EL1及閘極電極EL2。源極電極EL1經配置以便與單元區R2重疊。閘極電極EL2經配置以便不與單元區R2重疊。汲極電極EL3形成於第二表面SS上。源極電極EL1、閘極電極EL2及汲極電極EL3係由舉例而言鋁形成。
＜半導體裝置DEV1之製造方法＞ 圖5係半導體裝置DEV1之一製造方法之一流程圖。如圖5中展示，半導體裝置DEV1之製造方法包含一製備步驟S1、一磊晶生長步驟S2、一第一離子植入步驟S3、一第二離子植入步驟S4、一溝槽形成步驟S5、一閘極絕緣膜形成步驟S6、一閘極形成步驟S7、一層間絕緣膜形成步驟S8及一接觸插塞形成步驟S9。半導體裝置DEV1之製造方法進一步包含一基板拋光步驟S10、一凹入部分形成步驟S11、一第一電極形成步驟S12、一第二電極形成步驟S13及一單粒化步驟S14。可在溝槽形成步驟S5、閘極絕緣膜形成步驟S6及閘極形成步驟S7之後執行第一離子植入步驟S3及第二離子植入步驟S4。
在製備步驟S1中，製備半導體基板SUB。圖6係製備步驟S1中之半導體裝置DEV1之一橫截面視圖。如圖6中展示，在製備步驟S1中製備之半導體基板SUB僅具有汲極區DRA。
在磊晶生長步驟S2中，形成一磊晶層EPI。圖7係磊晶生長步驟S2中之半導體裝置DEV1之一橫截面視圖。如圖7中展示，磊晶層EPI形成於汲極區DRA上。磊晶層EPI具有第一導電性類型。藉由舉例而言一CVD (化學氣相沈積)方法形成磊晶層EPI。
圖8係第一離子植入步驟S3中之半導體裝置DEV1之一橫截面視圖。如圖8中展示，在第一離子植入步驟S3中，形成本體區BR。圖9係第二離子植入步驟S4中之一半導體裝置DEV2之一橫截面視圖。如圖9中展示，在第二離子植入步驟S4中，形成源極區SR。藉由執行離子植入形成本體區BR及源極區SR。未形成本體區BR及源極區SR之磊晶層EPI之一部分成為漂移區DRI。
圖10係溝槽形成步驟S5中之半導體裝置DEV1之一橫截面視圖。如圖10中展示，在溝槽形成步驟S5中，形成閘極溝槽GTR。藉由執行舉例而言乾式蝕刻(諸如RIE (反應性離子蝕刻) )而形成閘極溝槽GTR。圖11係閘極絕緣膜形成步驟S6中之半導體裝置DEV1之一橫截面視圖。如圖11中展示，在閘極絕緣膜形成步驟S6中，形成閘極絕緣膜GI。藉由執行舉例而言熱氧化而形成閘極絕緣膜GI。
圖12係閘極形成步驟S7中之半導體裝置DEV1之一橫截面視圖。如圖12中展示，在閘極形成步驟S7中，形成閘極GA。在形成閘極GA時，首先，構成閘極GA之一材料嵌入閘極溝槽GTR中。接著，藉由回蝕、CMP (化學機械拋光)或類似者移除構成閘極GA且從閘極溝槽GTR溢出之材料。
圖13係層間絕緣膜形成步驟S8中之半導體裝置DEV1之一橫截面視圖。如圖13中展示，在層間絕緣膜形成步驟S8中，形成層間絕緣膜ILD。藉由執行舉例而言CVD方法形成層間絕緣膜ILD。
在接觸插塞形成步驟S9中，形成接觸插塞。在形成接觸插塞時，首先，一接觸孔形成於層間絕緣膜ILD中。接觸孔沿厚度方向穿透層間絕緣膜ILD。藉由執行舉例而言乾式蝕刻(諸如RIE)而形成接觸孔。接著，藉由CVD方法將構成接觸插塞之一材料嵌入接觸孔中。接著，藉由回蝕、CMP或類似者移除構成接觸插塞且從接觸孔溢出之材料。
圖14係基板拋光步驟S10中之半導體裝置DEV1之一橫截面視圖。如圖14中展示，在基板拋光步驟S10中，對半導體基板SUB之第二表面SS側執行拋光。因此，汲極區DRA之厚度變成厚度T3。
圖15係凹入部分形成步驟S11中之半導體裝置DEV1之一橫截面視圖。如圖15中展示，在凹入部分形成步驟S11中，形成凹入部分RP。在形成凹入部分RP時，首先，一遮罩形成於第二表面SS上。藉由舉例而言藉由CVD或類似者在第二表面SS上形成氧化矽膜且圖案化所形成之氧化矽膜而形成遮罩。
接著，從遮罩中之一開口蝕刻半導體基板SUB以形成凹入部分RP。較佳地藉由使用四甲基氫氧化銨(TMAH)之濕式蝕刻執行蝕刻。在對單晶矽執行使用TMAH之濕式蝕刻之一情況中，一蝕刻速率在晶體定向之間顯著不同。因此，在第二表面SS正交於單晶矽之＜100＞方向之一情況中，從凹入部分RP之側壁曝露正交於單晶矽之＜111＞方向之表面，且角度θ變成50度或更大及60度或更小。
作為凹入部分形成步驟S11之結果，汲極區DRA在形成凹入部分RP之部分中變薄，且汲極區DRA之厚度T3變成厚度T2。即，作為凹入部分形成步驟S11之結果，形成凹入部分RP之位置處之汲極區DRA之厚度變得比未形成凹入部分RP之位置(即，外周邊區R1)處更薄。
圖16係第一電極形成步驟S12中之半導體裝置DEV1之一橫截面視圖。如圖16中展示，在第一電極形成步驟S12中，形成源極電極EL1及閘極電極EL2。
在形成源極電極EL1及閘極電極EL2時，首先，藉由濺鍍或類似者將構成源極電極EL1 (閘極電極EL2)之一材料沈積於層間絕緣膜ILD上。接著，構成源極電極EL1 (閘極電極EL2)之經沈積材料經圖案化以形成源極電極EL1及閘極電極EL2。
圖17係第二電極形成步驟S13中之半導體裝置DEV1之一橫截面視圖。如圖17中展示，在第二電極形成步驟S13中，形成汲極電極EL3。藉由執行舉例而言一濺鍍方法、一鍍覆方法或類似者而形成汲極電極EL3。在單粒化步驟S14中，執行半導體裝置DEV1之單粒化。藉由使用舉例而言一切割刀片執行單粒化。以此方式，製造具有圖1至圖4中展示之一結構之半導體裝置DEV1。
＜半導體裝置DEV1之效應＞ 在半導體裝置DEV1中，由於汲極區DRA之厚度在形成凹入部分RP之部分中係薄的，故減小接通電阻。舉例而言，當漂移區DRI之厚度係5 μm時，漂移區DRI之一電阻率係0.12 Ω·cm，汲極區DRA之一電阻率係0.8 mΩ·cm，且形成凹入部分RP以使汲極區DRA之厚度為150 μm至5 μm時，可將接通電阻減小達約20% (在汲極區DRA之厚度係150 μm之一情況中，接通電阻變成0.12 Ω·cm × 5 μm ＋ 0.8 mΩ·cm × 150 μm ≈ 7.2 mΩ·mm 2，且在汲極區DRA之厚度減小至5 μm之一情況中，接通電阻變成0.12 Ω·cm × 5 μm ＋ 0.8 mΩ× 5 μm ≈ 6.0 mΩ·mm 2)。
另一方面，由於在未形成凹入部分RP之部分中(即，在外周邊區R1中)維持汲極區DRA之厚度，故維持製程中之處置能力。
即，在外周邊區R1中之凹入部分RP之厚度係薄的之一情況中，將難以在單粒化步驟S14中使用切割刀片來切割半導體基板SUB。然而，在半導體裝置DEV1中，由於維持外周邊區R1中之汲極區DRA之厚度，故可使用切割刀片來切割半導體基板SUB。因此，根據半導體裝置DEV1，可維持製程中之處置能力同時減小接通電阻。
在第二表面SS正交於單晶矽之＜100＞方向之一情況中，可藉由對凹入部分RP執行使用TMAH之濕式蝕刻而使角度θ為50度或更大及60度或更小。即，在此情況中，可形成一錐形凹入部分RP。因此，在形成汲極電極EL3時，可抑制汲極電極EL3局部變薄(在該步驟中在汲極電極EL3中發生斷開連接)。
＜第一修改實例＞ 圖18係根據一第一修改實例之半導體裝置DEV1之一橫截面視圖。如圖18中展示，閘極溝槽GTR無需形成於半導體基板SUB中。即，半導體裝置DEV1可為一平面閘極型MOSFET而非一溝槽閘極型MOSFET。在第一修改實例中，閘極絕緣膜GI經配置於曝露於第一表面FS上之通道區CH上，且閘極GA經配置於閘極結緣膜GI上。
圖19係根據一第二修改實例之半導體裝置DEV1之一橫截面視圖。如圖19中展示，半導體基板SUB可具有一柱區PR。柱區PR從本體區BR延伸朝向第二表面SS側。柱區PR之導電性類型係第二導電性類型(p型)。即，半導體裝置DEV1可為具有一超接面結構之一MOSFET。在此情況中，由於漂移區DRI之雜質濃度經設定為相對較高，故藉由在凹入部分RP之位置處具有一薄汲極區DRA而減小接通電阻之效應變得相對較大。
第一表面FS及第二表面SS正交於單晶矽之＜110＞方向。圖20係根據一第三修改實例之半導體裝置DEV1之一橫截面視圖。在此情況中，如圖20中展示，藉由對凹入部分RP執行使用TMAH之濕式蝕刻，角度θ變為近似90度。
(第二實施例) 下文中，將描述根據一第二實施例之一半導體裝置(下文中被稱為「半導體裝置DEV2」)。此處，將主要描述不同於半導體裝置DEV1之要點，且將適當地省略冗餘描述。
＜半導體裝置DEV2之組態＞ 圖21係半導體裝置DEV2之一仰視圖。圖22係沿著圖21之一線XXII-XXII截取之一橫截面視圖。如圖21及圖22中展示，半導體裝置DEV2具有半導體基板SUB、閘極絕緣膜GI、閘極GA、層間絕緣膜ILD、源極電極EL1、閘極電極EL2及汲極電極EL3。在單元區R2中，凹入部分RP形成於第二表面SS中。在此方面，半導體裝置DEV2之組態與半導體裝置DEV1之組態係共同的。
半導體裝置DEV2具有複數個凹入部分RP。在平面圖中，半導體裝置DEV2中之複數個凹入部分RP經配置成一柵格狀配置。此柵格狀配置係舉例而言一方形柵格配置。在此方面，半導體裝置DEV2之組態不同於半導體裝置DEV1之組態。在平面圖中，凹入部分RP具有舉例而言一矩形形狀。
兩個鄰近凹入部分RP之間之一節距被定義為一節距P。凹入部分RP之相對側壁之間之一最小距離被定義為一寬度W。節距P較佳地大於寬度W。藉由將寬度W除以節距P所獲取之一值較佳地係0.1或更大及0.4或更小。凹入部分RP較佳地形成於其在平面圖中不與閘極電極EL2重疊之一位置處。閘極電極EL2位於其在平面圖中不與單元區重疊之一位置處。
＜半導體裝置DEV2之效應＞ 可能存在在源極電極EL1及閘極電極EL2上執行打線接合的情況。由於一個相對較大凹入部分RP形成於半導體裝置DEV1中，故在執行打線接合時，一負載施加至半導體基板SUB，使得半導體基板SUB撓曲，且存在半導體基板SUB破裂的風險。
另一方面，由於相對較小凹入部分以一柵格狀配置形成於半導體裝置DEV2中，故可藉由凹入部分RP之間之第二表面SS支撐在打線接合時施加之負載。因此，根據半導體裝置DEV2，可抑制由在打線接合時施加之負載導致之半導體基板SUB之破裂。
在藉由將寬度W除以節距P所獲取之值係0.1或更大及0.4或更小之一情況中，可保證對抗在打線接合時施加之負載之強度同時減小與凹入部分RP之形成相關聯之接通電阻。
在凹入部分RP經配置於其在平面圖中不與閘極電極EL2重疊之一位置處之一情況中，可抑制由當在閘極電極EL2上執行打線接合時施加之負載導致之半導體基板SUB之破裂。由於閘極電極EL2位於其在平面圖中不與單元區R2重疊之一位置處，故即使凹入部分RP未形成於其在平面圖中與閘極電極EL2重疊之一位置處，接通電阻亦幾乎不增加。
＜第一修改實例＞ 圖23係根據第一修改實例之半導體裝置DEV2之一仰視圖。如圖23中展示，無需以一方形柵格方式配置凹入部分RP。舉例而言，可以一交錯方式配置凹入部分RP。
圖24係根據第二修改實例之半導體裝置DEV2之一仰視圖。圖25係根據第三修改實例之半導體裝置DEV2之一仰視圖。如圖24及圖25中展示，凹入部分RP之一平面形狀無需為一矩形形狀。如圖24中展示，凹入部分RP之平面形狀可為除一矩形形狀以外之一多邊形形狀，且如圖25中展示，凹入部分RP之平面形狀可為一圓形(或橢圓形)形狀。
(第三實施例) 下文中，將描述根據一第三實施例之一半導體裝置(下文中被稱為「半導體裝置DEV3」)。此處，將主要描述不同於半導體裝置DEV1之要點，且將適當地省略冗餘描述。
＜半導體裝置DEV3之組態＞ 圖26係半導體裝置DEV3之一仰視圖。圖27係沿著圖26之一線XXVII-XXVII截取之一橫截面視圖。如圖26及圖27中展示，半導體裝置DEV3具有半導體基板SUB、閘極絕緣膜GI、閘極GA、層間絕緣膜ILD、源極電極EL1、閘極電極EL2及汲極電極EL3。在此方面，半導體裝置DEV3之組態與半導體裝置DEV1之組態係共同的。
半導體裝置DEV3具有形成為凹入部分RP之複數個凹槽TR。在此方面，半導體裝置DEV3之組態不同於半導體裝置DEV1之組態。
在平面圖中，凹槽TR沿一第一方向DR1延伸。複數個凹槽TR經配置以便在一第二方向DR2上彼此隔開。第二方向DR2係正交於第一方向DR1之一方向。凹槽TR之各者較佳地形成於其在平面圖中不與閘極電極EL2重疊之一位置處。
在平面圖中，閘極溝槽GTR之一延伸方向較佳地沿第一方向DR1延伸。即，閘極溝槽GTR之延伸方向較佳地平行於凹槽TR之各者之延伸方向。然而，閘極溝槽GTR之延伸方向可沿第二方向DR2延伸。
＜半導體裝置DEV3之效應＞ 由於複數個凹槽TR形成於半導體裝置DEV3中，故可藉由凹槽TR之間之第二表面SS支撐在打線接合時施加之負載。因此，根據半導體裝置DEV3，可抑制由在打線接合時施加之負載導致之半導體基板SUB之破裂。在凹槽TR之各者之延伸方向沿閘極溝槽GTR之延伸方向延伸之一情況中，可進一步減小接通電阻。
(第四實施例) 下文中，將描述根據一第四實施例之一半導體裝置(下文中被稱為「半導體裝置DEV4」)。此處，將主要描述不同於半導體裝置DEV1之要點，且將適當地省略冗餘描述。
＜半導體裝置DEV4之組態＞ 圖28係半導體裝置DEV4之一橫截面視圖。如圖28中展示，半導體裝置DEV4具有半導體基板SUB、閘極絕緣膜GI、閘極GA、層間絕緣膜ILD、源極電極EL1、閘極電極EL2及汲極電極EL3。在單元區R2中，凹入部分RP形成於第二表面SS中。在此方面，半導體裝置DEV3之組態與半導體裝置DEV1之組態係共同的。
半導體裝置DEV4進一步具有一導體CB。在此方面，半導體裝置DEV4之組態不同於半導體裝置DEV1之組態。導體CB嵌入凹入部分RP中。導體CB係由舉例而言銀粒子之一燒結體形成。然而，導體CB不限於由此燒結體形成。
＜半導體裝置DEV4之效應＞ 由於導體CB嵌入半導體裝置DEV3中之凹入部分RP中，故亦藉由導體CB支撐在打線接合時施加之負載。因此，根據半導體裝置DEV4，可抑制由在打線接合時施加之負載導致之半導體基板SUB之破裂。
(第五實施例) 下文中，將描述根據一第五實施例之一半導體封裝(下文中被稱為「半導體封裝PKG1」)。
＜半導體封裝PKG1之組態＞ 圖29係半導體封裝PKG1之一橫截面視圖。如圖29中展示，半導體封裝PKG1具有半導體裝置DEV1及一引線框LF。引線框LF具有一晶粒襯墊DP。晶粒襯墊DP具有一凸出部分PP。引線框LF係由舉例而言銅、銅合金或類似者形成。
半導體裝置DEV1經配置使得第二表面SS面向引線框LF (晶粒襯墊DP)。因此，將凸出部分PP插入凹入部分RP中。儘管未展示，然汲極電極EL3及引線框LF (晶粒襯墊DP)藉由舉例而言焊料連接。一接合導線BW連接至源極電極EL1及閘極電極EL2之各者。
＜半導體封裝PKG1之效應＞ 在半導體封裝PKG1中，由於亦藉由凸出部分PP支撐在將接合導線BW打線接合至源極電極EL1及閘極電極EL2之各者時施加之負載，故可抑制由在打線接合時施加之負載導致之半導體基板SUB之破裂。
(第六實施例) 下文中，將描述根據一第六實施例之一半導體封裝(下文中被稱為「半導體封裝PKG2」)。
＜半導體封裝PKG2之組態＞ 圖30係半導體封裝PKG2之一橫截面視圖。如圖30中展示，半導體封裝PKG2具有半導體裝置DEV1及引線框LF。引線框LF具有晶粒襯墊DP。將晶粒襯墊DP劃分成一第一部分DP1及一第二部分DP2。
半導體裝置DEV1經配置使得第一表面FS面向引線框LF (晶粒襯墊DP)。源極電極EL1及閘極電極EL2分別連接至第一部分DP1及第二部分DP2。源極電極EL1及第一部分DP1以及閘極電極EL2及第二部分DP2藉由舉例而言焊料(未展示)連接。接合導線BW連接至定位於凹入部分RP之底壁上之汲極電極EL3之一部分。
＜半導體封裝PKG2之效應＞ 在半導體封裝PKG2中，由於未在源極電極EL1及閘極電極EL2上執行打線接合，故可抑制由在打線接合時施加之負載導致之半導體基板SUB之破裂。 在前述內容中，已基於實施例具體描述本發明者之發明。然而，無需多言，本發明不限於前述實施例，且可在本發明之範疇內進行各種修改及更改。 相關申請案之交叉參考
2021年1月22日申請之日本專利申請案第2021-008604號之包含說明書、圖式及摘要之全部揭示內容以引用之方式併入本文中。
BR:本體區 BW:接合導線 CB:導體 CH:通道區 DEV1:半導體裝置 DEV2:半導體裝置 DEV3:半導體裝置 DP:晶粒襯墊 DP1:第一部分 DP2:第二部分 DR1:第一方向 DR2:第二方向 DRA:汲極區 DRI:漂移區 EL1:源極電極 EL2:閘極電極 EL3:汲極電極 EPI:磊晶層 FS:第一表面 GA:閘極 GI:閘極絕緣膜 GTR:閘極溝槽 ILD:層間絕緣膜 LF:引線框 P:節距 PKG1:半導體封裝 PKG2:半導體封裝 PP:凸出部分 PR:柱區 R1:外周邊區 R2:單元區 RP:凹入部分 S1:製備步驟 S2:磊晶生長步驟 S3:第一離子植入步驟 S4:第二離子植入步驟 S5:溝槽形成步驟 S6:閘極絕緣膜形成步驟 S7:閘極形成步驟 S8:層間絕緣膜形成步驟 S9:接觸插塞形成步驟 S10:基板拋光步驟 S11:凹入部分形成步驟 S12:第一電極形成步驟 S13:第二電極形成步驟 S14:單粒化步驟 SR:源極區 SS:第二表面 SUB:半導體基板 T1:厚度 T2:厚度 T3:厚度 TR:凹槽 W:寬度 θ:角度
圖1係一半導體裝置DEV1之一平面圖。 圖2係沿著圖1之一線II-II截取之一橫截面視圖。 圖3係圖2之一區III之一放大圖。 圖4係沿著圖1之一線IV-IV截取之一橫截面視圖。 圖5係半導體裝置DEV1之一製造方法之一流程圖。 圖6係一製備步驟S1中之半導體裝置DEV1之一橫截面視圖。 圖7係一磊晶生長步驟S2中之半導體裝置DEV1之一橫截面視圖。 圖8係一第一離子植入步驟S3中之半導體裝置DEV1之一橫截面視圖。 圖9係一第二離子植入步驟S4中之一半導體裝置DEV2之一橫截面視圖。 圖10係一溝槽形成步驟S5中之半導體裝置DEV1之一橫截面視圖。 圖11係一閘極絕緣膜形成步驟S6中之半導體裝置DEV1之一橫截面視圖。 圖12係一閘極形成步驟S7中之半導體裝置DEV1之一橫截面視圖。 圖13係一層間絕緣膜形成步驟S8中之半導體裝置DEV1之一橫截面視圖。 圖14係一基板拋光步驟S10中之半導體裝置DEV1之一橫截面視圖。 圖15係一凹入部分形成步驟S11中之半導體裝置DEV1之一橫截面視圖。 圖16係一第一電極形成步驟S12中之半導體裝置DEV1之一橫截面視圖。 圖17係一第二電極形成步驟S13中之半導體裝置DEV1之一橫截面視圖。 圖18係根據一第一修改實例之半導體裝置DEV1之一橫截面視圖。 圖19係根據一第二修改實例之半導體裝置DEV1之一橫截面視圖。 圖20係根據一第三修改實例之半導體裝置DEV1之一橫截面視圖。 圖21係半導體裝置DEV2之一仰視圖。 圖22係沿著圖21之一線XXII-XXII截取之一橫截面視圖。 圖23係根據第一修改實例之半導體裝置DEV2之一仰視圖。 圖24係根據第二修改實例之半導體裝置DEV2之一仰視圖。 圖25係根據第三修改實例之半導體裝置DEV2之一仰視圖。 圖26係一半導體裝置DEV3之一仰視圖。 圖27係沿著圖26之一線XXVII-XXVII截取之一橫截面視圖。 圖28係一半導體裝置DEV4之一橫截面視圖。 圖29係一半導體封裝PKG1之一橫截面視圖。 圖30係一半導體封裝PKG2之一橫截面視圖。
EL1:源極電極
EL2:閘極電極
EL3:汲極電極
FS:第一表面
R1:外周邊區
R2:單元區
RP:凹入部分
SS:第二表面
SUB:半導體基板
θ:角度

Claims (15)

  1. 一種半導體裝置，其包括： 一半導體基板，其具有一第一表面及在該第一表面之一相對側上之一第二表面； 一閘極絕緣膜，其形成於該第一表面上； 一閘極，其經由該閘極絕緣膜形成於該第一表面上； 一源極區，其形成於該半導體基板之第一表面側中； 一本體區，其形成以與該源極區接觸且包含一通道區； 一汲極區，其形成於該半導體基板之第二表面側中；及 一漂移區，其形成以與該本體區之第二表面側及該汲極區之第一表面側接觸， 其中該閘極面向該通道區且該閘極絕緣膜插置於其間，且 其中該半導體基板具有形成於該第二表面中且朝向該第一表面凹陷之至少一個凹入部分。
  2. 如請求項1之半導體裝置， 其中該半導體基板係由單晶矽形成，且 其中該第一表面及該第二表面正交於該單晶矽之一＜100＞方向。
  3. 如請求項2之半導體裝置， 其中該至少一個凹入部分之一側壁相對於該第二表面成50度或更大及60度或更小之一角度。
  4. 如請求項2之半導體裝置， 其中該至少一個凹入部分之一側壁係正交於該單晶矽之一＜111＞方向之一表面。
  5. 如請求項1之半導體裝置， 其中該至少一個凹入部分係在平面圖中配置成一柵格狀配置之複數個凹入部分。
  6. 如請求項5之半導體裝置， 其中該複數個凹入部分在平面圖中各具有一多邊形形狀或一圓形形狀。
  7. 如請求項5之半導體裝置，其進一步包括 一閘極電極，其形成於該第一表面上且電連接至該閘極， 其中該複數個凹入部分位於該複數個凹入部分在平面圖中不與該閘極電極重疊之一位置處。
  8. 如請求項5之半導體裝置， 其中藉由將該複數個凹入部分之相對側壁之間之一最小距離除以兩個鄰近凹入部分之間之一節距所獲取之一值係0.1或更大及0.4或更小。
  9. 如請求項1之半導體裝置， 其中該至少一個凹入部分係沿一第一方向延伸且經配置以便在與該第一方向相交之一第二方向上彼此隔開之複數個凹槽。
  10. 如請求項9之半導體裝置， 其中在平面圖中沿該第一方向延伸之一閘極溝槽形成於該第一表面中， 其中從該閘極溝槽之一側壁曝露該通道區，且 其中該閘極形成於該閘極溝槽內部以面向該通道區且該閘極絕緣膜插置於其間。
  11. 如請求項9之半導體裝置，其進一步包括 一閘極電極，其形成於該第一表面上且電連接至該閘極， 其中該複數個凹槽位於該複數個凹槽在平面圖中不與該閘極電極重疊之一位置處。
  12. 如請求項1之半導體裝置，其進一步包括 一導體，其填充於該至少一個凹入部分中。
  13. 如請求項1之半導體裝置， 其中在形成該至少一個凹入部分之一位置處，該汲極區之一厚度小於該漂移區之一厚度。
  14. 一種半導體封裝，其包括： 一引線框；及 如請求項1之半導體裝置，其經配置使得第二表面面向該引線框，且 其中該引線框具有插入至少一個凹入部分中之至少一個凸出部分。
  15. 一種半導體封裝，其包括： 一引線框；及 如請求項1之半導體裝置，其經配置使得第一表面面向引線框側。
TW111100420A 2021-01-22 2022-01-05 半導體裝置及半導體封裝 TW202245189A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021008604A JP2022112707A (ja) 2021-01-22 2021-01-22 半導体装置及び半導体パッケージ
JP2021-008604 2021-01-22

Publications (1)

Publication Number Publication Date
TW202245189A true TW202245189A (zh) 2022-11-16

Family

ID=79686694

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111100420A TW202245189A (zh) 2021-01-22 2022-01-05 半導體裝置及半導體封裝

Country Status (6)

Country Link
US (1) US20220238651A1 (zh)
EP (1) EP4044254A3 (zh)
JP (1) JP2022112707A (zh)
KR (1) KR20220106682A (zh)
CN (1) CN114784105A (zh)
TW (1) TW202245189A (zh)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5998833A (en) 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
JP2002016266A (ja) * 2000-06-28 2002-01-18 Sankosha Corp 半導体素子とその製造方法
JP2007243080A (ja) * 2006-03-13 2007-09-20 Fuji Electric Holdings Co Ltd 半導体装置およびその製造方法
JP2007311771A (ja) * 2006-04-21 2007-11-29 Sanyo Electric Co Ltd 半導体装置及びその製造方法
KR101776926B1 (ko) * 2010-09-07 2017-09-08 삼성전자주식회사 반도체 소자 및 그 제조 방법
US8709893B2 (en) * 2011-08-23 2014-04-29 Alpha & Omega Semiconductor, Inc. Method of making a low-Rdson vertical power MOSFET device
JP2015041638A (ja) * 2013-08-20 2015-03-02 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
JP2020043126A (ja) * 2018-09-06 2020-03-19 住友電気工業株式会社 炭化珪素半導体装置および炭化珪素半導体モジュール

Also Published As

Publication number Publication date
CN114784105A (zh) 2022-07-22
EP4044254A2 (en) 2022-08-17
JP2022112707A (ja) 2022-08-03
KR20220106682A (ko) 2022-07-29
EP4044254A3 (en) 2022-10-26
US20220238651A1 (en) 2022-07-28

Similar Documents

Publication Publication Date Title
US6770539B2 (en) Vertical type MOSFET and manufacturing method thereof
US11145711B2 (en) Capacitor and method for manufacturing capacitor
JP2018129378A (ja) 半導体装置および半導体装置の製造方法、ならびに、半導体ウエハ構造物
US7989884B2 (en) Structure for making a top-side contact to a substrate
EP1289022A2 (en) Power MOSFET transistor and Schottky diode
US11749749B2 (en) Semiconductor device
JP2011054885A (ja) 半導体装置及び半導体装置の製造方法
WO2013168796A1 (ja) 半導体装置および半導体装置の製造方法
US10332967B2 (en) Semiconductor device and method for manufacturing the same
US11646370B2 (en) Semiconductor device with contact plugs
JP2013089778A (ja) 半導体装置及びその製造方法
US20180374950A1 (en) Semiconductor device and method of manufacturing the same
WO2020032206A1 (ja) ＳｉＣ半導体装置
KR102059981B1 (ko) 반도체 디바이스와 그 제조 방법
JP6099302B2 (ja) 半導体装置の製造方法
JP7067698B2 (ja) 半導体装置
TWI664729B (zh) 切換元件及製造切換元件的方法
TW202245189A (zh) 半導體裝置及半導體封裝
JP5239254B2 (ja) 絶縁ゲート型半導体素子の製造方法
KR20190121256A (ko) 반도체 웨이퍼, 반도체 칩 및 반도체 웨이퍼 제조 방법
JP2017028056A (ja) 半導体装置の製造方法
TWI802305B (zh) 半導體結構以及埋入式場板結構的製造方法
JP2020035912A (ja) 半導体装置
JP2871216B2 (ja) 半導体装置の製造方法
WO2023233746A1 (ja) 半導体装置