CN1146040C - 半导体器件的基片及其制造方法、半导体器件 - Google Patents
半导体器件的基片及其制造方法、半导体器件 Download PDFInfo
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Abstract
在基片的半导体芯片安装面的配线和整个端子上镀软质金,在所设置的外部连接端子的背面的配线和整个端子上镀硬质金的情况下,贯通基片的通孔内的配线上产生未镀软质金也未镀硬质金的部分,由于电池作用和腐蚀作用,在该部分上会发生断线。为此,本发明在形成掩膜后进行电镀,以使镀软质金部分和镀质金部分的界限5,形成在半导体芯片安装面上的芯片连接端子2和通孔4之间。
Description
技术领域
本发明涉及例如用于IC卡等中的半导体器件的基片及其制造方法、及半导体器件、卡式组件、信息存储器件。
背景技术
近年来,IC卡等的卡式存储器件正已实用化。对于这类卡式存储器件,可使用下列半导体封装:仅单面的安装半导体芯片的模制树脂,其背面带有平面型的外部连接端子。这种半导体芯片中设置例如非易失性存储器。
图9及图10表示这类半导体封闭的例子。图9表示半导体封装的剖面图,图10(a)是半导体封装的树脂密封面的透视图。图10(b)是半导体封装的外部连接端子面的透视图。基片1是厚度为0.1~0.4mm的例如树脂的基片。半导体芯片6在基片1上用粘接材料9固定,基片1上的芯片连接端子2和半导体芯片6的焊盘用比如金属布线7连接,用树脂8单面密封基片1,覆盖住半导体芯片6。外部连接端子3设置在基片的无树脂密封的面上。此外部连接端子3,利用通过穿透基片1的通孔4的配线与芯片连接端子2电气连接。
图8表示这类半导体封装中所用基片的剖面。以下,对于同一构成元件标以相同的符号,并省略说明。对于此基片1,通常在基片的半导体芯片安装面上的配线2上镀以纯度99.9%以上的软质金。这样,由于连接半导体芯片6的焊盘和基片1上的芯片连接端子的焊接布线7中使用了软质金和铝,若在芯片连接端子上使用软质金,就能够使焊接布线7和芯片连接端子的接合变得可靠。另一方面,在外部连接端子面的配线3上镀以纯度99%的硬质金。这样,使用硬质金电镀方法不容易造成损伤。软质金电镀和硬质金电镀的界限5在通孔4的中间部分。
再有,在图8中为了简略,未分别表示镀金、镀镍、铜箔及镀铜。这些层作为芯片连接端子及外部连接端子集中表示在图8中。
图11表示现有半导体器件的基片制造工艺。
按以下方法进行上述镀金。
首先,把比如厚度为18μm的铜箔24用铝合剂粘在树脂制成的基片1的两面。图11(a)表示该阶段的基片剖面。接着,用钻头在基片上开孔,形成通孔4。图11(b)表示该阶段的基片剖面。其后,在整个基片上镀铜25,向基片的两面及通孔内部提供铜25。结果,利用镀铜,基片的两面电气连接。图11(c)表示该阶段的基片剖面。然后,依次在基片的铜上粘贴比如干膜的光致抗蚀剂、曝光、构图及蚀刻铜,形成铜的配线图型。图11(d)表示该阶段的基片剖面。
通常,利用铜箔和镀铜两个方面形成铜的配线,其理由如下。由于设置可粘贴在基片上的铜箔,使配线的膜厚容易变厚,而镀铜由于电镀本身进行得缓慢,变厚配线的膜厚就不容易。当然,若在没有费时效率方面的问题的情况下,也可以不使用铜箔而仅用镀铜形成配线。
接着,用带或比如光致抗蚀剂类的干膜,遮蔽安装芯片的整个表面之后,连接进行光亮镀镍(图中表示出)和镀硬质金,在外部连接端子表面上的铜图形及通孔4内的铜上镀上硬质金。
接着,把进行过镀硬质金的基片的外部连接端子面的全体用带或干燥膜遮蔽,依次进行无光亮或半光亮镀镍(图中表示)和镀软质金。结果,在芯片安装面上及通孔4内的铜配线上镀上软质金。在镀硬质金和镀软质金期间,先进行镀镍然后镀金,使镍夹在金和铜之间,以防止长时间金向铜的的扩散。
并且,可颠倒电镀顺序,可在芯片安装面上镀软质金,然后在外部连接端子面上镀硬质金。
这种方法中,进行镀软质金或镀硬质金时,由于通过掩膜堵住通孔部4的一侧,通孔4内存积有空气,使电镀液不容易流入通孔4内。因此,使通孔4的中间部分存在未被电镀的情况。
通孔4内无论在镀硬金时还是镀软金时皆产生未镀部分,若暴露出铜或镍基底金属,在通孔部4中会产生电池作用或腐蚀作用,导致配线的断线。
发明内容
针对上述课题,本发明的目的在于使通孔内能进行充分的电镀,从而提高配线的可靠性。
为解决上述课题,半导体器件基片具有如下特征:包括有第1主表面、第2主表面及为贯通第1、第2主表面而设置的通孔的基片;设置于所述基片的第1主表面上的外部连接端子;设置于所述基片的第2主表面上、通过所述通孔与所述外部连接端子电气连接的芯片连接端子;所述外部连接端子,所述通孔内部的全部及所述芯片连接端子的第1区域镀硬质金;所述芯片连接端子的第2区域上镀软质金,所述第1区域与所述第2区域的边界部在所述通孔的所述第2主表面侧的外部与所述芯片连接端子之间。
本发明的半导体器件基片还具有如下特征:包括有第1主表面、第2主表面及为贯通第1、第2主表面而设置的通孔的基片;设置于所述基片的第1主表面上的外部连接端子;设置于所述基片的第2主表面上、通过所述通孔与所述外部连接端子电气连接的芯片连接端子;所述外部连接端子,所述通孔内部的全部及所述芯片连接端子的第1区域镀软质金;所述芯片连接端子的第2区域上镀硬质金,所述第1区域与所述第2区域的边界部在所述通孔的所述第1主表面侧的外部与所述芯片连接端子之间。
本发明有半导体器件的基片的制造方法具有包括下列步骤的特征:在基片的第1,第2主表面上及为贯通所述第1,第2主表面而设置的通孔的内部,利用光刻技术和蚀刻技术形成镀铜配线图形;在所述基片的第1主表面上形成第1掩膜,该掩膜未覆盖所述通孔,但覆盖所述第1主表面上的配线图形;在未被所述第1掩膜覆盖的配线图形上及所述通孔内部的配线图形上依次镀镍和硬质金;除去所述第1掩膜;形成第2掩膜,该掩膜覆盖所述已镀硬质金的配线图形;在未被所述第2掩膜覆盖的配线图形上依次镀镍和软质金;除去第2掩膜。
并且,本发明的半导体器件的基片的制造方法具有包括下列步骤的特征:在基片的第1,第2主表面上及为贯通所述第1,第2主表面而设置的通孔的内部,利用光刻技术和蚀刻技术形成镀铜配线图形;在所述基片的第1主表面上形成第1掩膜,该掩膜未覆盖所述通孔,但覆盖所述第1主表面上的配线图形;在未被所述第1掩膜覆盖的配线图形上及所述通孔内部的配线图形上依次镀镍和软质金;除去所述第1掩膜;形成第2掩膜,该掩膜覆盖所述已镀软质金的配线图形;在未被所述第2掩膜覆盖的配线图形上依次镀镍和硬质金;除去第2掩膜。
并且,本发明的半导体器件的基片的制造方法具有包括下列步骤的特征:在有从基片的第1主表面贯通至第2主表面的通孔的基片上,至少在所述基片的第1主表面的通孔周边,所述基片的第2主表面的通孔周边及所述通孔内部镀硬质金;至少在所述未覆盖硬质金的所述基片的第1主表面上镀软质金。
并且,本发明的半导体器件的基片的制造方法具有包括下列步骤的特征:在有从基片的第1主表面贯通至第2主表面的通孔的基片上,至少在所述基片的第1主表面的通孔周边,所述基片的第2主表面的通孔周边及所述通孔内部镀软质金;至少在所述未覆盖硬质金的所述基片的第1主表面上镀硬质金。
并且,半导体器件具有下列特征,即包括:有第1主表面、第2主表面及为贯通第1、第2主表面而设置的通孔的基片;设置于所述基片的第1主表面上的外部连接端子;设置于所述基片的第2主表面上、通过所述通孔与所述外部连接端子电气连接的芯片连接端子;设置于所述基片的第2主表面上、与所述芯片连接端子电气连接的半导体芯片;用于覆盖所述基片的第2主表面的一部分的树脂密封部;所述外部连接端子,所述通孔内部的全部及所述芯片连接端子的第1区域镀硬质金;所述芯片连接端子的第2区域上镀软质金,所述第1区域与所述第2区域的边界部在所述通孔的所述第2主表面侧的外部与所述芯片连接端子之间。
并且,半导体器件具有下列特征,即包括:有第1主表面、第2主表面及为贯通第1、第2主表面而设置的通孔的基片;设置于所述基片的第1主表面上的外部连接端子;设置于所述基片的第2主表面上、通过所述通孔与所述外部连接端子电气连接的芯片连接端子;设置于所述基片的第2主表面上、与所述芯片连接端子电气连接的半导体芯片;用于覆盖所述基片的第2主表面的一部分的树脂密封部;所述外部连接端子,所述通孔内部的全部及所述芯片连接端子的第1区域镀软质金;所述芯片连接端子的第2区域上镀硬质金,所述第1区域与所述第2区域的边界部在所述通孔的所述第1主表面侧的外部与所述芯片连接端子之间。
还有,卡式组件具有下列特征,即包括:有凹部的卡式支承体;有第1主表面、第2主表面及为贯通第1、第2主表面而设置的通孔的基片;设置于所述基片的第1主表面上的外部连接端子;设置于所述基片的第2主表面上、通过所述通孔与所述外部连接端子电气连接的芯片连接端子;设置于所述基片的第2主表面上、与所述芯片连接端子电气连接的半导体芯片;用于覆盖所述基片的第2主表面的一部分的树脂密封部;所述外部连接端子,所述通孔内部的全部及所述芯片连接端子的第1区域镀硬质金;所述芯片连接端子的第2区域上镀软质金,所述第1区域与所述第2区域的边界部在所述通孔的所述第2主表面侧的外部与所述芯片连接端子之间;在所述卡式支承体的凹部埋入所述基片的所述树脂密封部侧,进行安装。
并且,卡式组件具有下列特征,即包括:有凹部的卡式支承体;有第1主表面、第2主表面及为贯通第1、第2主表面而设置的通孔的基片;设置于所述基片的第1主表面上的外部连接端子;设置于所述基片的第2主表面上、通过所述通孔与所述外部连接端子电气连接的芯片连接端子;设置于所述基片的第2主表面上、与所述芯片连接端子电气连接的半导体芯片;用于覆盖所述基片的第2主表面的一部分的树脂密封部;所述外部连接端子,所述通孔内部的全部及所述芯片连接端子的第1区域镀软质金,所述第1区域与所述第2区域的边界部在所述通孔的所述第1主表面侧的外部与所述芯片连接端子之间;所述芯片连接端子的第2区域上镀硬质金;在支承体的凹部埋入所述基片的所述树脂密封部侧,进行安装。
还有,信息存储器件具有下列特征,即包括下列主要部分:卡式组件,它包括:
有凹部的卡式支承体;
有第1主表面、第2主表面及为贯通第1、第2主表面而设置的通孔的基片;
设置于所述基片的第1主表面上的外部连接端子;
设置于所述基片的第2主表面上、通过所述通孔与所述外部连接端子电气连接的芯片连接端子;
设置于所述基片的第2主表面上、与所述芯片连接端子电气连接的半导体芯片;
至少覆盖所述基片的第2主表面的一部分的树脂密封部;
所述外部连接端子,所述通孔内部的全部及所述芯片连接端子的第1区域镀硬质金;
所述芯片连接端子的第2区域上镀软质金;
在所述卡式支承体的凹部埋入所述基片的所述树脂密封部;
与卡式组件的外部连接端子连接的第一连接器,与器械连接的第二连接器;与所述第一连接器、第二连接器连接的接口电路。
并且,信息存储器件具有下列特征,即包括下列主要部分:卡式组件,它包括:
有凹部的卡式支承体;
有第1主表面、第2主表面及为贯通第1、第2主表面而设置的通孔的基片;
设置于所述基片的第1主表面上的外部连接端子;
设置于所述基片的第2主表面上、通过所述通孔与所述外部连接端子电气连接的芯片连接端子;
设置于所述基片的第2主表面上、与所述芯片连接端子电气连接的半导体芯片;
至少覆盖所述基片的第2主表面的一部分的树脂密封部;
所述外部连接端子,所述通孔内部及所述芯片连接端子的第1区域镀软质金;
所述芯片连接端子的第2区域上镀硬质金;
在所述卡式支承体的凹部埋入所述基片的所述树脂密封部;与卡式组件的外部连接端子连接的第一连接器,与器械连接的第二连接器;与所述第一连接器、第二连接器连接的接口电路,所述第1区域与所述第2区域的边界部在所述通孔的所述第1主表面侧的外部与所述芯片连接端子之间。
附图说明
图1是本发明的基片的剖面图。
图2是本发明的半导体器件的剖面图。
图3是本发明的半导体器件的剖面图。
图4表示本发明图的半导体器件基片的俯视图。
图5是本发明卡式组件的透视图。
图6是本发明基片的制造工艺示意图。
图7是本发明卡的透视图。
图8是现有技术的基片剖面图。
图9是现有技术的半导体器件的剖面图。
图10是现有技术的半导体器件的透视图。
图11是现有技术的基片制造工艺示意图。
具体实施方式
图1表示本发明的半导体器件基片。而且,图6表示本发明的半导体器件基片的制造工艺。
首先,把比如厚度为18μm的铜箔24用粘接剂贴在树脂制成的基片1的两侧,图6(a)表示此阶段的基片剖面。接着,用钻头在基片上打孔,形成通孔4,图6(b)表示该阶段的基片剖面。之后,对整个基板镀铜。镀铜的膜厚比如为10~15μm。图6(c)表示该阶段的基片剖面。其结果,通孔4内部和基片1的两面的镀铜25,使基片两面电连接。然后,在基片的铜25上依次进行:粘贴比如光致抗蚀剂、曝光、构图及蚀刻铜,形成铜的配线图形。图6(d)表示该阶段的基片剖面。
接着,对基片的芯片安装面上的配线的一部分作掩膜。此时,遮蔽了芯片连接端子,但未遮蔽通孔4。并且,掩膜是在基片上粘贴按预定形状加工好的带,或是在整个芯片安装面上涂敷干膜,利用金属版印刷技术构图形成的。之后,依次光亮镀镍(图中标出)和镀硬质金,构成配线图形上的硬质金3。图6(e)表示该阶段的基片剖面。此时,由于通孔部4的上下孔都不会被掩膜而堵住,所以电镀液容易流入通孔部4中。结果,使通孔4内的整个铜上和芯片安装面中未遮蔽的配线图形部分及整个外部连接端子面的配线上镀上硬质金。
接着,除去所述掩膜后,对已镀硬质金3的部分按前述方法作掩膜。之后,依次光亮镀镍(图中表示)和镀软质金,在未覆盖掩膜的部分镀上软质金2。其后,除去此掩膜。结果,半导体芯片的安装面上的芯片连接端子和其周围部分的配线上镀上了软质金2。图6(f)表示该阶段的基片剖面。
这样,本实施例中,整个通孔4内的铜上镀有硬质金,镀软质金和镀硬质金的交界部5在通孔4的外部,即在通孔4和芯片连接端子之间。还有,图1中,为简化起见,仅表示了基片上已镀软质金的配线和芯片连接端子及已镀硬质金的配线和外部连接端子。后面的图2及图3也是如此。
可以颠倒上述电镀顺序,也就是芯片安装面的芯片连接端子及其周围镀软质金,之后,在未镀软质金的芯片安装面部分和通孔及外部连接端子面上镀硬质金。
4表示本发明图的半导体器件基片的俯视图。配线12从芯片连接端子11延伸,穿过通孔4与设置在背面的外部连接端子连接。13表示半导体芯片的设置面,14表示树脂密封界限。再有,15表示在基片1上设置半导体芯片,并在树脂密封后其半导体组件切取的切线,还有,16表示镀软质金和镀硬质金的界限,界限16的内侧配线镀软质金,界限16的外侧配线镀硬质金。
图2表示本发明的半导体封装。在图1所示的本发明基片上,使用粘接剂9粘接半导体芯片6,半导体芯片6的焊盘与基片1的芯片连接端子比如用金属布线7连接,用树脂8仅密封半导体芯片安装面。其结果,形成半导体封装。这里,树脂材料比如用环氧树脂,半导体芯片使用非易失生半导体存储器,例如使用NAND型瞬时E2PROM。再有,不使用金属线7,使用图3所示的凸块10,利用倒装法连接半导体芯片和基片的芯片连接端子也可以。
图2和图3中所示的半导体封装,用比如图5所示的那种卡式组件。卡式组件中所用的卡底座18由树脂形成,比如长、宽及厚度为37mm×45mm×0.76mm,并设有凹部18a。为使半导体封装17的外部连接端子3的表面和卡底座18的表面大致为一面,向卡底座18的凹部18a中埋设已粘接的半导体封装17的树脂密封面。
图5所示的卡式组件使用在IC存储卡等中。图7表示在专用的PCMCIA等卡槽中安装这种卡式组件的接合组件。该接合组件20有卡式的外形,该接合组件20有安装卡式组件19的插入口20a,配有专用的PCMCIA卡槽中可安装标准的连接器23。接合组件20的内部,设有与卡式组件19的外部连接端子3接触的连接器22,和具有在卡式组件与专用器械间的连接功能的接口电路21。
此外,图中虽未示出,但插座最好不要为装在PCMCIA卡槽上的这种卡,并最好在电脑(バソコン)或暗箱等本体上配置与卡式组件的外部连接端子3接触的连接器22及接口电路21等。
再有,在接合组件20的内部,最好设置根据电信号能控制卡式组件的驱动电路等。
还有,对于上述说明,除树脂制成的基片外,也可用(タブテ-プ)制成的基片。
并且,上述说明中,通孔内部,基片的表面及通孔周围部分镀硬质金,但可不受此限制,镀软质金也可以。
如上所述,本发明的基片中,由于在基片选择电镀时未堵住通孔部,电镀液容易流进通孔,能可靠地电镀通孔的表面,并且电镀的界限不在通孔部。其结果,在通孔部不产生电池作用和腐蚀作用,提高了通孔的可靠性。
Claims (26)
1.半导体器件的基片,包括:
有第1主表面、第2主表面及为贯通第1、第2主表面而设置的通孔的基片;
设置于所述基片的第1主表面上的外部连接端子;
设置于所述基片的第2主表面上、通过所述通孔与所述外部连接端子电气连接的芯片连接端子;
其特征在于:所述外部连接端子、所述通孔内部的全部及所述芯片连接端子的第1区域镀硬质金;
所述芯片连接端子的第2区域上镀软质金,
所述第1区域与所述第2区域的边界部在所述通孔的所述第2主表面侧的外部与所述芯片连接端子之间。
2.如权利要求1所述的半导体器件基片,其特征在于:所述外部连接端子有平坦的区域。
3.如权利要求1所述的半导体器件基片,其特征在于:所述芯片连接端子有平坦的区域。
4.如权利要求1所述的半导体器件基片,其特征在于:所述芯片连接端子配置在所述基片的周边。
5.半导体器件基片,包括:
有第1主表面、第2主表面及为贯通第1、第2主表面而设置的通孔的基片;
设置于所述基片的第1主表面上的外部连接端子;
设置于所述基片的第2主表面上、通过所述通孔与所述外部连接端子电气连接的芯片连接端子;
其特征在于:所述外部连接端子,所述通孔内部的全部及所述芯片连接端子的第1区域镀软质金;
所述芯片连接端子的第2区域上镀硬质金,
所述第1区域与所述第2区域的边界部在所述通孔的所述第1主表面侧的外部与所述芯片连接端子之间。
6如权利要求5所述的半导体器件基片,其特征在于:所述外部连接端子有平坦的区域。
7如权利要求5所述的半导体器件基片,其特征在于:所述芯片连接端子有平坦的区域。
8如权利要求5所述的半导体器件基片,其特征在于:所述芯片连接端子配置在所述基片的周边。
9半导体器件的基片的制造方法,其特征在于包括下列步骤:
在基片的第1,第2主表面上及为贯通所述第1,第2主表面而设置的通孔的内部,利用光刻技术和蚀刻技术形成镀铜配线图形;
在所述基片的第1主表面上形成第1掩膜,该掩膜未覆盖所述通孔,但覆盖所述第1主表面上的配线图形;
在未被所述第1掩膜覆盖的配线图形上及所述通孔内部的配线图形上依次镀镍和硬质金;
除去所述第1掩膜;
形成第2掩膜,该掩膜覆盖所述已镀硬质金的配线图形;
在未被所述第2掩膜覆盖的配线图形上依次镀镍和软质金;
除去第2掩膜。
10.如权利要求9所述的半导体器件基片的制造方法,其特征在于:被所述硬质金覆盖的配线图形有作为外部连接端子的功能。
11半导体器件的基片的制造方法,其特征在于包括下列步骤:
在基片的第1,第2主表面上及为贯通所述第1,第2主表面而设置的通孔的内部,利用光刻技术和蚀刻技术形成镀铜配线图形;
在所述基片的第1主表面上形成第1掩膜,该掩膜未覆盖所述通孔,但覆盖所述第1主表面上的配线图形;
在未被所述第1掩膜覆盖的配线图形上及所述通孔内部的配线图形上依次镀镍和软质金;
除去所述第1掩膜;
形成第2掩膜,该掩膜覆盖所述已镀软质金的配线图形;
在未被所述第2掩膜覆盖的配线图形上依次镀镍和硬质金;
除去第2掩膜。
12.如权利要求11所述的半导体器件基片的制造方法,其特征在于:被所述硬质金覆盖的配线图形有作为外部连接端子的功能。
13.半导体器件的基片的制造方法,其特征在于包括下列步骤:在有从基片的第1主表面贯通至第2主表面的通孔的基片上,至少在所述基片的第1主表面的通孔周边,所述基片的第2主表面的通孔周边及所述通孔内部镀硬质金;至少在所述未覆盖硬质金的所述基片的第1主表面上镀软质金。
14.如权利要求13所述的半导体器件基片的制造方法,其特征在于:被所述硬质金覆盖的配线图形有作为外部连接端子的功能。
15.半导体器件的基片的制造方法,其特征在于包括下列步骤:在有从基片的第1主表面贯通至第2主表面的通孔的基片上,至少在所述基片的第1主表面的通孔周边,所述基片的第2主表面的通孔周边及所述通孔内部镀软质金;至少在所述未覆盖硬质金的所述基片的第1主表面上镀硬质金。
16.如权利要求15所述的半导体器件基片的制造方法,其特征在于:被所述硬质金覆盖的配线图形有作为外部连接端子的功能。
17半导体器件,包括:
有第1主表面、第2主表面及为贯通第1、第2主表面而设置的通孔的基片;
设置于所述基片的第1主表面上的外部连接端子;
设置于所述基片的第2主表面上、通过所述通孔与所述外部连接端子电气连接的芯片连接端子;
设置于所述基片的第2主表面上、与所述芯片连接端子电气连接的半导体芯片;
用于覆盖所述基片的第2主表面的一部分的树脂密封部;
其特征在于:所述外部连接端子,所述通孔内部的全部及所述芯片连接端子的第1区域镀硬质金;
所述芯片连接端子的第2区域上镀软质金,
所述第1区域与所述第2区域的边界部在所述通孔的所述第2主表面侧的外部与所述芯片连接端子之间。
18如权利要求17所述的半导体器件,其特征在于:所述芯片连接端子与所述半导体芯片通过金属线连接。
19如权利要求17所述的半导体器件,其特征在于:所述芯片连接端子与所述半导体芯片通过倒装法连接。
20半导体器件,包括:
有第1主表面、第2主表面及为贯通第1、第2主表面而设置的通孔的基片;
设置于所述基片的第1主表面上的外部连接端子;
设置于所述基片的第2主表面上、通过所述通孔与所述外部连接端子电气连接的芯片连接端子;
设置于所述基片的第2主表面上、与所述芯片连接端子电气连接的半导体芯片;
用于覆盖所述基片的第2主表面的一部分的树脂密封部;
其特征在于:所述外部连接端子,所述通孔内部的全部及所述芯片连接端子的第1区域镀软质金;
所述芯片连接端子的第2区域上镀硬质金,
所述第1区域与所述第2区域的边界部在所述通孔的所述第1主表面侧的外部与所述芯片连接端子之间。
21如权利要求20所述的半导体器件,其特征在于:所述芯片连接端子与所述半导体芯片通过金属线连接。
22如权利要求20所述的半导体器件,所述芯片连接端子与所述半导体芯片通过倒装法连接。
23卡式组件,其特征在于包括:
有凹部的卡式支承体;
有第1主表面、第2主表面及为贯通第1、第2主表面而设置的通孔的基片;
设置于所述基片的第1主表面上的外部连接端子;
设置于所述基片的第2主表面上、通过所述通孔与所述外部连接端子电气连接的芯片连接端子;
设置于所述基片的第2主表面上、与所述芯片连接端子电气连接的半导体芯片;
用于覆盖所述基片的第2主表面的一部分的树脂密封部;
所述外部连接端子,所述通孔内部的全部及所述芯片连接端子的第1区域镀硬质金;
所述芯片连接端子的第2区域上镀软质金;
在所述卡式支承体的凹部埋入所述基片的所述树脂密封部侧,进行安装,
所述第1区域与所述第2区域的边界部在所述通孔的所述第2主表面侧的外部与所述芯片连接端子之间。
24卡式组件,其特征在于包括:
有凹部的卡式支承体;
有第1主表面、第2主表面及为贯通第1、第2主表面而设置的通孔的基片;
设置于所述基片的第1主表面上的外部连接端子;
设置于所述基片的第2主表面上、通过所述通孔与所述外部连接端子电气连接的芯片连接端子;
设置于所述基片的第2主表面上、与所述芯片连接端子电气连接的半导体芯片;
用于覆盖所述基片的第2主表面的一部分的树脂密封部;
所述外部连接端子,所述通孔内部的全部及所述芯片连接端子的第1区域镀软质金;
所述芯片连接端子的第2区域上镀硬质金;
在支承体的凹部埋入所述基片的所述树脂密封部侧,进行安装。
25信息存储器件,其特征在于包括下列主要部分:
卡式组件,它包括:
有凹部的卡式支承体;
有第1主表面、第2主表面及为贯通第1、第2主表面而设置的通孔的基片;
设置于所述基片的第1主表面上的外部连接端子;
设置于所述基片的第2主表面上、通过所述通孔与所述外部连接端子电气连接的芯片连接端子;
设置于所述基片的第2主表面上、与所述芯片连接端子电气连接的半导体芯片;
用于覆盖所述基片的第2主表面的一部分的树脂密封部;
所述外部连接端子,所述通孔内部的全部及所述芯片连接端子的第1区域镀硬质金;
所述芯片连接端子的第2区域上镀软质金;
在所述卡式支承体的凹部埋入所述基片的所述树脂密封部;与卡式组件的外部连接端子连接的第一连接器,与器械连接的第二连接器;与所述第一连接器、第二连接器连接的接口电路。
26信息存储器件,其特征在于包括下列主要部分:卡式组件,它包括:
有凹部的卡式支承体;
有第1主表面、第2主表面及为贯通第1、第2主表面而设置的通孔的基片;
设置于所述基片的第1主表面上的外部连接端子;
设置于所述基片的第2主表面上、通过所述通孔与所述外部连接端子电气连接的芯片连接端子;
设置于所述基片的第2主表面上、与所述芯片连接端子电气连接的半导体芯片;
用于覆盖所述基片的第2主表面的一部分的树脂密封部;
所述外部连接端子,所述通孔内部的全部及所述芯片连接端子的第1区域镀软质金;
所述芯片连接端子的第2区域上镀硬质金;
在所述卡式支承体的凹部埋入所述基片的所述树脂密封部;
与卡式组件的外部连接端子连接的第一连接器,与器械连接的第二连接器;
与所述第一连接器、第二连接器连接的接口电路,
所述第1区域与所述第2区域的边界部在所述通孔的所述第1主表面侧的外部与所述芯片连接端子之间。
Applications Claiming Priority (3)
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---|---|---|---|
JP138344/1996 | 1996-05-31 | ||
JP13834496 | 1996-05-31 | ||
JP138344/96 | 1996-05-31 |
Publications (2)
Publication Number | Publication Date |
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Family
ID=15219733
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB971149046A Expired - Fee Related CN1146040C (zh) | 1996-05-31 | 1997-05-30 | 半导体器件的基片及其制造方法、半导体器件 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6091137A (zh) |
EP (1) | EP0810656B1 (zh) |
KR (1) | KR100280170B1 (zh) |
CN (1) | CN1146040C (zh) |
DE (1) | DE69731028T2 (zh) |
TW (1) | TW332334B (zh) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5952716A (en) * | 1997-04-16 | 1999-09-14 | International Business Machines Corporation | Pin attach structure for an electronic package |
SE512710C2 (sv) * | 1998-07-08 | 2000-05-02 | Ericsson Telefon Ab L M | Kapsel för högeffekttransistorchip för höga frekvenser innefattande en elektriskt och termiskt ledande fläns |
KR100420879B1 (ko) | 1999-02-18 | 2004-03-02 | 세이코 엡슨 가부시키가이샤 | 반도체 장치, 실장기판 및 그 제조방법, 회로기판 및전자기기 |
US6599147B1 (en) | 1999-05-11 | 2003-07-29 | Socket Communications, Inc. | High-density removable expansion module having I/O and second-level-removable expansion memory |
US6353870B1 (en) * | 1999-05-11 | 2002-03-05 | Socket Communications Inc. | Closed case removable expansion card having interconnect and adapter circuitry for both I/O and removable memory |
TW535465B (en) * | 2000-05-15 | 2003-06-01 | Hitachi Aic Inc | Electronic component device and method of manufacturing the same |
JP2002092575A (ja) * | 2000-09-19 | 2002-03-29 | Mitsubishi Electric Corp | 小型カードとその製造方法 |
US6774486B2 (en) * | 2001-10-10 | 2004-08-10 | Micron Technology, Inc. | Circuit boards containing vias and methods for producing same |
AU2003220678A1 (en) | 2002-04-08 | 2003-10-27 | Socket Communications, Inc | Wireless enabled memory module |
TWI234210B (en) * | 2002-12-03 | 2005-06-11 | Sanyo Electric Co | Semiconductor module and manufacturing method thereof as well as wiring member of thin sheet |
KR100499003B1 (ko) * | 2002-12-12 | 2005-07-01 | 삼성전기주식회사 | 도금 인입선을 사용하지 않는 패키지 기판 및 그 제조 방법 |
TWI228804B (en) * | 2003-07-02 | 2005-03-01 | Lite On Semiconductor Corp | Chip package substrate having flexible printed circuit board and method for fabricating the same |
US7240144B2 (en) * | 2004-04-02 | 2007-07-03 | Arm Limited | Arbitration of data transfer requests |
JP4361826B2 (ja) * | 2004-04-20 | 2009-11-11 | 新光電気工業株式会社 | 半導体装置 |
KR100723493B1 (ko) * | 2005-07-18 | 2007-06-04 | 삼성전자주식회사 | 와이어 본딩 및 플립 칩 본딩이 가능한 스마트 카드 모듈기판 및 이를 포함하는 스마트 카드 모듈 |
US20080237842A1 (en) * | 2007-03-29 | 2008-10-02 | Manepalli Rahul N | Thermally conductive molding compounds for heat dissipation in semiconductor packages |
JP2009206429A (ja) * | 2008-02-29 | 2009-09-10 | Toshiba Corp | 記憶媒体 |
US8084348B2 (en) * | 2008-06-04 | 2011-12-27 | Oracle America, Inc. | Contact pads for silicon chip packages |
KR20100033012A (ko) | 2008-09-19 | 2010-03-29 | 주식회사 하이닉스반도체 | 반도체 패키지 및 이를 갖는 적층 반도체 패키지 |
USD795261S1 (en) * | 2009-01-07 | 2017-08-22 | Samsung Electronics Co., Ltd. | Memory device |
USD794644S1 (en) * | 2009-01-07 | 2017-08-15 | Samsung Electronics Co., Ltd. | Memory device |
USD794034S1 (en) * | 2009-01-07 | 2017-08-08 | Samsung Electronics Co., Ltd. | Memory device |
USD794643S1 (en) * | 2009-01-07 | 2017-08-15 | Samsung Electronics Co., Ltd. | Memory device |
USD794642S1 (en) * | 2009-01-07 | 2017-08-15 | Samsung Electronics Co., Ltd. | Memory device |
USD794641S1 (en) * | 2009-01-07 | 2017-08-15 | Samsung Electronics Co., Ltd. | Memory device |
USD795262S1 (en) * | 2009-01-07 | 2017-08-22 | Samsung Electronics Co., Ltd. | Memory device |
US8407888B2 (en) | 2010-05-07 | 2013-04-02 | Oracle International Corporation | Method of assembling a circuit board assembly |
CN102339404B (zh) * | 2010-07-20 | 2016-06-15 | 上海仪电智能电子有限公司 | 一种新型智能卡模块及其生产工艺 |
TWI408837B (zh) * | 2011-02-08 | 2013-09-11 | Subtron Technology Co Ltd | 封裝載板及其製作方法 |
CN103237416B (zh) * | 2013-05-08 | 2015-10-07 | 无锡江南计算技术研究所 | 同一表面实现电镀硬金和电镀软金的图形制作方法 |
Family Cites Families (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3663376A (en) * | 1971-03-17 | 1972-05-16 | Gary Uchytil | Selective spot plating of lead frame sheets |
FR2439478A1 (fr) * | 1978-10-19 | 1980-05-16 | Cii Honeywell Bull | Boitier plat pour dispositifs a circuits integres |
JPS5990938A (ja) * | 1982-11-17 | 1984-05-25 | Nec Corp | 半導体装置用プリント回路基板 |
US4703420A (en) * | 1985-02-28 | 1987-10-27 | International Business Machines Corporation | System for arbitrating use of I/O bus by co-processor and higher priority I/O units in which co-processor automatically request bus access in anticipation of need |
DE3531318A1 (de) * | 1985-09-02 | 1987-03-05 | Allied Corp | Kontaktiereinrichtung fuer eine chip-karte |
US4882702A (en) * | 1986-03-31 | 1989-11-21 | Allen-Bradley Company, Inc. | Programmable controller with I/O expansion module located in one of I/O module positions for communication with outside I/O modules |
US4837628A (en) * | 1986-07-14 | 1989-06-06 | Kabushiki Kaisha Toshiba | Electronic still camera for recording still picture on memory card with mode selecting shutter release |
US4980856A (en) * | 1986-10-20 | 1990-12-25 | Brother Kogyo Kabushiki Kaisha | IC memory cartridge and a method for providing external IC memory cartridges to an electronic device extending end-to-end |
JPS6478397A (en) * | 1987-09-18 | 1989-03-23 | Mitsubishi Electric Corp | Ic card writing system |
FR2624635B1 (fr) * | 1987-12-14 | 1991-05-10 | Sgs Thomson Microelectronics | Support de composant electronique pour carte memoire et produit ainsi obtenu |
US5018017A (en) * | 1987-12-25 | 1991-05-21 | Kabushiki Kaisha Toshiba | Electronic still camera and image recording method thereof |
JPH0795577B2 (ja) * | 1988-04-12 | 1995-10-11 | 富士プラント工業株式会社 | リードフレームへの部分メッキ方法 |
JP2565387B2 (ja) * | 1988-10-28 | 1996-12-18 | イビデン株式会社 | Icカード用プリント配線板とその製造方法 |
JPH02111861U (zh) * | 1989-02-27 | 1990-09-06 | ||
US5184282A (en) * | 1989-02-27 | 1993-02-02 | Mips Co., Ltd. | IC card adapter |
US5535328A (en) * | 1989-04-13 | 1996-07-09 | Sandisk Corporation | Non-volatile memory system card with flash erasable sectors of EEprom cells including a mechanism for substituting defective cells |
US5172338B1 (en) * | 1989-04-13 | 1997-07-08 | Sandisk Corp | Multi-state eeprom read and write circuits and techniques |
EP0618535B1 (en) * | 1989-04-13 | 1999-08-25 | SanDisk Corporation | EEPROM card with defective cell substitution and cache memory |
US5457590A (en) * | 1989-12-12 | 1995-10-10 | Smartdiskette Gmbh | Insertable element for a disk station of EDP equipment with connections to external components |
US5153818A (en) * | 1990-04-20 | 1992-10-06 | Rohm Co., Ltd. | Ic memory card with an anisotropic conductive rubber interconnector |
JPH0416396A (ja) * | 1990-05-10 | 1992-01-21 | Mitsubishi Electric Corp | 半導体装置カード |
JP2560895B2 (ja) * | 1990-07-25 | 1996-12-04 | 三菱電機株式会社 | Icカードの製造方法およびicカード |
US5293236A (en) * | 1991-01-11 | 1994-03-08 | Fuji Photo Film Co., Ltd. | Electronic still camera including an EEPROM memory card and having a continuous shoot mode |
US5663901A (en) * | 1991-04-11 | 1997-09-02 | Sandisk Corporation | Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems |
DE4121023C2 (de) * | 1991-06-26 | 1994-06-01 | Smartdiskette Gmbh | In eine EDV-Einrichtung einsteckbares Element |
US5430859A (en) * | 1991-07-26 | 1995-07-04 | Sundisk Corporation | Solid state memory system including plural memory chips and a serialized bus |
US5299089A (en) * | 1991-10-28 | 1994-03-29 | E. I. Dupont De Nemours & Co. | Connector device having two storage decks and three contact arrays for one hard disk drive package or two memory cards |
FR2686172B1 (fr) * | 1992-01-14 | 1996-09-06 | Gemplus Card Int | Carte enfichable pour microordinateur formant lecteur de carte a contacts affleurants. |
JPH06105271A (ja) * | 1992-09-16 | 1994-04-15 | Asahi Optical Co Ltd | Icメモリカードカメラシステム |
US5343319A (en) * | 1993-06-14 | 1994-08-30 | Motorola, Inc. | Apparatus for adapting an electrical communications port to an optical communications port |
JPH07507412A (ja) * | 1992-11-12 | 1995-08-10 | ニュー・メディア・コーポレーション | コンピュータと周辺装置との間の再構成可能インターフェイス |
US5475441A (en) * | 1992-12-10 | 1995-12-12 | Eastman Kodak Company | Electronic camera with memory card interface to a computer |
US5469399A (en) * | 1993-03-16 | 1995-11-21 | Kabushiki Kaisha Toshiba | Semiconductor memory, memory card, and method of driving power supply for EEPROM |
US5488433A (en) * | 1993-04-21 | 1996-01-30 | Kinya Washino | Dual compression format digital video production system |
JPH0737049A (ja) * | 1993-07-23 | 1995-02-07 | Toshiba Corp | 外部記憶装置 |
US5887145A (en) * | 1993-09-01 | 1999-03-23 | Sandisk Corporation | Removable mother/daughter peripheral card |
JPH07321155A (ja) * | 1994-05-25 | 1995-12-08 | Hitachi Cable Ltd | Tabテープキャリアの製造方法 |
KR0144818B1 (ko) * | 1994-07-25 | 1998-08-17 | 김광호 | 낸드형 플래쉬메모리 아이씨카드 |
FR2723257B1 (fr) * | 1994-07-26 | 1997-01-24 | Sgs Thomson Microelectronics | Boitier bga de circuit integre |
US5611057A (en) * | 1994-10-06 | 1997-03-11 | Dell Usa, L.P. | Computer system modular add-in daughter card for an adapter card which also functions as an independent add-in card |
US5508971A (en) * | 1994-10-17 | 1996-04-16 | Sandisk Corporation | Programmable power generation circuit for flash EEPROM memory systems |
JPH08139456A (ja) * | 1994-11-10 | 1996-05-31 | Hitachi Chem Co Ltd | 半導体搭載用多層配線板の製造法 |
KR0152042B1 (ko) * | 1995-04-15 | 1998-10-15 | 김광호 | 낸드형 플래쉬메모리 아이씨카드 기록장치 |
JPH08319456A (ja) * | 1995-04-28 | 1996-12-03 | E I Du Pont De Nemours & Co | 印刷回路用の水系処理可能な軟質の光画像化可能耐久被覆材 |
US5596532A (en) * | 1995-10-18 | 1997-01-21 | Sandisk Corporation | Flash EEPROM self-adaptive voltage generation circuit operative within a continuous voltage source range |
-
1997
- 1997-05-28 TW TW086107247A patent/TW332334B/zh not_active IP Right Cessation
- 1997-05-29 US US08/864,958 patent/US6091137A/en not_active Expired - Lifetime
- 1997-05-30 KR KR1019970021875A patent/KR100280170B1/ko not_active IP Right Cessation
- 1997-05-30 CN CNB971149046A patent/CN1146040C/zh not_active Expired - Fee Related
- 1997-06-02 DE DE69731028T patent/DE69731028T2/de not_active Expired - Lifetime
- 1997-06-02 EP EP97108766A patent/EP0810656B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
CN1170960A (zh) | 1998-01-21 |
KR970077542A (ko) | 1997-12-12 |
US6091137A (en) | 2000-07-18 |
EP0810656A2 (en) | 1997-12-03 |
DE69731028T2 (de) | 2005-10-06 |
DE69731028D1 (de) | 2004-11-11 |
EP0810656A3 (en) | 1998-08-26 |
KR100280170B1 (ko) | 2001-02-01 |
TW332334B (en) | 1998-05-21 |
EP0810656B1 (en) | 2004-10-06 |
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