CN1139994C - 半导体图象传感器的结构及其制造方法 - Google Patents

半导体图象传感器的结构及其制造方法 Download PDF

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CN1139994C
CN1139994C CNB98123996XA CN98123996A CN1139994C CN 1139994 C CN1139994 C CN 1139994C CN B98123996X A CNB98123996X A CN B98123996XA CN 98123996 A CN98123996 A CN 98123996A CN 1139994 C CN1139994 C CN 1139994C
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CN1219772A (zh
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���︣�¡�I������
克里福德·I·朱雷
M
罗伯特·M·贵达西
S�����ɭ
马克·S·思文森
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Eastman Kodak Co
Motorola Solutions Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/84—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of applied mechanical force, e.g. of pressure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14645—Colour imagers

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Electromagnetism (AREA)
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  • Ceramic Engineering (AREA)
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Abstract

一种图象传感器(10)，具有图象敏感元件，该元件包括N型导电区(26)和P型嵌入层(37)。这两个区构成两个深度不同的P-N结，提高了不同光频下电荷载流子收集的效率。导电区(26)是通过有角度的注入形成的，这样可以保证导电区(26)的一部分可以用作MOS晶体管(32)的源。

Description

半导体图象传感器的结构及其制造方法
本发明一般涉及半导体器件，特别涉及一种半导体图象传感器。
过去，采用了各种方法在具有互补金属氧化物半导体(CMOS)器件的衬底上形成半导体传感器。一般情况下，传感器的光接收部分形成为大面积晶体管的栅，常称之为光栅，或形成为金属氧化物半导体(MOS)晶体管的源-漏结。采用光栅晶体管时，需要光扫过晶体管的硅栅，以将光转化为电能。因此，采用光栅的情况减小了灵敏度。另外，耗尽区一般较浅(小于一个微米)，所以减小了吸收红光诱发的载流子的收集效率。并且常规光栅对表面复合产生的噪声敏感。
采用源-漏结的情况一般有一个对于晶体管操作最佳的结，并且还有一个会造成红光诱发的载流子无效收集的浅结。采用源-漏结情况的另一缺点是结一般形成于重掺杂(大于1016原子/cm3)区中，限制了结耗尽区的宽度，进而减小了吸收红光诱发的载流子的收集效率。另外，在这种重掺杂区中形成结会产生很大的电容，进而会减少可以从光敏元件传递到其它电子元件的电荷量。
因此，希望形成一种图象传感器，不用光栅可具有较高效率，没有浅结深度可提高效率，可使表面复合噪声最小。
唯一的附图展示根据本发明图象传感器实施例的放大剖面图；
图1是有源象素传感器或半导体图象传感器10的放大剖面图。传感器10包括底层P型衬底11。传感器10具有形成于底层衬底11的第一区13中的第一阱或P阱16。阱16的掺杂浓度一般高于底层衬底11的第二区14的掺杂浓度。区13和14由括弧标识出。第二区14构成衬底11内的第二阱。阱16的表面掺杂浓度一般至少为1×1016原子/cm3。阱16的第一深度或深度24一般约为2-4微米，以便于在衬底11上形成其它CMOS器件。
传感器10的图象获取元件或光敏元件包括形成于第二阱或第二区14中的N型导电区26。导电区26与衬底11的P型材料一起构成第一P-N结。这第一P-N结处于导电区26的第二深度或深度29，以便于容易地感应红光，该深度一般是从衬底11表面算起小于约0.7微米，最好是约小于0.5微米。P型嵌入层37形成于区26内，并从区26向外延伸到衬底11中，以与其电连接。该电连接将加于图象传感器的该元件的电位保持住。因此，所得的光电二极管常被称为嵌入光电二极管。第二P-N结沿层37和区26的交界区形成。一般层37与其它P沟道MOS晶体管(未示出)的轻掺杂漏和源区同时形成于衬底11上。第二P-N结的深度小于第一P-N结的深度。该深度选择成使对蓝光的收集或感应最佳。传递晶体管或第一MOS晶体32邻近导电区26形成，以便区26的一部分构成晶体管32的源。第二或复位MOS晶体管31形成于阱16内。耦合区41使晶体管31的源电耦合到晶体管32。
通过有一开口而露出区14某部分表面的掩模形成延伸到并包括晶体管32一部分栅22的导电区26。然后，以偏离衬底11法线向着栅22的角度注入掺杂剂，以确保区26在栅22下延伸，由此省去形成区26和晶体管32的源时的掩蔽和其它工艺。
现在，应理解，这里提供了一种新颖的图像传感器及其制造方法。形成深导电区和较浅嵌入层，构成了两个P-N结，其中一个P-N结及有关的耗尽区较深，以便于获取红光，第二P-N结及有关的耗尽区较浅，以便于获取蓝光。这种结构还使表面复合作用最大限度地减小，并使电荷最大限度地传递。利用有角度的注入形成导电区，可以保证导电区可用作电荷传递晶体管的源，由此使制造操作步骤最大限度地减少。

Claims (8)

1·一种图象传感器，其特征在于：
具有第一掺杂浓度的第一导电类型的衬底(11)；
衬底上的第一阱(16)，第一阱具有第一导电类型和大于第一掺杂浓度的第二掺杂浓度，其中第一阱具有深入到衬底的第一深度(24)；
与第一阱(16)隔开横向的衬底上的第一MOS晶体管(32)；
与第一MOS晶体管邻接的位于衬底内的第二导电类型的导电区(26)，其中一部分导电区形成第一MOS晶体管的漏，并且导电区(26)具有深入到衬底的第二深度(29)；
第一导电类型的嵌入层(37)，具有形成于导电区(26)内部的第一部分和以远离第一MOS晶体管(32)的方向从导电区横向延伸的第二部分。
2·如权利要求1所述的图象传感器，其特征在于：第二深度(29)大于嵌入层的深度，从而在第一深度处形成第一P-N结，在嵌入层和导电区的交界区附近形成第二P-N结。
3·如权利要求2所述的图象传感器，其特征在于：第二深度(29)近似小于7微米。
4·有源象素传感器的形成方法，其特征在于包括以下步骤：
提供具有第一导电类型的表面和第一导电类型的第一区(16)的衬底(11)；
在第一导电类型的第二区(14)中提供嵌入式光电二极管，使得第二区的第二掺杂浓度小于第一区(16)的第一掺杂浓度，嵌入式光电二极管具有离表面第一深度(29)处的第一P-N结和小于第一深度的第二深度处的第二P-N结；以及
在第二区中至少形成一个MOS晶体管(32)。
5·如权利要求4所述的方法，其特征在于：提供嵌入式光电二极管的步骤还包括以偏离衬底法线的一个角度注入与第一导电类型相反的第二导电类型的掺杂剂，以在MOS晶体管的栅下延伸。
6·如权利要求5所述的方法，其特征在于还包括在第二导电类型的区域(26)内形成嵌入式光电二极管的嵌入层(37)。
7·如权利要求6所述的方法，其特征在于：所注入的第二导电类型的掺杂剂(26)比嵌入层(37)在MOS晶体管的栅(22)的更下方延伸。
8·如权利要求7所述的方法，其特征在于还包括在第一区(16)内形成电耦合于第一MOS晶体管(32)的第二MOS晶体管(31)。
CNB98123996XA 1997-11-14 1998-11-11 半导体图象传感器的结构及其制造方法 Expired - Lifetime CN1139994C (zh)

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US970703 1997-11-14
US08/970,703 US6100556A (en) 1997-11-14 1997-11-14 Method of forming a semiconductor image sensor and structure

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CN1139994C true CN1139994C (zh) 2004-02-25

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US6100556A (en) 2000-08-08
CN1219772A (zh) 1999-06-16
KR100595907B1 (ko) 2006-09-07
TW434898B (en) 2001-05-16
JPH11233748A (ja) 1999-08-27

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