CN113782535A - 高电压应用中的浮栅器件 - Google Patents

高电压应用中的浮栅器件 Download PDF

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CN113782535A
CN113782535A CN202110585500.6A CN202110585500A CN113782535A CN 113782535 A CN113782535 A CN 113782535A CN 202110585500 A CN202110585500 A CN 202110585500A CN 113782535 A CN113782535 A CN 113782535A
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vertically stacked
capacitor
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A·扎卡
T·赫尔曼
F·施拉普霍夫
吴楠
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Dresden First Mock Exam Co ltd And Two Cos
GlobalFoundries Dresden Module One LLC and Co KG
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Abstract

本发明涉及高电压应用中的浮栅器件。本公开涉及半导体结构，更具体地涉及浮栅器件及制造方法。该结构包括：栅极结构，其包括栅极电介质材料和栅电极；以及垂直堆叠的电容器，其位于所述栅电极上方并与所述栅电极电连接。

Description

高电压应用中的浮栅器件
技术领域
本公开涉及半导体结构，更具体地涉及浮栅器件及制造方法。
背景技术
高电压半导体器件被用于各种应用中。这些应用包括例如非易失性存储器装置。利用非易失性存储器的电子设备在减小尺寸的同时需要更大的非易失性数据存储容量。
非易失性存储器单元(memory cell)可以使用“双多晶硅”结构形成，其中控制栅和浮栅分别形成在单独的多晶体硅(也称为多晶硅)层中。然而，由于形成多个多晶硅层需要额外的制造步骤，因此双多晶硅工艺较昂贵。替代地，可以通过提供非常厚的栅极氧化物来制造存储器单元，例如，与传统器件的
Figure BDA0003087130410000011
相比，该栅极氧化物的厚度约为
Figure BDA0003087130410000012
或更大。然而，制造较厚的栅极氧化物也是耗时且昂贵的过程。
在另一种非易失性存储器单元中，用作浮栅的晶体管栅极被耦接(couple)到用作控制栅的电容器。这些存储器单元占用非常大的半导体表面积，因为电容器必须在半导体衬底中实现并且在晶体管侧面布局。具有电容器的非易失性存储器单元还需要最小间距要求，这增加了半导体面积的占用。
发明内容
在本公开的一方面，一种结构包括：栅极结构，其包括栅极电介质材料和栅电极；以及垂直堆叠的电容器，其位于所述栅电极上方并与所述栅电极电连接。
在本公开的一方面，一种结构包括：衬底；浮栅结构，其位于所述衬底上并包括栅极电介质材料和栅电极；以及垂直堆叠的电容器，其位于所述浮栅结构上方，并且具有与所述浮栅结构相同或小于所述浮栅结构的覆盖区(footprint)。
在本公开的一方面，一种方法包括：在衬底上形成栅极结构；以及将电容器形成为位于所述栅极结构的垂直上方并与所述栅极结构电连接。
附图说明
在下面的详细描述中，借助本公开的示例性实施例的非限制性示例，参考所提到的多个附图来描述本公开。
图1示出了根据本公开的方面的栅极结构以及相应的制造工艺。
图2示出了根据本公开的方面的堆叠(stack)在栅极结构上的分压器以及相应的制造工艺。
图3示出了根据本公开的方面的浮栅电压(fg)和输入控制栅(Cg)的表示。
图4示出了根据本公开的方面的堆叠在栅极结构上的分压器的俯视图。
图5至图7示出了对堆叠在栅极结构上的分压器与传统栅电极进行比较的图。
具体实施方式
本公开涉及半导体结构，更具体地涉及浮栅器件及制造方法。更具体地，本公开涉及在例如25V+的高电压应用中使用的浮栅器件。在实施例中，浮栅器件包括栅极结构，在该栅极结构的顶部上具有垂直堆叠的电容器。有利地，本公开允许在不修改栅堆叠的栅极电介质的情况下在栅极堆叠处实现高电压应用，例如25V+的器件。该浮栅器件也没有增大覆盖区，并且进一步降低了栅极制造工艺的复杂性。
在实施例中，将分压器(例如，后段制程(BEOL)电容器)垂直堆叠在形成于衬底上的场效应晶体管(FET)的栅电极的顶部上。优选地，BEOL电容器形成在栅电极的覆盖区之内，尽管也预期BEOL电容器可以延伸超过栅电极的覆盖区。在实施方式中，BEOL电容器(即分压器)可以通过与栅电极的电容性耦接来控制施加到FET的栅电极的电压。例如，通过将BEOL电容器的连接部直接耦接到FET的栅电极，并且在实施例中，保持某些浮置连接，可以控制施加到FET的栅电极的电压。
本公开的浮栅器件可以使用多种不同的工具，以多种方式来制造。然而，一般地，方法和工具被用来形成具有微米和纳米级尺寸的结构。已经根据集成电路(IC)技术采用了用于制造本公开的浮栅器件的方法(即，技术)。例如，这些结构建立在晶片上，并在借助晶片顶部上的光刻工艺而图案化的材料膜中实现。具体地，浮栅器件的制造使用三个基本构造块：(i)在衬底上沉积材料薄膜；(ii)通过光刻成像在膜顶部上施加图案化掩模；以及(iii)对掩模有选择性地蚀刻膜。
图1示出了根据本公开的方面的栅极结构以及相应的制造工艺。更具体地，图1所示的结构10包括形成在衬底14上的栅极结构12。在实施例中，衬底14可以是任何适当的半导体材料。例如，衬底14可以由任何合适的材料组成，其中包括但不限于Si、SiGe、SiGeC、SiC、GaAs、InAs、InP以及其它III/V或II/VI族化合物半导体。此外，衬底14可以代表诸如体硅的单一半导体材料。替代地，衬底可以包括本领域中公知的绝缘体上半导体(SOI)技术，因此不需要进一步的解释就可以完全理解本公开。
仍参考图1，栅极结构12包括栅极电介质材料16和栅电极18。在实施例中，栅极电介质材料16可以是高k栅极电介质材料，例如，HfO2、Al2O3、Ta2O3、TiO2、La2O3、SrTiO3、LaAlO3、ZrO2、Y2O3、Gd2O3，以及包括其多层的组合。栅极电介质材料16可以具有约
Figure BDA0003087130410000031
或更大的厚度；但是这里也可以预期其他厚度。栅电极18可以是例如多晶硅材料。
在实施例中，通过常规的沉积、光刻和蚀刻工艺来形成栅极电介质材料16和栅电极18。例如，栅极电介质材料16可以通过作为示例的常规原子层沉积(ALD)工艺或等离子体增强化学气相沉积(PECVD)工艺来沉积。栅电极18可以通过利用CVD沉积工艺在栅极电介质材料16上沉积多晶硅材料来形成。在沉积工艺之后，使用常规的光刻和蚀刻工艺来图案化栅极电介质材料16和栅电极18的材料，因此不需要进一步的解释就可以完全理解本公开。侧壁间隔物20通过常规的沉积工艺形成在栅极结构12上，然后进行各向异性蚀刻工艺。侧壁间隔物20可以是例如氮化物材料。
图1还示出了通过常规的离子注入工艺形成的源区和漏区22或通过掺杂的外延生长工艺形成的抬升的源区和漏区22。例如，在外延生长工艺中，通过在衬底14上选择性地生长半导体材料形成外延区域(源区/漏区)。尽管未示出，但是衬底14可以包括通过引入掺杂剂(借助例如在衬底14中引入一定浓度的掺杂剂的离子注入)而形成的阱。除了其他合适的示例之外，P阱被掺杂有p型掺杂剂，例如硼(B)；N阱被掺杂有n型掺杂剂，例如砷(As)、磷(P)和Sb。
图2示出了垂直堆叠在栅极结构12上的分压器24以及相应的制造工艺。更具体地，分压器24是垂直堆叠在栅极结构12上的BEOL电容器。如图2所示，BEOL电容器24不增大器件(例如栅极结构12)的覆盖区，因为它被定位在栅极结构12的垂直上方；也就是，BEOL电容器24可以具有与栅极结构12相同或与之相比更小的覆盖区。在一个非限制的示例性实施例中，BEOL电容器24可以是金属-氧化物-金属(MOM)电容器或交替极性金属-氧化物-金属(APMOM)电容器。在后一种情况下，位于同一布线层级上的布线28将在正负之间交替。
根据设计参数，BEOL电容器24可以包括一层或多层布线28。例如，布线28的层数的增加将使电容增大；而布线28层数的减少将使电容减小。此外，可以调节同一层级或层或不同层级上的布线28之间的间隔或布线28的尺寸，以增大或减小电容密度。例如，在施加8V电压时使用五个金属层将导致1:4的电容耦合，从而将现有的20V高电压(HV)栅极氧化物扩展到25V HV应用中。类似地，在施加12V电压时使用三个金属层将导致1:1.67的电容耦合，从而将现有的20V高电压(HV)栅极氧化物扩展到32V HV应用中。下面提供了更详细的示例。
BEOL电容器24通过布线或互连结构26耦接到栅极结构12的栅电极18。例如，BEOL电容器24的至少一个或多个布线28通过布线或互连结构26直接连接到栅电极18。以此方式，在施加电压时，栅极结构12变为浮动节点(例如，浮栅器件)。此外，可以可选地通过氮化物层30来分隔一层或多层布线28。BEOL电容器24和布线或过孔结构26形成在电介质材料32内。在实施例中，电介质材料32是层级间电介质材料，其包括例如SiO2。此外，例如，栅极电介质材料16的厚度与后段制程电介质材料(例如，电介质材料32)的厚度之比可以是1:1至1:4。
使用本领域技术人员公知的常规光刻、蚀刻和沉积方法，可以将BEOL电容器24(例如，布线结构和互连结构)形成为具有与栅极结构12相同或比其更小的覆盖区。例如，形成在电介质材料32的层上方的抗蚀剂被暴露于能量(光)下以形成图案(开口)。将使用具有选择性化学作用的蚀刻工艺(例如反应离子蚀刻(RIE))来通过抗蚀剂的开口在电介质材料32中形成一个或多个沟槽。在利用常规的氧灰化工艺或其他已知的剥离剂去除抗蚀剂之后，可以通过任何常规的沉积工艺(例如化学气相沉积(CVD)工艺)来沉积导电材料。在形成下一层之前，可以通过常规的化学机械抛光(CMP)工艺去除绝缘体材料表面上的任何残留材料，然后可选地沉积氮化物材料30。该工艺可以继续形成所需的布线28的层数。因此，尽管图2示出了三层布线28，但是此处可以根据设计参数(例如耦合电容、栅极氧化物处的期望电压等)构想任何数量的布线层。
在实施例中，如图3所示，通过与互连结构26和输入控制栅(Cg)的电容耦合来控制浮栅电压(fg)。耦合比可通过BEOL电容器24(MOM或APMOM)的适当选择(例如，不同布线的间距、数量和尺寸)来设计，其中浮栅电压中的初始电荷通过BEOL结构中的最终退火(例如400℃)排空。例如，通过各种端子(例如，布线28)控制电容耦合，而不会发生通过电介质(即，隧穿)从栅极结构12(例如浮栅)到与栅电极(例如，多晶硅)18接触的衬底14或布线28的任何有效电荷转移。以此方式，借助电容耦合，通过在浮栅12中积聚的电荷量来调制器件的Vth。而且，利用BEOL电容器24通过精确的电容耦合来控制分压，现在可以实现更高的输入电压(例如25V/30V)。
图4示出了根据本公开的方面的堆叠在栅极结构上的分压器的俯视图。分压器24(例如BEOL电容器)包括被配置为指状物的多个布线28。BEOL电容器24还被显示为垂直堆叠在栅极结构12上，例如堆叠在栅电极上方，并且具有与栅极结构12相同或比栅极结构12更小的覆盖区。此外，BEOL电容器24包括两个自由度：(i)水平金属线之间的间距和金属线的厚度本身；以及(ii)金属层的数量。
下面的表1提供了实现本文所述的BEOL电容器的不同应用的示例，例如25V和30V的输入电压。
表1
Figure BDA0003087130410000061
图5至图7示出了比较表1中的示例的图(例如，栅极电介质厚度为
Figure BDA0003087130410000071
的栅极器件与本公开中描述的BEOL电容器组合)。更具体地说，在图5示出的图中，X轴表示输入电压(V)，Y轴表示浮栅电压(V)。如该图所示，表1中表示的示例“B”和“C”中的每一个以及常规器件“A”提供大约20V的浮栅电压。这表明在以上示例中示出的电容器布局的尺寸和利用将在HV晶体管(例如，器件12的栅极氧化物16)处产生期望的栅极电压。
图6和7分别示出了其中X轴表示输入电压(V)，Y轴表示漏极电流(A/μm)的图。如图6的图形所示，表1中表示的示例“B”和“C”中的每一个以及常规器件“A”具有相似的开关特性。另一方面，如图7所示，表1中表示的示例“B”和“C”中的每一个以及常规器件“A”具有相似的漏极电流。因此，这表明示例“B”和“C”的Idsat相对于常规器件“A”而言几乎没有变化。
可以在片上系统(SoC)技术中利用所述浮栅器件。本领域技术人员应当理解，SoC是将电子系统的所有组件集成在单个芯片或衬底上的集成电路(也称为“芯片”)。由于组件集成在单个衬底上，因此与具有等效功能的多芯片设计相比，SoC消耗的功率少得多，占用的面积也小得多。因此，SoC正成为移动计算(例如智能手机)和边缘计算市场中的主导力量。SoC也常用于嵌入式系统和物联网。
上述方法用于集成电路芯片的制造。所得到的集成电路芯片可以由制造商以原始晶片形式(即，作为具有多个未封装芯片的单个晶片)，作为裸芯或以封装形式分发。在后一种情况下，芯片以单芯片封装(例如塑料载体，其引线固定到主板或其它更高级别的载体)或多芯片封装(例如陶瓷载体，其具有表面互连和/或掩埋互连)的形式被安装。在任何情况下，芯片然后与其它芯片、分立电路元件和/或其它信号处理器件集成，作为(a)中间产品(例如主板)或(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其它低端应用到具有显示器、键盘或其它输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已经出于说明的目的给出，但并非旨在是穷举的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的选择旨在最好地解释各实施例的原理、实际应用或对市场中发现的技术的技术改进，或者使本技术领域的其他普通技术人员能够理解本文公开的实施例。

Claims (20)

1.一种结构，包括：
栅极结构，其包括栅极电介质材料和栅电极；以及
垂直堆叠的电容器，其位于所述栅电极上方并与所述栅电极电连接。
2.根据权利要求1所述的结构，其中，位于所述栅电极上方的所述垂直堆叠的电容器包括一个或多个布线层。
3.根据权利要求2所述的结构，其中，所述垂直堆叠的电容器包括多个垂直堆叠的布线层。
4.根据权利要求2所述的结构，其中，所述垂直堆叠的电容器通过互连而电连接到所述栅电极。
5.根据权利要求2所述的结构，其中，所述栅极电介质材料的厚度为
Figure FDA0003087130400000011
或更大，并且所述栅极电介质材料的厚度与后段制程电介质材料的厚度之比为1:1至1:4。
6.根据权利要求2所述的结构，其中，所述垂直堆叠的电容器具有与所述栅极结构相同的覆盖区。
7.根据权利要求2所述的结构，其中，所述垂直堆叠的电容器具有小于所述栅极结构的覆盖区。
8.根据权利要求2所述的结构，其中，所述栅极结构是浮栅器件。
9.根据权利要求8所述的结构，其中，所述垂直堆叠的电容器包括通过所述垂直堆叠的电容器施加的控制栅电压和浮栅电压(fg)。
10.根据权利要求9所述的结构，其中，所述垂直堆叠的电容器提供通过所述垂直堆叠的电容器的各种布线来控制的电容耦合，这引起从所述栅极结构到与所述栅电极接触的衬底或端子的电荷转移。
11.根据权利要求2所述的结构，其中，所述垂直堆叠的电容器是金属-氧化物-金属(MOM)电容器。
12.根据权利要求2所述的结构，其中，所述垂直堆叠的电容器是交替极性金属-氧化物-金属(APMOM)电容器，其包括在正负之间交替的位于同一布线层级上的布线。
13.一种结构，包括：
衬底；
浮栅结构，其位于所述衬底上并包括栅极电介质材料和栅电极；以及
垂直堆叠的电容器，其位于所述浮栅结构上方，并且具有与所述浮栅结构相同或小于所述浮栅结构的覆盖区。
14.根据权利要求13所述的结构，其中，所述垂直堆叠的电容器包括多个垂直堆叠的布线层。
15.根据权利要求13所述的结构，其中，所述栅极电介质材料的厚度为
Figure FDA0003087130400000021
或更大，并且所述栅极电介质材料的厚度与后段制程电介质材料的厚度之比为1:1至1:4。
16.根据权利要求13所述的结构，其中，所述垂直堆叠的电容器包括通过所述垂直堆叠的电容器施加的控制栅电压和浮栅电压(fg)。
17.根据权利要求13所述的结构，其中，所述垂直堆叠的电容器提供通过所述垂直堆叠的电容器的各种布线来控制的电容耦合，这引起从所述栅极结构到与所述栅电极接触的衬底或端子的电荷转移。
18.根据权利要求13所述的结构，其中，所述垂直堆叠的电容器是金属-氧化物-金属(MOM)电容器。
19.根据权利要求13所述的结构，其中，所述垂直堆叠的电容器是交替极性金属-氧化物-金属(APMOM)电容器，其包括在正负之间交替的位于同一布线层级上的布线。
20.一种方法，包括：
在衬底上形成栅极结构；以及
将电容器形成为位于所述栅极结构的垂直上方并与所述栅极结构电连接。
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