CN1134604A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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CN1134604A
CN1134604A CN95120132A CN95120132A CN1134604A CN 1134604 A CN1134604 A CN 1134604A CN 95120132 A CN95120132 A CN 95120132A CN 95120132 A CN95120132 A CN 95120132A CN 1134604 A CN1134604 A CN 1134604A
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八寻和之
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Abstract

本方法提高了半导体基板上形成回流绝缘膜的抗裂性并确保其平坦化所需的膜厚。其特征是具备下述工序：在基板上形成下层布线32后，形成厚度大于0.1μm的第1等离子体SiO2膜33；使SiH4气体和H2O2在低于650Pa的真空中，在-10℃以上+10℃以下范围内相互反应，在基板上形成厚度大于0.4μm小于1.4μm的回流SiO2膜34；之后，在规定真空中把基板放置30秒以上；在高于300℃不到450℃的高温中放置120秒以上600秒以下；在基板上形成厚度大于0.3μm的第2等离子体SiO2膜35。

Description

半导体装置的制造方法
本发明涉及半导体装置的制造方法，特别是涉及具有多层布线构造的半导体装置的层间绝缘膜的形成方法。
随着半导体装置的集成度的增大，技术发展为在基板上形成多层布线材料的所谓多层布线化，使得具有这种多层布线构造的半导体装置的制造工艺复杂化，长工序化。
特别是多层布线的形成工艺在半导体装置的制造价格中所占比例很大，故在减少多层布线工序方面的要求日益高涨，以求得降低半导体装置的价格。
在此，对现有的多层布线的形成工序进行说明。首先，在淀积好用作下层布线的第1布线材料之后，进行下层布线的图形化，并在此下层布线上边形成第1绝缘膜的同时在下层布线彼此之间埋入绝缘膜。在这一时刻，取决于上述下层布线的图形等等面在第1绝缘膜的表面上存在有台阶，如果不加处理的话，在今后淀积用作上层布线的第2布线材料和上层布线图形化时将会产生不利影响，并存在着带来因上层布线在台阶处断开所形成断线、短路等重大缺陷的危险。
所以，通常在上述第1绝缘膜的上边淀积第2布线材料之前，把作为其基底的第1绝缘膜的表面用光刻胶反复刻蚀(Resist efchback)的办法使之平坦化的使台阶平缓之后，在其上边形成第2绝缘膜。
上述这样的把第1绝缘膜和第2绝缘膜叠层之后的现有的层间绝缘膜和形成工序，由于具有第1次成膜→平坦化→第2次成膜这样的多道工序，故对上述那种减少多层布线工序的要求来说成了一个大障碍。
此外，人们知道还有一种可以取代上边所说的那种使第1绝缘膜平坦化的方法。这种方法采用在第1绝缘膜上边形成作为绝缘材料的自旋玻璃(Spin on Glass；SOG)的办法来缓和上层布线材料的基底的台阶。
但是，这种在形成(烧成)SOG膜的时候需要多次的热处理工序，必须要用光刻胶反复刻蚀除去SOG膜的没用的部分以确保上层布线的可靠性。结果是工序数增多，仍然不能充分满足上述那种减少多层布线工序的要求。
可是，最近，作为一种能够满足上述减少多层布线工序的要求的技术，在形成层间绝缘膜之际，通过采用使SiH4气体和作为氧化剂的H2O2(过氧化氢水)在低温(比如说在0℃左右)和真空中进行反应的办法，在下层布线上边形成自我流动型(回流：reflow)的绝缘膜(以下称之为回流绝缘膜)的方法引起了人们的重视。
这种方法，由于可同时实现下层布线的布线相互之间的绝缘膜的埋入和绝缘膜表面的平坦化，用一次的成膜可结束直到平坦化为止的工序，故可以实现减少多层布线的工序的目的。
但是，上述那种回流绝缘膜的形成方法，如从其反应形态所知道的那样，在绝缘膜的成膜过程中产生了水分(H2O)，从而绝缘膜中含有大量的水分，所以在成膜过程中或者成膜之后进行必要的热处理(例如在450℃，30分钟)时，膜中水分将急剧地放出而使绝缘膜附裂(以下称之为产生裂缝)。
图4示出了实测数据，它实测的是用上述那种回流绝缘膜的形成法形成的回流SiO2膜上产生了裂缝的状况。在这种情况下，示出了以回流SiO2膜的膜厚和在回流绝缘膜上用通常的等离子体CVD(气相生长)法形成了SiO膜(以下称之为盖(cap)膜)时的盖膜厚为参数，在成膜之后以450℃进行了30分钟的热处理时的裂缝产生状况。
从图4可知，在不存在盖膜和即使存在盖膜但在回流SiO2膜的膜厚大于1.1μm的时候也会产生裂缝。换句话说，在抗裂缝性这一点上，在回流SiO2绝缘膜的膜厚中存在着上限，在本例中膜厚上限较低，约为1.0μm。
但是，在使用上述那样的回流SiO2膜时，要想把形成于层间绝缘膜上边的上层布线的基底台阶弄成足够平缓(平坦化)，就必须确保某种程度的膜厚，而且，改善抗裂缝性是重要的。
另外，在回流SiO2膜的上部用通常的等离子体CVD法形成层间绝缘膜时，由于半导体大片尚未充分地升温，故形成了湿法刻蚀速率低的绝缘膜。这样一来，在层间绝缘膜形成之后要进行的用于开贯穿孔或穿透孔的刻蚀中，层间绝缘膜与回流SiO2膜之间的界面将变为异常的刻蚀形状，使在其后形成的上层布线的敷层恶化，将成为招致上层布线导通不良的原因。
像上述那样在现有的多层布线工序中的层间绝缘膜形成工序里采用回流绝缘膜形成技术的情况下所得到的回流SiO2膜，即便是想确保已考虑了其平坦化所需的膜厚也还存在着在抗裂缝性这一点上上限会被压低的问题。
另外，在上述回流SiO2膜的上部的层间绝缘形成之后进行的用于开贯穿孔或穿透孔的刻蚀时，存在着层间绝缘膜与回流SiO2膜之间的界面将形成异常的刻蚀形状、使上层布线的敷层恶化，变成为导致上层布线导通不好的原因这样的问题。
本发明是为了解决这些问题而形成的，所以目的是提供一种半导体装置的制造方法。这种制造方法可以提高在半导体装置的多层布线工序中的层间绝缘膜形成工序里采用回流绝缘膜形成技术时所得到的回流绝缘膜的抗裂缝性，并可确保考虑了回流绝缘膜的平坦化的所需的膜厚，而且可以制造在层间绝缘膜形成后所形成的上层布线的可靠性高的半导体装置。
本发明的半导体制造方法的特征是它具有回流膜形成工序和基板放置工序，上述回流膜成工序向放有形成绝缘膜之后的半导体基板的反应室内导入SiH4气体和H2O2并在650Pa以下的真空中，在-10℃以上+10℃以下的温度范围内使上述SiH4气体与H2O2相互进行反应，在上述半导体基板上形成具有回流形状的厚度大于0.4μm，小于1.4μm的回流SiO2膜，上述基板放置工序包括在膜形成后在上述反应室内，在指定的真空中把上述半导体基板放置30秒以上的放置工序，和接着把上述半导体基板在300℃以上不到450℃的高温中放置120秒以上但小于600秒的时间的放置工序。
在多层布线工序中的层间绝缘膜形成的工序中，通过采用回流绝缘膜形成的技术，并在形成回流SiO2膜之后在规定的真空中放置规定时间以上，再在规定的高温中放置规定的时间以上的办法，就可以控制回流SiO2膜中的水分显并可改善抗裂缝性。
由于借助于这样地改善回流SiO2膜的抗裂缝性，可以确保已考虑了回流绝缘膜平坦化的所需的膜厚，故可以改善层间绝缘膜的表面的平坦性，并可使在层间绝缘膜形成之后形成的上层布线进一步微细化。
而且，可以防止在层间绝缘膜形成后进行的用于开贯穿孔或穿透孔的刻蚀中的异常刻蚀，并可改善上层布线的可靠性，不使在刻蚀后形成的上层布线的敷层恶化，也不导致上层布线的导通不良。
图1的构成说明图概略性地示出了在本发明的半导体装置的制造方法中所用的半导体制造装置的一个例子。
图2的剖面图示出在本发明的半导体装置的制造方法中所涉及的层间绝缘膜形成工序里采用了回流绝缘膜形成技术的多层布线工序的一个例子。
图3示出了对用图1的工序所得到的回流SiO2膜，以其膜厚和形成于回流SiO2膜上的盖SiO2膜的膜厚为参数进行热处理时的裂缝产生状况的实测结果。
图4示出了裂缝产生状况的实测结果，这是对在制造现有的半导体装置时在层间绝缘膜形成工序中，用采用了回流绝缘膜形成技术的多层布线工序所得到的回流SiO2膜，以其膜厚和形成于回流SiO2膜上的盖SiO2膜的膜厚为参数进行热处理时实测到的裂缝产生状况。
实施例
以下参照附图详细说明本发明的一个实施例。
图1(a)概略性地示出了本发明的半导体装置的制造方法中所用的半导体制造装置结成的一个例子。
在图1(a)中，10是等离子体GVD装置，20为减压CVD装置，1为收容并固定半导体基板的箱式(casseffe)装片机室，2为在上述箱体装片室1与上述等离子体GVD装置10的反应室或者减压GVD装置20的反应室之间运送(送入、送出)半导体基板的机械手。
上述等离子体GVD装置10具有通常的构成，其构成情况的一个例子概略性地示于图1(b)。图1(b)中，11为反应室(chamber)，12为上部电极(shower head：喷啉头)，13为下部电极(table：工作台)，14为排气口，15为工艺气体(process gas)供给通路，16为高频电力供给电路。
上述减压GVD装置具有通常的构成。图1(c)中概略性地示出了它的一个构成例。在图1(c)中，21是反应，22是上部电极，23是下部电极，24是排气口，25是SiH4气体供给通路，26是H2O2供给通路。
图2(a)到(e)示出了在本发明的半导体装置的制造方法中所涉及的多层布线工序中的层间绝缘膜形成工序里采用了回流绝缘膜形成技术的多层布线工序的一个例子。
以下参照图1和图2，说明本发明的半导体装置的制造方法中所涉及的在层间绝缘膜形成工序中采用了回流绝缘膜形成技术的多层布线工序的一个例子。
首先，如图2所示，在半导体基板30上的绝缘膜31的上边比方说用溅射法淀积上用作下层布线的第1布线材料(比如铝)之后，应用光刻技术和反应性离子刻蚀(RIE)技术，进行第1布线材料的图形化进而形成下层布线32。
其次，使用上述半导体制造装置，把绝缘膜埋入上述下层布线32的布线之间，同时在下层布线上边淀积绝缘膜以形成层间绝缘膜。
在上述层间绝缘膜形成工序中，把形成下层布线后的半导体基板30放置于上述箱式装片机重1内的比如说石英舟上。
接着，用真空泵(没有画出来)把箱式装片机室1内设定为规定的真空状态，并用机械手2把上述半导体基板送到等离子体CVD装置10的反应室11内。将该等离子体CVD装置10的反应11内事先设定为约300℃，在半导体基板20上边的整个面上形成厚度大于0.1μm(本例中为100nm)的作为第1绝缘膜的第1等离子体SiO2膜33。
其次，用机械手22，把上述半导体基板30从CVD装置的反应室11内运往减压CVD装置的反应室21内。并经由SiH4气体供给通路25和H2O2供给通路26，从SiH4气体供给源和H2O2供给源向该减压CVD装置的反应室21内导入SiH4气体和H2O2，使之在低于650Pa的真空中，在-10℃以上+10℃以下的温度范围内(例如0℃)下相互反应，如图2(b)所示，就会在上述半导体基板30上得到具有回流形状的厚度大于0.4μm小于1.4μm的回流SiO2膜34。
接着，如图2(c)所示，把上述半导体基板30在上述减压CVD装置的反应室11内在低于6.5Pa的真空中放置30秒以上(在本例中放置30秒)。
其次，用机械手2，把上述半导体基板30从减压CVD装置的反应室21内运往等离子体CVD装置的反应室11内。并如图2(d)所示，在等离子体CVD装置10的反应室内，在高于300℃且不到450℃的高温(在本例中为300℃)中放置120秒以上600秒以下的时间(在本例中为120秒)。
之后，如图2(e)所示，在半导体基板30上的整个面上形成厚度大于0.3μm(在本例中为300nm)的作为第2绝缘膜的第2等离子体SiO2膜35。
此后，从上述半导体制造装置中取出上述半导体基板30，用别的半导体制造装置在450℃下进行30分钟的炉内退火。
然后，进行用于在层间绝缘膜打接触孔或穿透孔的刻蚀，并在淀积好用于上层布线的第2布线材料之后，进行图形化以形成上层布线。
在此，在图3中示出了一个实测结果。它是在用上述实施例制得的回流SiO2膜34的成膜之后，在450℃下进行了30分钟的热处理的情况下，以回流SiO2膜34的膜厚和在回流SiO2膜上边形成了等离子体SiO2膜(盖膜)时的盖膜厚为参数，实测的产生裂缝的状况。
从图3可知，在本实施例中所制得的回流SiO2膜34，在盖膜不存在时的裂缝特性与现有例相比没有变化，但在存在盖膜的情况下，不产生裂缝的膜厚上限，从现有例的大体上1.0μm上升到大体上约2.0μm，提高了抗裂缝性。
若采用上述实施例，则在多层布线工序中的层间绝缘膜形成工序中采用回流绝缘膜形成技术，在形成了回流SiO2膜34之后，安在规定的真空中放置规定的时间以上，还安在规定的高温中放置规定时间以上。
这样一来，即使假定在回流SiO2膜34的形成工序中，在绝缘膜的成膜过程中产生了水分因而在绝缘膜中含有水分，也可通过进行控制使得减少绝缘膜中的水分，从而可得到抗裂缝性良好的回流SiO2膜34。
通过采用这样地改善回流SiO2膜的抗裂缝性的办法，就在可能确保考虑了回流SiO2膜的平坦化的所需的膜厚。
因而，可以提高层间绝缘膜的表面的平坦性，同时还可以防止因上层布线在台阶处断裂而产生断线、短路等重大缺陷的危险而又不会给层间绝缘膜形成后上层布线材料淀积时和上层布线的图形化时带来不良影响。
此外，若采用上述实施例，则在回流SiO2膜的上部用通常的等离子体CVD法形成层间绝缘膜时，由于半导体大片上充分升温，故不会形成湿法刻蚀速率慢的绝缘膜，在形成层间绝缘膜后进行的用于开贯穿孔或穿透孔的刻蚀中也不会使层间绝缘膜和回流SiO2膜之间的界面的刻蚀形状变得异常，在其层形成的上层布线的敷层不会恶化，也不会导致上层布线的导通不良。
如上所述，若采用本发明的半导体装置的制造方法，则由于可以提高在多层布线工序中的层间绝缘膜形成工序里，在采用回流绝缘膜形成技术的情况下所得到的抗裂缝性，且可以确保考虑了回流绝缘膜的平坦化的所需的膜厚，所以可以提高层间绝缘膜的表面的平坦性，且可使在层间绝缘膜形成后所形成的上层布线进一步微细化。
而且，可以防止在层间绝缘膜形成后进行的用于开贯穿孔或穿透孔的刻蚀中的异常刻蚀，且不会使在之后形成的上层布线的敷层恶化、或导致上层布线的导通不良，从而可以提高上层布线的可靠性。

Claims (6)

1.一种半导体装置的制造方法，其特征是：它具有回流膜形成工序，用于向放置形成第1绝缘膜后的半导体基板的反应室内导入SiH4气体和H2O2，使上述SiH4气体和H2O2在低于650Pa的真空中，在-10℃以上+10℃以下的温度范围内相互进行反应，以在上述半导体基板上形成具有回流形状的厚度大于0.4μm，小于1.4μm的回流SiO2膜；放置工序，用于在形成上述膜之后，在上述反应室内在规定的真空中把上述半导体基板放置30秒钟以上；放置工序.用于接着把上述半导体基板在高于300℃，不足450℃的温度中放置120秒以上600秒以下的时间。
2.权利要求1所述的半导体装置的制造方法，其特征是：在上述120秒以上600秒以下的放置工序之后，还具备在上述回流SiO2膜上边形成第2绝缘膜的工序。
3.权利要求2所述的半导体装置的制造方法，其特征是在形成上述第2绝缘膜后，进行450℃、30分钟的炉内退火。
4.一种半导体装置的制造方法，其特征是它具备下述工序：
把已形成了布线层的半导体基板送入等离子体CVD装置中去的工序、
在上述半导体基板上形成厚度大于0.1μm的第1等离子体SiO2膜的工序、
把上述半导体基板从上述等离子体CVD装置运往减压CVD装置的工序、
向上述减压CVD装置内导入SiH4和H2O2、使这些SiH4气体和H2O2在650Pa以下的真空中，在-10℃以上+10℃以下的温度范围内相互进行反应，在上述半导体基板上形成具有回流形状的、厚度在0.4μm以上、1.4μm以下的回流SiO2膜的工序、
在上述回流SiO2膜形成之后，把上述半导体基板在上述减压CVD装置中放置30秒的工序、
把上述半导体基板从上述减压CVD装置运送至上述等离子体CVD装置的工序、
把上述半导体基板在高于300℃不到450℃的温度中放置120秒以上600秒以下的工序。
5.权利要求4所述的半导体装置的制造方法，其特征是在上述120秒以上600秒以下的放置工序之后，还具有在上述回流SiO2膜上形成第2等离子体SiO2膜的工序。
6.权利要求5所述的半导体装置的制造方法，其特征是在上述第2等离子体SiO2膜形成之后，进行450℃、30分钟的炉内退火。
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JPH08181276A (ja) * 1994-12-26 1996-07-12 Toshiba Corp 半導体装置の製造方法
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CN106118636A (zh) * 2016-06-27 2016-11-16 高大元 一种荧光氧化硅纳米颗粒的制备方法

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EP0720212A2 (en) 1996-07-03
CN1082721C (zh) 2002-04-10
DE69522195D1 (de) 2001-09-20
DE69522195T2 (de) 2002-04-18
EP0720212A3 (en) 1997-07-02
EP0720212B1 (en) 2001-08-16
US6153542A (en) 2000-11-28
KR0184378B1 (ko) 1999-04-15
SG42823A1 (en) 1997-10-17
JPH08181276A (ja) 1996-07-12
TW312817B (zh) 1997-08-11

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