CN1144270C - 制造具有多层布线层的半导体装置的方法 - Google Patents

制造具有多层布线层的半导体装置的方法 Download PDF

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CN1144270C
CN1144270C CNB981205534A CN98120553A CN1144270C CN 1144270 C CN1144270 C CN 1144270C CN B981205534 A CNB981205534 A CN B981205534A CN 98120553 A CN98120553 A CN 98120553A CN 1144270 C CN1144270 C CN 1144270C
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小田典明
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Abstract

这里提供一种制造即使在小线距时也具有小线容的半导体装置的制造方法。所包含的步骤包括在线层上形成包含三氧化二硅氢(HSQ)膜层的绝缘夹层，把氢离子植入HSQ膜层，并且对该半导体装置进行低温退火等。

Description

制造具有多层布线层的半导体装置的方法
本发明涉及一种半导体装置制造方法，具体地说，涉及一种制造具有多层布线层并使用三氧化二硅氢(hydrogen silsesquioxance，往后缩写为HSQ)作为夹层绝缘膜的半导体装置的方法。
与近年来的小型化趋势相适应，具有多层布线层的半导体装置的布线间距已经被减小。当布线间距减小时，相邻布线间的距离减小并且被称作线容的相邻导线间的电容增加。因而，运行速度放慢并且电源消耗增加。为解决此问题，这里建议使用具有低介电常数的薄膜(低介电常数膜片)作为绝缘夹层来代替到目前为止使用的氧化硅膜片。通过使用低介常数膜片，既使对于具有小线距的半导体装置来说也有可能实现小线容。
由不同材料制作的低介电常数膜片已经进行了研究和开发。具体地讲，HSQ是一种最具应用前景的低介电常数膜，因为它具有1400℃或更高的热阻。
传统的使用HSQ作为绝缘夹层的半导体装置制造方法在T.Zoes，B.Ahlburn，K.Erz，及M.Marsden，等人的论文“在亚0·5μm范围中可流动氧化物的平面化表现”中描述。该论文收在材料研究学会(MaterialsResearch Society)会议报告集，ULSIXI 1996中，PP.121-125(1996)。
与上述文件中所描述的方法相同的传统半导体装置制造方法在下面作以描述，参见图7A和7B以及图8A和8B。
图7A中，在由BPSG(Boro-phospho-Silicate Glass硼——磷酰——硅化玻璃)膜组成的厚度约为0.8μm的第1绝缘夹层1上形成了由厚度约为30nm的钛膜和厚度约为100nm的氮化钛膜组成的第1耐火金属膜2，由厚度约为0.5微米的AlCu膜组成的第1金属膜3，以及由厚度约为50nm的氮化钛膜组成用来在光刻工艺中防止反射的第1防反射膜4。这些膜层按照所述顺序通过溅射方法从底层开始形成。然后，通过光刻工艺和反应离子蚀刻形成图案以形成由第1耐火金属膜2，第1金属膜3以及第1防反射膜4组成的第1线层。此后，具有大约50nm厚度的第1氧化等离子膜通过使用SiH4和NH3的混合气体的等离子CVD方法形成。还有，HSQ被涂在第1线层上使得HSQ的膜层厚度达到大约0.4微米并且随之经过烘烤形成HSQ膜层6作为绝缘夹层。再者，具有大约1.4微米厚度的第2氧化等离子膜7使用等离子CVD方法在HSQ膜层6上形成。至少通过化学抛光或机械抛光使得HSQ膜层6和第2氧化等离子膜层7的总厚度在第1线层上达到0.8微米。
随后，如图7B所示，第1通路孔8通过光刻工艺和反应离子蚀刻形成。接着，由钛层组成的具有大约30nm厚度的第2耐火金属层9和具有大约100nm厚度的氮化钛膜层通过溅射方法在第1通路孔8中和第2氧化等离子膜层7上形成。更进一步，通过利用WF8或同类材料作为气体源的CVD方法使钨层沉积大约0.5微米并且在此后通过逆向蚀刻使第1钨膜层10仅仅留存于通路孔8中。然后，由AlCu膜组成具有大约0.5微米厚度的第2金属膜11和由氮化钛膜组成具有大约50nm厚度的第2防反射膜12通过溅射方法在整个表面上形成。再者，通过光刻工艺和反应离子蚀刻来形成图案以形成由第2耐火金属膜层9，第2金属膜层11和第2防反射膜层12组成的第2线层。
然后，如图8A中所示，具有大约50nm厚度的第3氧化等离子膜层通过利用SiH4和Mn的混合气体的等离子CVD方法形成。此后，通过在第2线层上涂HSQ并进行烘烤形成大约1.4微米厚的HSQ膜层15。再者，通过等离子CVD方法在HSQ膜层上形成具有大约1.4微米厚度的第4氧化等离子膜层16。随后，至少通过化学抛光或机械抛光使得HSQ膜层15与第4氧化等离子膜层16的总厚度在第2线层上达到大约0.8微米。接着，第2通路孔17通过光刻工艺和反应离子蚀刻法形成。然后，由厚度大约30nm的钛膜层和厚度大约为100nm的氧化钛膜层组成的第3耐火金属膜层18通过溅射方法在第2通路孔17中形成。再者，通过利用WF6或类似材料作为气体源的CVD方法使钨层沉积至厚度约为0.5微米，并且在此后，通过逆向蚀刻使钨仅仅留存在通路孔17中以形成第2钨膜层100。接着，由厚度约为0.5微米的Alcu膜层组成的第3金属膜层19以及由厚度约为50nm的氮化钛膜层组成的第3防反射膜层20通过溅射法在整个表面上形成。接着，通过光刻工艺和反应离子蚀刻形成图案从而形成由第3耐火金属膜层18，第3金属膜19以及第3防反射膜20组成的第3线层。
然后，如图8B中所示，形成由厚度约为0.8微米的氧化等离子膜层和厚度约为0.3微米的SiON等离子膜层组成的覆膜层22。
上述传统制造方法有一个问题，即HSQ的电介电常数在加工过程中上升，尽管这里作为低介电常数膜层的HSQ膜被用作绝缘夹层，因而，线容也增加了。
其原因在于，当高温热量在HSQ膜层形成后被施加在HSQ膜层上时，一些Si-H键被破坏并被转变成Si-OH键。因此，HSQ膜层中的Si-H键的数目减少，并因之使HSQ膜层的介电常数增加。据估计，上述传统方法中Si-H键的破坏发生在大约300-400℃的温度氧化等离子膜形成的时侯或者发生在大约400-450℃温度钨膜层形成的时侯。尤其，Si-H键在400℃或更高温度时大大减少。因而，Si-H键数目在加工过程中使用最高温度的钨膜形成条件下大大减少，因而，这一加工过程导致线容大大增加。
本发明的一个目标在于提供一种半导体装置制造方法，能够制造既使在小线距时也具有小线容的半导体装置。
根据本发明，获得了一种半导体装置制造方法，该方法由在线层上形成包含HSQ膜层的绝缘夹层的步骤组成，其中把氢离子植入HSQ膜层，并使半导体装置低温退火。
再者，根据本发明，获得了一种半导体装置制造方法，该方法还由在绝缘夹层膜上形成通路孔和在通路孔中嵌入钨膜层的步骤组成，其中离子植入步骤和低温退火步骤在钨嵌入步骤之后进行。
更进一步，根据本发明，获得了一种半导体装置制造方法，其中低温退火步骤在包含氢气的氛围中进行。
根据上述方法，氢气被充填入HSQ，其中Si-H键数目由于一些Si-H键被破坏而减少。破坏了的Si-H键被重新建立，因而Si-H键的数目再次增加。所以，HSQ介电常数再次降低，线容被减少，从而实现了高运行速度和低电源消耗的结果。
本发明的上述和其它目标，优点及特征将通过对相应附图进行的下列描述而更明确，即：
图1A和1B是本发明第一实施例半导体装置加工方法的剖面图。
图2A和2B是本发明第一实施例半导体装置加工方法剖面图。
图3A和3B是本发明第一实施例半导体装置加工方法剖面图。
图4是比较本发明第一实施例与传统方法的HSQ膜层介电常数的示意图；
图5A和5B是本发明第二实施例半导体装置加工方法的剖面图。
图6A和6B是本发明第二实施例半导体装置加工方法的剖面图。
图7A和7B是一个传统例子的半导体装置加工方法剖面图；并且
图8A和8B是一个传统例子半导体装置加工方法剖面图。
第一实施例
如图1A中所示，由厚度约为30nm的钛膜层和厚度约为100nm的氮化钛膜组成的第1耐火金属膜层2，由具有约0.5微米厚度的AlCu膜组成的第1金属膜层3，以及用于防止光刻工艺中的反射，由厚度约为50nm的氮化钛膜层组成的第1防反射膜层4在第1绝缘夹层1上通过溅射方法从底层按顺序形成，这里的第1绝缘夹层1由厚度约为0.8微米的BPSG膜层组成。在这种情况下，第1耐火金属膜层2和第1防反射膜层4在大约150-300℃的温度时形成，而第1金属膜层3在约100-400℃温度时形成。然后，通过光刻工艺和反应离子蚀刻形成图案从而形成由第1耐火金属膜层2，第1金属膜层3以及第1防反射膜层4组成的第1线层。此后，通过等离子CVD方法使用SiH4和NH2在约300-400℃时的混合气体形成厚度约为50nm的第1氧化等离子膜层5。氧化等离子膜层5的形成以改善后面要形成的HSQ膜层与第1线层之间的粘合性。HSQ被涂在第1线层上使得所形成的HSQ膜层具有大约0.4微米的厚度。接着，分别在150，200和350℃的温度烘烤1分钟并且在400℃时在氮气氛围中进一步烘烤60分钟以形成HSQ膜层6作为一个绝缘夹层。再者，厚度约为1.4微米的第2氧化等离子膜层7通过等离子CVD方法在300-400℃时在HSQ膜层6上形成。至少通过化学抛光或机械抛光使得HSQ膜层6和第2氧化等离子膜层7的总厚度在第1线层上成为约0.8微米。因为HSQ膜层是一个涂层，该膜层本身的厚度作为绝缘夹层来说是不够的。同时，当HSQ膜层曝露于磨蚀溶液或清洗溶液中时，其质量会下降。因此，在本实施例中，第2氧化等离子膜层7在HSQ膜层6上形成以达到为获得足够的平面表面所需的充足数量的CMP。
随后，如图1B中所示，第1通路孔8通过光刻工艺和反应离子蚀刻形成。接着，在约150-300℃时，通过溅射法，形成由厚度约为30nm的钛膜层和厚度约为100nm的氮化钛膜层组成的第2耐火金属层9。再者，使用WF6或类似材料作为气体源，通过CVD方法，在400-450℃温度时使钨沉积至约0.5微米的厚度，并且随之通过逆向蚀刻使钨层仅仅留存于第1通路孔8中以形成第1钨膜层10。然后，厚度约为0.5微米的AlCu膜层组成的第2金属层11以及厚度约为50nm的氮化钛膜层组成的第2防反射膜层12通过溅射方法在整个表面上形成，这一溅射法与第1金属膜层3和第1防反射膜层4的情况类似。随后，通过光刻工艺和反应离子蚀刻来形成图案从而形成由第2耐火金属膜层9，第2金属膜层11以及第2防反射膜层12组成的第2线层。
随后，如图2A中所示，在50KeV的能量时，使用约1×10-16/cm2的剂量把氢离子13植入。接着，在约400℃时，实施低温退火约10分钟。在这种情况下，最好使用比率为1∶1的氢与氮的混合气体作为退火气体氛围。按照上述处理，由前面主要是在形成钨膜层10时进行热处理所破坏的Si-H键被重新建立以降低被增加了的电介电常数。
接着，如图2B中所示，厚度约为50nm的第3氧化等离子膜层14通过等离子CVD方法，使用Si-H和NH2混合气体，在约300-400℃温度时形成。随后，通过采用与HSQ膜层6相似的方法涂HSQ涂层并进行烘烤，在第2线层上形成HSQ膜层15，以达到大约0.4微米的厚度。然后，通过等离子CVD方法，在膜层15上形成厚度约为1.4微米的第4氧化等离子膜层16。这时，至少在第2线层上的第4氧化等离子膜层16上应用化学抛光或机械抛光使得HSQ膜层15和第4氧化等离子膜层16的总厚度约为0.8微米。
此后，通过光刻工艺和反应离子蚀刻形成第2通路孔17。由厚度约为30nm的钛膜层和厚度约为100nm的氮化钛膜层组成的第3耐火金属层18通过溅射方法在第2通路孔17中形成。再者，通过使用WF6或类似材料作为气体源的CVD方法在400-450℃时使钨沉积至约0.5微米的厚度，并且随之通过逆向蚀刻工艺仅仅使钨在第2通路孔17中留存，以形成钨膜层100。接着，由厚度约为0.5微米的AlCu膜层组成的第3金属层19以及由厚度约为50nm的氮化钛膜层组成的第3防反射膜层20通过溅射法在整个表面上形成。然后，通过光刻工艺和反应离子蚀刻来形成图案从而形成由第3耐火金属膜层18，第3金属膜层19以及第3防反射膜层20组成的第3线层。
然后，如图3A中所示，在50KeV的能量时，使用约1×10-16/cm2的剂量把氢离子21植入。接着，在约400℃时实施低温退火约10分钟。在这种情况下，最好使用比率为1∶1的氢与氮的混合气体作为退火气体氛围。根据这一离子植入和退火处理，由主要在第2钨膜层100形成时被破坏的HSQ膜层15和6中的Si-H键被重新建立并且有可能降低HSQ膜层15和6的介电常数。
然后，如图3B中所示，形成由厚度约为0.8微米的氧化等离子膜层和厚度约为0.3微米的SiON等离子膜层的覆膜层22。与第1和第2线层不同，HSQ膜层不是在第3线层上形成。这是因为最顶层的线层通常仅作为具有大线距的电源线或地线，因此，有一点线容不成其问题。所以，当线容成为问题时，最好也在这一线层上使用HSQ膜层。
在上述本发明第一实施例的情况中，HSQ膜层6形成，接着，第2线层在膜层6上形成并且在此后，氢离子13被植入，然后，进行低温退火。因此，在HSQ膜层6中，由于高温热处理，尤其是由于嵌入第1通路孔8的钨膜层10的形成所破坏的Si-H键被重新建立，已升高的介电常数再次降低。类似地，HSQ膜层15形成，接着第3线层在膜层15上形成，此后，氢离子21被植入，然后，进行低温退火。因此，在HSQ膜层15中，由于嵌入第2通路孔17的钨膜层100的形成所破坏的Si-H键被重新建立，已升高的介电常数被再次降低。在这种情况下，在HSQ膜层6中，因形成钨膜层100所破坏的Si-H键同时被重新建立并且降低了介电常数。
上述结果通过参考图4作以下说明。图4是一个比较第1实施例HSQ膜层和图7和图8中所示传统实施例介电常数的说明图。图4中，在传统实施例的情况下，可看到第1线层和第2线层之间的HSQ膜层6的介电常数由于HSQ膜层所经历的热处理过程被极大地增加了。当覆膜层22最终形成时，介电常数升至约3.7。同时，第2与第3线层之间HSQ膜层15的介电常数升至大约3.4。然而本发明第1实施例的情况下，HSQ膜层6和15的介电常数被保持在约3.1。
在本实施例中，氢离子在形成一个线层后被植入。这是因为钨层10和100通过在耐火金属膜层上形成钨膜层并随之通过逆向蚀刻在通路孔中留下钨膜的方法而形成。也就是说，在上述方法的情况下，在形成钨膜层10和100之后，氧化等离子膜7和16的整个表面立即被耐火金属膜层9和18所覆盖。因而，既使氢离子在上述状态下被植入，也很难达到HSQ膜层6和15。所以离子在线层图案形成后被植入。
然而，氢离子植入和低温退火可以在热处理过程中进行或在形成钨膜层后的任何时间里进行。例如，如果氧化膜层6和17的上面一侧是裸露的，不用通过逆向蚀刻而用CMP方法在通路孔中嵌入钨膜层10和100时，则有可能在膜层10和100形成后立即实施膜层10和100的嵌入。
第二实施例
在图5A，5B和6A，6B中，与第1实施例相同的那些部分给出与图1至图4中相同的表示符号。
首先，图5A表示一种状态，其中直到第2线层使用与图1A和1B所示第1实施例中相同的加工工艺形成并且这一步的加工工艺的描述被略去。
然后，如图5B中所示，厚度约为50nm的第3氧化等离子膜层14通过使用SH4和NH3的混合气体的等离子CVD方法形成。接着，通过在第2线层上涂HSQ并进行烘烤，在该线层上形成具有大约0.4微米厚度的HSQ膜层15。再者，通过等离子CVD方法在膜层15上形成厚度约为1.4微米的第4氧化等离子膜层16。随后，至少通过对第4等离子膜层16采用化学抛光或机械抛光使得HSQ膜层15和第4氧化等离子膜层16的总厚度在第2线层上成为约0.8微米。
再者，通过光刻工艺和反应离子蚀刻形成第2通路孔17。由厚度约为30nm的钛膜层和厚度约为100微米的氮化钛膜层组成的第3耐火金属膜层18通过溅射方法在第2通路孔17中和第4氧化等离子膜层16上形成。接着，通过使用WF6或同类材料作为气体源的CVD方法使钨沉积至约0.5微米的厚度并随之通过逆向蚀刻工艺使钨仅仅留存于通路孔17中以形成第2钨膜层100，然后，由厚度约为0.5微米的AlCu组成的第3金属膜层19和由厚度约50nm的第3氮化钛膜层20通过溅射法在整个表面上形成。再者，通过光刻工艺和反应离子蚀刻形成图案从而形成由第3耐火金属层18，第3金属层19以及第3氮化钛膜层20组成的第3线层。
接着，如图6A中所示，在100KeV能量时，使用约1×10-16/cm2的剂量把氢离子13植入。在这种情况下，大多数氢离子13被特别地植入第1和第2线层间的HSQ膜层6中。随后，在约400℃的温度时实施低温退火约10分钟。在这种情况下，最好使用比率为1∶1的氢与氮混合气体作为退火气体氛围。
最后，如图6B所示，形成由厚度约为0.8微米的氧化等离子膜层和厚度约为0.3微米的SiON等离子膜层组成的覆膜层22。
在第2实施例的情况中，直到最顶线层(在此实施例中为第2线层)被形成后只进行一次氢离子的植入。因而，第2实施例比第1实施例具有较少的步骤。因为HSQ膜层6通过形成第1和第2钨膜层10和100的步骤，造成了最大的介电常数的增加。然而，由于所采用氢离子植入能量水平比第1实施例中的更高，氢离子被充分地植入HSQ膜层6。因此，有可能再次增加已降低Si-H键的数量。
这样，通过恰当地调节氢离子的植入能量和剂量，既使出现包括有多个HSQ膜层的绝缘夹层被叠合的半导体装置的情况，也有可能通过一次离子植入工艺来重新建立Si-H键。
再者，在第2实施例的情况下，未作与第1实施例类似的在线层图案形成后实施氢离子植入和低温退火的限制。
更进一步，在本发明中，为了补偿HSQ膜层中氢的缺乏，最好使用在氢离子植入之后采用包含氢气的气体作为退火气体氛围。然而，如果使用包含太多氢的气体，HSQ膜层中的Si-O键被破坏，Si-H键则过量增加。结果，HSQ膜层的机械强度被降低并且很容易被剥离，因而，降低了导线的可靠性。因此，在第1和第2实施例中，使用了比率为1∶1作为退火气体氛围的氢和氮混合气体。
再者，在本发明中，质子和氘可被用来代替氢离子。特别地，因为氘比氢离子重，在一定深度的植入范围比氢更容易控制。
本发明的半导体装置制造方法包括形成含有HSQ膜层的绝缘夹层，并在此后，把氢离子植入半导体装置的步骤以及对半导体装置进行低温退火的步骤。因此，有可能制造出既使在小线距情况下，也具有小线容的半导体装置。
也就是说，氢被重新充满于因诸如钨膜层形成时的热处理过程造成一些Si-H键被破坏，因而Si-H键被减少的绝缘夹层中，这样，被破坏的Si-H键被重新建立并且Si-H键的数目被再次增加。因此，HSQ的介电常数再次被降低，线容被减小，从而实现了高速运行及低能耗的结果。
很明显，本发明不限于上述实施例，因而可以在不偏离本发明的范围及原理的情况下进行修改或变更。

Claims (5)

1.一种半导体装置的制造方法，包括步骤：
在一个布线层上形成含有三氧化二硅氢膜层的绝缘夹层；
将氢离子植入所述三氧化二硅氢膜层；
对所述半导体装置进行退火处理；
在所述绝缘夹层中形成通路孔；和
在所述通路孔中嵌入钨膜层，其中：
所述离子植入的步骤和低温退火步骤在所述钨膜嵌入步骤之后执行。
2.根据权利要求1所述的半导体制造方法，其特征在于其中所述形成绝缘夹层的步骤包括在所述布线层表面上形成第1绝缘膜层，在所述第1绝缘膜层上形成所述三氧化二硅氢膜层，在所述三氧化二硅氢膜层上形成第2绝缘膜层，以及至少对所述第2绝缘膜层进行化学抛光或机械抛光等步骤。
3.一种半导体装置的制造方法，包括步骤：
在一个布线层上形成含有三氧化二硅氢膜层的绝缘夹层；
将氢离子植入所述三氧化二硅氢膜层；
对所述半导体装置进行退火处理；
在所述绝缘夹层中形成通路孔；
在所述通路孔里和所述绝缘夹层上形成耐火金属膜层；
在所述通路孔中嵌入钨膜；
在所述耐火金属膜层上形成金属膜层；以及
把所述金属膜和所述耐火金属膜形成布线图案，其中：
所述氢离子植入步骤和所述低温退火步骤在所述图案形成步骤之后执行。
4.一种半导体装置的制造方法，该半导体包括多层布线层和用来使所述各线层间绝缘的多个绝缘夹层，所述各绝缘夹层中具有三氧化二硅氢膜层，所述的方法的步骤包括：
把氢离子植入所述三氧化二硅氢膜层；和
对所述半导体装置进行退火处理，其中所述离子植入步骤和所述低温退火步骤仅在所述最顶层绝缘夹层形成后执行一次。
5.根据权利要求4所述半导体装置制造方法，其特征在于其中通过调节离子植入能量使得氢离子到达所述最底层绝缘夹层。
CNB981205534A 1997-10-23 1998-10-22 制造具有多层布线层的半导体装置的方法 Expired - Fee Related CN1144270C (zh)

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