CN113270397B - 衬底上晶圆级芯片封装光电组件及其组装方法 - Google Patents

衬底上晶圆级芯片封装光电组件及其组装方法 Download PDF

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CN113270397B
CN113270397B CN202110115170.4A CN202110115170A CN113270397B CN 113270397 B CN113270397 B CN 113270397B CN 202110115170 A CN202110115170 A CN 202110115170A CN 113270397 B CN113270397 B CN 113270397B
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CN113270397A (zh
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M·A·塞耶迪
M·菲奥伦蒂诺
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Abstract

本文的示例涉及光电组件。具体地，本文的实施方式涉及通过衬底上晶圆级芯片(CoWoS)封装形成的光电组件。光电组件包括衬底、中介层、以及电子集成电路(EIC)。衬底、中介层、以及EIC中的每一者都包括相对的第一侧和第二侧。EIC被倒装组装到中介层的第一侧，并且EIC组装到其的中介层被倒装组装到衬底的第一侧。注塑层在中介层的第一侧上延伸并且封装EIC。注塑层包括使得中介层的第一侧的区域被暴露出来的腔。光学部件被放置在腔内并且被耦接到中介层的第一侧。

Description

衬底上晶圆级芯片封装光电组件及其组装方法
技术领域
本公开涉及衬底上晶圆级芯片封装光电组件及其组装方法。
背景技术
光电通信(例如，使用光信号发送电子数据)作为一种对于诸如，高性能计算系统、大容量数据存储服务器和网络设备等的应用中对高带宽、高质量和低功耗数据传输的日益增长的需求的至少部分的潜在解决方案变得越来越流行。对于现有的衬底上晶圆级芯片封装方案的改进是提供集成在具有从上到下的光输入/输出附件的中介层上的共封装光电组件所必需的。
发明内容
本公开提供了一种通过衬底上晶圆级芯片CoWos工艺组装光电组件的方法，该方法包括：制造具有穿过衬底通孔TSV的中介层，所述中介层具有相对的第一侧和第二侧；将具有相对的第一侧和第二侧的电子集成电路EIC倒装组装到所述中介层的第一侧；将封装体耦接到所述中介层的第一侧，所述封装体具有盖体和四个侧壁，并且具有比所述电子集成电路的高度更大的高度；将注塑层沉积在所述中介层的第一侧上，所述注塑层密封所述电子集成电路；对所述注塑层进行平坦化，其中，所述封装体的所述盖体在所述注塑层的平坦化期间被移除，所述封装体的所述四个侧壁形成延伸通过所述注塑层并且暴露出所述中介层的第一侧的区域的腔；在所形成的腔内将光学部件耦接到所述中介层的第一侧；以及将所述中介层倒装组装到衬底的第一侧。
附图说明
在下面的详细描述中，参考附图描述某些示例，其中：
图1A-1E示意性地示出了传统的衬底上晶圆级芯片封装流程的示例的各种步骤；
图2A-2F示意性地示出了根据本公开的通过衬底上晶圆级芯片封装形成示例光电组件的各种步骤，并且图2G是光电组件的顶视图；
图3A-3F示意性地示出了根据本公开的通过衬底上晶圆级芯片封装形成另一示例光电组件的各种步骤，并且图3G是光电组件的顶视图；
图4A-4B示意性地示出了根据本公开的光电组件的其他示例的剖视图。
具体实施方式
本公开描述了光电组件及形成光电组件的方法的各种示例。具体地，本文的实施方式涉及通过衬底上晶圆级芯片(CoWoS)封装形成的光电组件。光电组件包括衬底、中介层、以及电子集成电路(EIC)。衬底、中介层、以及EIC中的每一者都包括相对的第一侧和第二侧。EIC被倒装(flip-chip)组装到中介层的第一侧，并且EIC组装到其的中介层被倒装组装到衬底的第一侧。注塑层在中介层的第一侧上延伸并且封装EIC。注塑层包括使得中介层的第一侧的区域被暴露出来的腔。光学部件被放置在腔内并且被耦接到中介层的第一侧。注塑层中的腔暴露出了中介层的第一侧的区域并且被配置为允许通过中介层的第一侧的暴露区域进入或离开光学部件的光输入/输出(I/O)。
中介层可以由硅或者其他具有相对较高折射率的适当材料(例如，GaAs、GaP、GaN、InP)构成。中介层被布置在衬底上或之上。如本文所述，取决于应用，“衬底”可以指代有机堆积衬底、另一中介层、或电路板(例如，PCB)。另外，中介层包括在EIC及其下方的衬底之间形成电通路的穿过衬底通孔(TSV)。
本文描述的“光学部件”可以指代光学插座(例如，以使能光纤卡套附接)、透镜或反射镜、隔离器、或其他光学I/O组件。本文描述的“光纤”可以指代提供单向或双向光通信的单光纤(例如，包括纤芯和包层)，可以指代在光网络中提供发送和接收通信的双向光纤对(例如，每条光纤都包括纤芯和包层)，或者可以指代使得单个包层可以密封多个单模纤芯的多芯光纤。
图1A-1E示出了传统的衬底上晶圆级芯片(CoWoS)封装流程100的示例的各种步骤。如图1A所示，制造具有相对的第一侧和第二侧的中介层102，其中，TSV 104延伸通过该中介层。在图1B中，具有相对的第一侧和第二侧的EIC 106被倒装组装到中介层102的第一侧。使用对应的焊盘和微凸块(例如，回流焊工艺)，EIC 106被动地对齐并耦接到中介层102的第一侧。如图1C所示，非光学透明的注塑层108随后被沉积在中介层102的第一侧上。注塑层108在中介层102的整个或基本上整个第一侧上或上方延伸并且封装EIC 106。注塑层108随后被平坦化并且被固化或硬化(图1D)。注塑层108在后续的封装或其他工艺流程步骤期间向EIC/中介层组件提供结构或机械稳定性。中介层102的第二侧被减薄，以暴露出TSV104和形成在其上的焊块110。EIC 106倒装组装在其上的中介层102随后被倒装组装到衬底112的第一侧(图1E)。如图1E所示，光学IO不能通过中介层102的第一侧实现，因为非光学透明的注塑层108覆盖中介层102的第一侧。
参考图2A-2F，示出了根据本公开的通过CoWoS封装技术形成示例光电组件200的各种步骤。光电组件200可以包括以上针对工艺流程100部分或全部描述的任意特征或步骤。相反，光电组件200包括暴露出中介层202的第一侧的区域的腔220，如下面进一步详细描述的。
如图2A-2B所示，制造具有相对的第一侧和第二侧203和205的中介层202，其中，TSV 204延伸通过该中介层202。在图2B中，具有相对的第一侧和第二侧207和209的EIC 206被倒装组装到中介层202的第一侧203。使用对应的焊盘和微凸块(例如，回流焊工艺)，EIC206被动地对齐并耦接到中介层202的第一侧203。
在图2C中，通过例如拾放工具，使用粘接剂(例如，环氧树脂)将封装体230耦接或附接到中介层202的第一侧203。封装体230可以包括盖体232或罩体和四个侧壁234，并且封装体230具有面朝下或面朝向中介层202的第一侧203的开放侧。封装体230的高度大于EIC206的高度(例如，盖体232在中介层202的第一侧203上方相对于EIC206的第一侧207的更高的位置)。封装体230可以由硅或其他适当材料形成。
如图2D所示，非光学透明的注塑层208被沉积在中介层202的第一侧203之上并且密封EIC 206。注塑层208被固化或硬化。在图2E中，注塑层208被平坦化(例如，通过化学机械抛光)。在注塑层208的平坦化期间，封装体230的盖体232被磨光或移除(例如，因为盖体232比EIC 206高或者处于相对于EIC 206的更高位置)。移除封装体230的盖体232形成了在四个侧上被封装体230的四个侧壁234包围的腔220(图2E-2G)，其中，腔220位于注塑层208中或者通过注塑层208延伸到中介层202的第一侧203。图2G示出了光电组件200的顶视图。如图所示，腔220可以具有由四个侧壁234包围或约束的矩形或正方形横截面构造。除了腔220外，中介层202的其他部分被注塑层208保护或覆盖。
腔220暴露出了中介层202的第一侧203的允许光学I/O从上到下地附接到中介层202的区域(例如，通过第一侧203)。例如，如图2F所示，光学部件240可以被放置在注塑层208的腔220中并被耦接到中介层202的第一侧203。如上所述，光学部件240可以包括但不限于，光学插座(例如，以使能光纤卡套附接)、透镜或反射镜、或隔离器。来自或去往光学部件240的光信号可以通过中介层202的第一侧203进入或退出中介层202的光学层。
中介层202可以包括多个层。例如，中介层202可以包括以下的一个或多个层：包括钝化层和金属化层中的一者或两者的再分布层202a、光学层202b(例如，硅光学层)、埋氧层(buried oxide layer)202c和/或本征层202d(例如，硅本征层)。光学层202b可以包括一个或多个光栅，以将通过光学层202b的光信号重定向离开光学部件240或重定向到光学部件240。另外，如以上针对工艺流程100所述，EIC倒装组装到其且具有暴露区域的中介层202可以被减薄以暴露出TSV 204，并且可以进一步被倒装组装或耦接到衬底212的第一侧(例如，通过对应的焊盘和凸块及回流焊工艺)。
图3A-3F示意性地示出了根据本公开的通过衬底上晶圆级芯片封装形成另一示例光电组件300的各种步骤。光电组件300通过与光电组件200相同或类似的方式形成，并且可以包括以上针对光电组件200总体或部分描述的任意特征或步骤。但是，在对注塑层308进行平坦化并移除盖体332后，四个侧壁334中的某个侧壁可以被劈开或移除。封装体330的其余三个侧壁334形成具有U形横截面构造的腔320(图3G)。通过移除封装体330的外边缘或侧壁334，中介层302的暴露边缘随后可以被蚀刻(例如，在后工艺步骤期间)，以创建用于光纤附接的v形沟槽。如图所示，中介层302的外边缘被暴露出来，以使得中介层302的层边缘可以被访问从而被蚀刻或进行工艺。
图4A-4B分别示意性地示出了根据本公开的光电组件400a和400b的其他示例的剖视图。光电组件400a和400b可以包括以上针对光电组件200和300部分或总体描述的任何特征或步骤。例如，光电组件400a和400b分别示出了具有如以上针对光电组件200和300所述地形成的正方形横截面构造和U形横截面构造的腔420的封装体430。相反，光电组件400a和400b示出了耦接到中介层402的第一侧403的封装体430(没有粘接剂或环氧树脂)。在图4A-4B中，光电组件400a和400b的各个封装体430被使用对应的微凸块和焊垫(例如，回流焊工艺)耦接或附接。在这种实施方式中，封装体430可以与EIC 406同时被耦接到中介层402的第一侧403。在其他实施方式中，形成腔420的封装体430可以在EIC 406之前或之后被耦接到中介层402。
在前面的描述中，阐述了很多细节，以提供对于本文公开的主题的理解。但是，实施方式可以在没有这些细节中的一些或所有细节的条件下实现。其他实施方式可以包括对于以上讨论的细节的添加、修改、或改变。希望所附权利要求覆盖这些修改和改变。相应地，本说明书和附图被认为是说明性而非限制性的。另外，为了清楚并避免不必要地模糊描述，在本公开的各种示例的描述中，没有给出描述通常与光电组件相关联的公知结构和系统(例如，接触焊盘、焊盘之间的痕迹、驱动电路、ASIC、光栅等)的其他细节。
将认识到，本文使用的术语“包括”、“包含”、以及“具有”意图被理解为开放式用语。针对两个或两个以上的项目的列表中的术语“或”覆盖该单词的所有以下解释：该列表中的任意项目、该列表中的所有项目、以及该列表中的项目的任意组合。如本文使用的术语“连接”、“耦接”、或它们的任意变形是指两个或两个以上的元件、节点、或组件之间的任意直接或间接(例如，具有额外的介于之间的组件或元件)连接或耦接；元件之间的耦接或连接可以是物理的、机械的、逻辑的、光学的、电子的、或它们的组合。在附图中，相同的参考标号标识相同或者至少总体上类似的元件。为了方便讨论任意特定元件，任意参考标号的最高有效位指代首次引入该元件的附图。例如，参考图1首次引入并讨论元件110。

Claims (10)

1.一种通过衬底上晶圆级芯片CoWos工艺组装光电组件的方法，该方法包括：
制造具有穿过衬底通孔TSV的中介层，所述中介层具有相对的第一侧和第二侧；
将具有相对的第一侧和第二侧的电子集成电路EIC倒装组装到所述中介层的第一侧；
将封装体耦接到所述中介层的第一侧，所述封装体具有盖体和四个侧壁，并且具有比所述电子集成电路的高度更大的高度；
将注塑层沉积在所述中介层的第一侧上，所述注塑层密封所述电子集成电路；
对所述注塑层进行平坦化，其中，所述封装体的所述盖体在所述注塑层的平坦化期间被移除，所述封装体的所述四个侧壁形成延伸通过所述注塑层并且暴露出所述中介层的第一侧的区域的腔；
在所形成的腔内将光学部件耦接到所述中介层的第一侧；以及
将所述中介层倒装组装到衬底的第一侧。
2.如权利要求1所述的组装光电组件的方法，其中，所述封装体通过利用粘接剂耦接到所述中介层的第一侧。
3.如权利要求1所述的组装光电组件的方法，其中，所述封装体通过回流焊工艺耦接到所述中介层的第一侧。
4.如权利要求1所述的组装光电组件的方法，其中，所述腔具有矩形横截面构造。
5.如权利要求1所述的组装光电组件的方法，还包括：
在移除所述盖体后劈开所述封装体的所述四个侧壁中的一个侧壁，使得所述腔具有U形横截面构造。
6.如权利要求1所述的组装光电组件的方法，其中，所述封装体通过拾放工具被放置在所述中介层的第一侧上。
7.如权利要求1所述的组装光电组件的方法，其中，所述封装体和所述电子集成电路在回流焊工艺期间被同时耦接到所述中介层的第一侧。
8.如权利要求1所述的组装光电组件的方法，其中，在所述注塑层的平坦化之后，所述中介层被倒装组装到所述衬底。
9.如权利要求1所述的组装光电组件的方法，其中，所述电子集成电路和所述中介层的第一侧和第二侧分别是上侧和下侧。
10.如权利要求1所述的组装光电组件的方法，其中，所述穿过衬底通孔从所述中介层的第一侧延伸到所述中介层的第二侧，以将所述电子集成电路耦接到所述衬底的第一侧。
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