CN111123444B - 光学收发器及其制造方法 - Google Patents
光学收发器及其制造方法 Download PDFInfo
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- CN111123444B CN111123444B CN201910083021.7A CN201910083021A CN111123444B CN 111123444 B CN111123444 B CN 111123444B CN 201910083021 A CN201910083021 A CN 201910083021A CN 111123444 B CN111123444 B CN 111123444B
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Abstract
本公开提供一种光学收发器,包含光子集成电路组件、电子集成电路组件以及绝缘密封体。光子集成电路组件包含至少一个光学输入/输出部和位于至少一个光学输入/输出部附近的至少一个凹槽。电子集成电路组件安置于光子集成电路组件上且电性连接到所述光子集成电路组件。绝缘密封体安置于光子集成电路组件上,且横向地包封电子集成电路组件。光子集成电路组件的至少一个凹槽被绝缘密封体暴露出,且适用于插入光子器件。
Description
技术领域
本发明实施例涉及一种光学收发器及其制造方法。
背景技术
光学收发器模块用于要求高性能、紧密封装以及低功耗的高速光通信系统中。光传输/接收功能实施于可插拔(pluggable)光学收发器模块中。光学收发器模块遵从高达大于100Gbps的通信速度范围下的各种国际标准规范。目前,光学收发器模块的制造工艺非常复杂,且其良率增加是必要的。
发明内容
根据本发明的实施例,一种光学收发器,包括光子集成电路组件、电子集成电路组件以及绝缘密封体。光子集成电路组件包括至少一个光学输入/输出部以及位于所述至少一个光学输入/输出部附近的至少一个凹槽。电子集成电路组件安置于所述光子集成电路组件上且电性连接到所述光子集成电路组件。绝缘密封体安置于所述光子集成电路组件上且横向地包封所述电子集成电路组件,其中所述绝缘密封体以及所述光子集成电路组件的所述至少一个凹槽适用于插入光子器件。
根据本发明的实施例,一种制造光学收发器的方法,包括:提供光子集成电路组件,其中所述光子集成电路组件包括至少一个光学输入/输出部以及位于所述至少一个光学输入/输出部附近的至少一个凹槽;使电子集成电路组件与所述光子集成电路组件接合;在所述光子集成电路组件上形成突出部以覆盖所述至少一个凹槽;在所述光子集成电路组件上形成绝缘密封体以横向地包封所述电子集成电路组件以及所述突出部;以及从所述光子集成电路组件去除所述突出部。
根据本发明的实施例,一种制造光学收发器的方法,包括:提供包括多个光子集成电路组件的中介物,且所述多个光子集成电路组件中的每一个包括至少一个光学输入/输出部以及位于所述至少一个光学输入/输出部附近的至少一个凹槽;使多个电子集成电路组件与所述中介物接合;在所述中介物上形成多个突出部,且所述多个突出部填充所述中介物的所述多个凹槽并从所述中介物突出;在所述中介物上形成绝缘密封体以形成结构,其中所述绝缘密封体横向地包封所述多个电子集成电路组件以及所述多个突出部;使所述结构单体化以形成多个单体化光学收发器;以及从所述多个单体化光学收发器去除所述多个突出部。
附图说明
当结合附图阅读时,从以下详细描述最好地理解本公开的方面。应注意,根据业界中的标准惯例,各种特征未按比例绘制。实际上,为了论述清楚起见,可任意增大或减小各种特征的尺寸。
图1到图13说明根据本公开的一些实施例的用于制造光学收发器的工艺流程。
图14A是根据本公开的一些实施例的图13中所说明的光学收发器的示意图。
图14B是根据本公开的一些替代实施例的图13中所说明的光学收发器的示意图。
图15A是根据本公开的一些实施例的示意性地说明图13中示出的区域A 的横截面图。
图15B是根据本公开的一些替代实施例的示意性地说明图13中示出的区域A的横截面图。
图16A是根据本公开的一些实施例的示意性地说明图13中示出的区域B 的横截面图。
图16B是根据本公开的一些替代实施例的示意性地说明图13中示出的区域B的横截面图。
[附图标号说明]
100:光子集成电路组件;
100a:电接合部;
100b:光学输入/输出部;
100c:凹槽;
200:电子集成电路组件;
300a、300b:绝缘密封体;
A、B:区域;
AS1:第一有源表面;
AS2:第二有源表面;
B1、B2:导电凸块;
C1、C2、C3:载体;
C2′:单体化载体;
CS:约束结构;
INT:中介物;
OTC:单体化光学收发器;
P:突出部;
PD:光子器件;
RS1:第一后表面;
RS2:第二后表面;
SUB:布线衬底;
SW1、SW4、SW5、SW5′、SW6、SW6′:弯曲倾斜侧壁;
SW2:侧壁;
SW3:弯曲侧壁;
SW5″、SW6″:垂直侧壁;
UF1、UF2:底填充物;
w1、w3:顶部尺寸;
w2、w4:底部尺寸。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同实施例或实例。下文描述组件和布置的具体实例以简化本公开。当然,这些只是实例且并不意欲为限制性的。举例来说,在以下描述中,第一特征在第二特征上方或上的形成可包含第一特征和第二特征直接接触地形成的实施例,且还可包括额外特征可在第一特征与第二特征之间形成使得第一特征和第二特征可不直接接触的实施例。另外,本公开可在各个实例中重复参考标号和/或字母。这种重复是出于简化和清楚的目的,且本身并不指示所论述的各种实施例和/或配置之间的关系。
此外,为易于描述,可在本文中使用空间相对术语,如“在...下方”、“在... 下”、“下部”、“在...上方”、“上部”以及类似术语,以描述如图式中所说明的一个元件或特征与另一(一些)元件或特征的关系。除图式中所描绘的定向以外,空间相对术语意欲涵盖器件在使用或操作中的不同定向。设备可以其它方式定向(旋转90度或处于其它定向),且本文中所使用的空间相对描述词同样可相应地进行解释。
还可包含其它特征和工艺。举例来说,可包含测试结构以帮助验证测试3D 封装或3D-IC器件。测试结构可包含例如形成于重布线层中或衬底上的测试垫,所述衬底允许测试3D封装或3D-IC、使用探针和/或探针卡以及类似物。可对中间结构以及最终结构执行验证测试。另外,本文中所公开的结构和方法可与并有已知良好管芯的中间验证的测试方法结合使用以增大良率并降低成本。
图1到图13说明根据本公开的一些实施例的用于制造光学收发器的工艺流程。图14A是根据本公开的一些实施例的图13中所说明的光学收发器的示意图。图14B是根据本公开的一些替代实施例的图13中所说明的光学收发器的示意图。
参考图1,提供其中包含多个光子集成电路组件100的中介物INT。光子集成电路组件100以阵列布置,且实体彼此至连接。多个光子集成电路组件100 当中的每一光子集成电路组件100可分别包含:电接合部100a;至少一个光学输入/输出部100b,配置成传输和接收光学信号;以及至少一个凹槽100c,位于所述至少一个光学输入/输出部100b附近。光学信号是例如脉冲光、具有持续波(continuous wave;CW)的光或其组合。在一些实施例中,光子集成电路组件100的电接合部100a可包含半导体器件(例如,晶体管、电容器等等)、用于电性连接的布线或导体,且光子集成电路组件100的光学输入/输出部100b 可包含半导体器件和用于处理光学信号的光学器件(例如,光栅耦合器(grating coupler))。举例来说,形成于光学输入/输出部100b中的半导体器件可包含晶体管、电容器、光电二极管或其组合,且形成于光学输入/输出部100b中的光学器件可包含调制器(modulator)、光栅耦合器、边缘耦合器(edge coupler)、波导、滤波器或其组合。如图1所示,中介物INT可包含第一有源表面AS1和与第一有源表面AS1相对的第一后表面RS1,其中光子集成电路组件100的电接合部100a、光学输入/输出部100b以及凹槽100c形成于中介物INT的第一有源表面AS1处。在一些实施例中,多个凹槽100c可形成于中介物的第一有源表面AS1上,且凹槽100c可以是通过刻蚀或其它合适的工艺形成的V型-凹槽。本公开中并不限制一或多个凹槽的数目。
如图1所示,中介物INT可进一步包含形成于其第一有源表面AS1上的多个导电凸块B1。在一些实施例中,导电凸块B1可以是形成于中介物INT的第一有源表面AS1上的微型凸块(micro-bump)(例如,焊料凸块、铜凸块或其它金属凸块)。举例来说,多组导电凸块B1可形成于中介物INT上,且每组导电凸块B1可分别形成于多个光子集成电路组件100中的一个上。
如图1所示,多个电子集成电路组件200设置且安装到中介物INT上。在一些实施例中,可拾取(pick and place)电子集成电路组件200且将其放置到中介物INT的第一有源表面AS1上,使得电子集成电路组件200可覆盖光子集成电路组件100的电接合部100a,且光子集成电路组件100的光学输入/输出部 100b可不由电子集成电路组件200覆盖或屏蔽。多个电子集成电路组件200中的每一个可分别包含第二有源表面AS2和与第二有源表面AS2相对的第二后表面RS2。在拾取电子集成电路组件200且将其放置到中介物INT上后,电子集成电路组件200的第二有源表面AS2可面向中介物INT,且电子集成电路组件 200可通过多个导电凸块B1与中介物INT接合。举例来说,可执行导电凸块 B1的回焊工艺以便于电子集成电路组件200与中介物INT之间接合。在一些实施例中,电子集成电路组件200的数目可等于包含于中介物INT中的光子集成电路组件100的数目。在一些替代实施例中,电子集成电路组件200的数目可高于包含于中介物INT中的光子集成电路组件100的数目。本公开中并不限制电子集成电路组件200的数目。
在一些实施例中,在执行导电凸块B1的上述回焊工艺后,底填充物UF1 可形成于电子集成电路组件200与中介物INT之间,以便横向地包封导电凸块 B1。底填充物UF1不仅保护导电凸块B1免于疲劳(fatigue),且还增强电子集成电路组件200与中介物INT之间的接合可靠性。在一些替代实施例中,底填充物UF1的形成可省略。
尽管通过由底填充物UF1包封的导电凸块B1来实现电子集成电路组件200 与中介物INT之间的接合和电性连接(图1中所示),但本公开的电子集成电路组件200与中介物INT之间的接合和电性连接不限于此,且可利用其它合适的芯片到晶片(chip-to-wafer)接合工艺(例如,芯片到晶片混合式接合(hybrid bonding)工艺)。
参考图2,在电子集成电路组件200与中介物INT接合后,多个突出部P 形成于中介物INT的第一有源表面AS1上以覆盖多个凹槽100c。突出部P填充凹槽100c,且从中介物INT的第一有源表面AS1突出。凹槽100c可增强中介物INT与突出部P之间的结合力。在一些实施例中,突出部P不仅覆盖凹槽 100c,且还覆盖光学输入/输出部100b的部分,且由突出部P覆盖的光学输入/ 输出部100b的部分位于凹槽100c附近。在一些实施例中,突出部P的数目可等于光子集成电路组件100的光学输入/输出部100b的数目。
如图2中所示,突出部P可具有弯曲倾斜侧壁SW1,且突出部P的弯曲倾斜侧壁SW1位于光学输入/输出部100b上方。突出部P形成为暂时地占用用以插入光子器件PD(如图13中所示)的空间。换句话说,利用突出部P来定义光子器件PD的插入位置。由于形成突出部P以确定和暂时地占用用以插入光子器件PD的空间,因此可根据要插入的光子器件PD的耦合部分的几何形状来在中介物INT上设计和制造突出部P的几何形状。
在一些实施例中,突出部P可通过列印工艺(例如,三维列印工艺)形成于中介物INT上,且突出部P可由印墨或其它合适的介电聚合物(例如,PI、环氧树脂、丙烯酸酯类等等)形成。形成于中介物INT上的突出部P的高度可高于凹槽100c的深度。举例来说,突出部P的高度可介于约40微米到约3000 微米范围内,且凹槽100c的深度可介于约20微米到约1500微米范围内。此外,如图2中所示,在一些实施例中,突出部P的顶部表面低于电子集成电路组件 200的第二后表面RS2。在一些替代实施例中,图中未示,突出部P的顶部表面可大体上与电子集成电路组件200的第二后表面RS2齐平。
参考图3,绝缘密封体300a形成于中介物INT上,以便包封电子集成电路组件200、底填充物UF1以及突出部P。在一些实施例中,绝缘密封体300a可通过包覆模制(over-mold)工艺后接第一研磨工艺而形成。在包覆模制工艺期间,绝缘模制材料形成于中介物INT上,以包封电子集成电路组件200、底填充物UF1以及突出部P,使得不暴露电子集成电路组件200、底填充物UF1以及突出部P。随后,研磨或抛光(即第一研磨工艺)绝缘模制材料直到暴露电子集成电路组件200的第二后表面RS2为止。在执行研磨工艺后,绝缘密封体 300a形成于中介物INT上。如图3中所示,由于突出部P的顶部表面低于电子集成电路组件200的第二后表面RS2,因此在执行第一研磨工艺后,突出部P 不由绝缘密封体300a暴露。绝缘模制材料的第一研磨工艺可以是化学机械抛光 (chemical mechanical polishing;CMP)工艺、机械研磨工艺、其组合或其它合适的工艺。
在一些替代实施例中,图中未示,当突出部P的顶部表面可大体上与电子集成电路组件200的第二后表面RS2齐平时,在执行第一研磨工艺后,突出部 P由绝缘密封体300a暴露。另外,在执行第一研磨工艺后,当突出部P已由绝缘密封体300a暴露时,不需要额外研磨工艺(例如,图7中描述的研磨工艺)。
参考图3和图4,在形成绝缘密封体300a后,将图3中示出的所得结构转移接合到载体C1上,使得电子集成电路组件200的第二后表面RS2和绝缘密封体300a与载体C1接合。在一些实施例中,载体C1可以是半导体晶片(例如,硅晶片)或能够承载图3中所示的所得结构的其它合适衬底。
参考图4和图5,执行薄化工艺以减小中介物INT的厚度。在一些实施例中,可对中介物INT的第一后表面RS1执行研磨或抛光工艺直到暴露光子集成电路组件100的电接合部100a为止。中介物INT的研磨工艺可以是化学机械抛光(CMP)工艺、机械研磨工艺、其组合或其它合适的工艺。
参考图5和图6,在执行中介物INT的薄化工艺后,多个导电凸块B2可形成于中介物INT的第一后表面RS1上。在一些实施例中,形成于中介物INT 的第一后表面RS1上的导电凸块B2可以是可控塌陷芯片连接凸块(C4凸块)。举例来说,多组导电凸块B2可形成于中介物INT的第一后表面RS1上,且每组导电凸块B2可分别形成于多个光子集成电路组件100中的一个上。
参考图6和图7,在中介物INT的第一后表面RS1上形成导电凸块B2后,执行转移接合工艺以将由载体C1承载的所得结构从载体C1转移到另一载体 C2上。在一些实施例中,由载体C1承载的所得结构可转换到载体C2上,使得导电凸块B2和中介物INT的第一后表面RS1与载体C2粘合。随后,执行载体C1的剥离(de-bonding)工艺。举例来说,载体C2可以是与导电凸块B2 和中介物INT的第一后表面RS1粘合的锯带(saw tape),且导电凸块B2可由所述锯带保护。
如图6和图7所示,执行绝缘密封体300a的第二研磨工艺。对绝缘密封体 300a的顶部表面和电子集成电路组件200的第二后表面RS2执行第二研磨工艺直到暴露突出部P为止。在执行绝缘密封体300a的第二研磨工艺后,绝缘密封体300b形成于中介物INT上,以便横向地包封电子集成电路组件200和突出部P。另外,在执行绝缘密封体300a的第二研磨工艺后,电子集成电路组件200 的厚度减小,且突出部P暴露出。
参考图7和图8,沿切割线(scribe line)SL(图7中所示)执行单体化工艺,使得由载体C2承载的所得结构单体化为多个单体化光学收发器OTC,且多个单体化光学收发器OTC中的每一个由单体化载体C2啄载的。如图8所示,多个单体化光学收发器OTC中的每一个可包含至少一个光子集成电路组件 100、至少一个电子集成电路组件200、绝缘密封体300b以及突出部P。至少一个光子集成电路组件100包含至少一个电接合部100a、至少一个光学输入/输出部100b以及位于所述至少一个光学输入/输出部100b附近的至少一个凹槽 100c。另外,电子集成电路组件200安置于光子集成电路组件100的电接合部 100a上且电性连接到所述电接合部。突出部P至少覆盖光子集成电路组件100 的至少一个光学输入/输出部100b的部分。
如图7和图8所示,在单体化工艺期间,切断中介物INT和载体C2,且可去除突出部P的部分。在单体化光学收发器OTC中,可暴露突出部P的至少一个侧壁SW2,且所述至少一个侧壁与光子集成电路组件100的弯曲侧壁SW3 大体上对准。
参考图8和图9,执行转移接合(transfer bonding)工艺以将多个单体化光学收发器OTC中的至少一个从单体化载体C2′转移到载体C3上。在一些实施例中,通过框装(framemount)工艺将由单体化载体C2啄载的至少一个单体化光学收发器OTC安装于载体C3(例如,用于支撑单体化光学收发器OTC的框)上,且随后从单体化光学收发器OTC去除单体化载体C2′,使得单体化光学收发器OTC的导电凸块B2组暴露出。
参考图9和图10,设置布线衬底SUB。通过导电凸块B2组将至少一个单体化光学收发器OTC安装到布线衬底SUB上且电性连接到所述布线衬底。举例来说,可执行导电凸块B2的回焊工艺,以便于至少一个单体化光学收发器 OTC与布线衬底SUB之间的接合。
参考图11,在执行导电凸块B2的上述回焊工艺后,约束结构CS(例如,障壁(dam))可形成于布线衬底SUB上,且约束结构CS可形成于单体化光学收发器OTC的一侧处。在一些实施例中,约束结构CS可从布线衬底SUB向上延伸,且可与突出部P的侧壁SW2和光子集成电路组件100的弯曲侧壁SW3 接触。如图11所示,突出部P的侧壁SW2可部分地由约束结构CS覆盖。举例来说,形成于布线衬底SUB上的约束结构CS的高度可介于约10微米到约 500微米范围内。另外,约束结构CS的底部部分可具有弯曲倾斜侧壁SW4,且约束结构CS的弯曲倾斜侧壁SW4位于凹槽100c下方。
在一些实施例中,约束结构CS可通过列印工艺(例如,三维列印工艺) 形成于布线衬底SUB上,且约束结构CS可由印墨或其它合适的介电材料(例如,PI、环氧树脂、丙烯酸酯类等等)形成。
参考图12,在一些实施例中,底填充物UF2可形成于单体化光学收发器 OTC与布线衬底SUB之间,以便横向地包封导电凸块B2。底填充物UF2的分布由约束结构CS约束。换句话说,约束结构CS附近的底填充物UF2可不横向地超过单体化光学收发器OTC的侧壁(例如,侧壁SW2和侧壁SW3)。底填充物UF2不仅保护导电凸块B2免于疲劳,且还增强单体化光学收发器OTC 与布线衬底SUB之间的接合可靠性。在一些替代实施例中,约束结构CS和底填充物UF2的形成可省略。
参考图12和图13,在形成底填充物UF2后,可去除单体化光学收发器OTC 的约束结构CS和突出部P,使得暴露出光子集成电路组件100的凹槽100c和光学输入/输出部100b的部分。在一些实施例中,通过湿式刻蚀或干式刻蚀来去除约束结构CS和突出部P。
如图13所示,单体化光学收发器OTC包含光子集成电路组件100、电子集成电路组件200以及绝缘密封体300b。光子集成电路组件100至少包含至少一个光学输入/输出部100b和位于所述至少一个光学输入/输出部100b附近的至少一个凹槽100c。电子集成电路组件200安置于光子集成电路组件100上,且电性连接到所述光子集成电路组件。绝缘密封体300b安置于光子集成电路组件 100上,且横向地包封电子集成电路组件200。另外,至少一个光学输入/输出部100b的部分和光子集成电路组件100的至少一个凹槽100c(例如,图14A 或图14B中所说明的V型-凹槽)通过绝缘密封体300b而暴露,且适用于插入至少一个光子器件PD。
在一些实施例中,单体化光学收发器OTC可进一步包含多个导电凸块B1 (例如,微型凸块)和安置于电子集成电路组件200与光子集成电路组件100 之间的底填充物UF1,其中电子集成电路组件200可通过导电凸块B1电性连接到光子集成电路组件100。在一些替代实施例中,单体化光学收发器OTC可进一步包含电子集成电路组件200与光子集成电路组件100之间的混合式接合界面(未示出),其中电子集成电路组件200可通过所述混合式接合界面电性连接到光子集成电路组件100,所述混合式接合界面包含金属对金属 (metal-to-metal)接合界面和介电质对介电质(dielectric-to-dielectric)接合界面。
在一些实施例中,单体化光学收发器OTC可进一步包含导电凸块B2和安置于布线衬底SUB与光子集成电路组件100之间的底填充物UF2,其中光子集成电路组件100通过导电凸块B2电性连接到布线衬底SUB,且导电凸块B2 由底填充物UF2横向地包封。
如图13的区域A所示,在一些实施例中,位于光子集成电路组件100的至少一个光学输入/输出部100b上方的绝缘密封体300b的部分可包含弯曲倾斜侧壁SW5。包含弯曲倾斜侧壁SW5的绝缘密封体300b的部分可位于光子集成电路组件100的至少一个凹槽100c附近。另外,如图13所示,绝缘密封体300b 的所述部分的顶部尺寸w1大于绝缘密封体300b的所述部分的底部尺寸w2。绝缘密封体300b的弯曲倾斜侧壁SW5的轮廓与如图8所示的突出部P的几何形状相关,且可由所述突出部的几何形状确定。换句话说,绝缘密封体300b 的弯曲倾斜侧壁SW5的轮廓与如图8所示的突出部P的弯曲倾斜侧壁SW1相关,且可由所述突出部的弯曲倾斜侧壁确定。
如图13的区域B所示,在一些实施例中,位于光子集成电路组件100的至少一个凹槽100c下方的底填充物UF2的部分可包含弯曲倾斜侧壁SW6。另外,底填充物UF2的所述部分的顶部尺寸w3大于底填充物UF2的部分的底部尺寸w4。底填充物UF2的弯曲倾斜侧壁SW6的轮廓与如图11所示的约束结构CS的几何形状相关,且可由所述约束结构的几何形状确定。换句话说,底填充物UF2的弯曲倾斜侧壁SW6的轮廓与如图11所示的约束结构CS的弯曲倾斜侧壁SW4的轮廓相关,且可由所述约束结构的弯曲倾斜侧壁的轮廓确定。
在一些实施例中,如图14A所示,从光学收发器OTC的顶部视图看,绝缘密封体300b包含多个槽,使得光学输入/输出部100b的部分和多个凹槽100c 由绝缘密封体300b的槽暴露。在一些替代实施例中,如图14B所示,从光学收发器OTC的顶部视图看,绝缘密封体300b并不分布于多个凹槽100c上方,使得光学输入/输出部100b的部分和多个凹槽100c由绝缘密封体300b暴露出。
图15A是根据本公开的一些实施例的示意性地说明图13中示出的区域A 的横截面图。参考图15A,位于光子集成电路组件100的至少一个光学输入/ 输出部100b上方的绝缘密封体300b的部分可包含弯曲倾斜侧壁SW5′,其中绝缘密封体300b的所述部分的顶部尺寸小于绝缘密封体300b的所述部分的底部尺寸。另外,包含弯曲倾斜侧壁SW5′的绝缘密封体300b的部分可位于光子集成电路组件100的至少一个凹槽100c附近。
图15B是根据本公开的一些替代实施例的示意性地说明图13中示出的区域A的横截面图。参考图15B,位于光子集成电路组件100的至少一个光学输入/输出部100b上方的绝缘密封体300b的部分可包含垂直侧壁SW5″,其中绝缘密封体300b的所述部分的顶部尺寸大体上等于绝缘密封体300b的所述部分的底部尺寸。另外,包含垂直倾斜侧壁SW5″的绝缘密封体300b的部分可位于光子集成电路组件100的至少一个凹槽100c附近。
图16A是根据本公开的一些实施例的示意性地说明图13中示出的区域B 的横截面图。参考图16A,位于光子集成电路组件100的至少一个凹槽100c下方的底填充物UF2的部分可包含弯曲倾斜侧壁SW6′,其中底填充物UF2的所述部分的顶部尺寸小于底填充物UF2的所述部分的底部尺寸。弯曲倾斜侧壁 SW6′的顶部端可与光子集成电路组件100的侧壁SW3大体上对准,且弯曲倾斜侧壁SW6′的底部端可横向地超过光子集成电路组件100的侧壁SW3。换句话说,底填充物UF2可横向地略微超过光子集成电路组件100的侧壁SW3。
图16B是根据本公开的一些替代实施例的示意性地说明图13中示出的区域B的横截面图。参考图16B,位于光子集成电路组件100的至少一个凹槽100c 下方的底填充物UF2的部分可包含垂直侧壁SW6″,其中底填充物UF2的所述部分的顶部尺寸大体上等于底填充物UF2的所述部分的底部尺寸。换句话说,光子集成电路组件100的垂直侧壁SW6″可与底填充物UF2的侧壁SW3大体上对准。
不限制且可修改图13中所说明的绝缘密封体300b和底填充物UF2的轮廓或几何形状。在一些实施例中,可将图13中所说明的绝缘密封体300b的轮廓或几何形状修改成图15A或图15B中所说明的绝缘密封体300b的轮廓或几何形状。在一些替代实施例中,可将图13中所说明的底填充物UF2的轮廓或几何形状修改成图16A或图16B中所说明的底填充物UF2的轮廓或几何形状。
光子集成电路组件100的至少一个凹槽100c在如图2到图12中所说明的工艺期间由突出部P保护,光学收发器OTC的制造工艺的良率可相应地增大。此外,由于可通过三维列印形成且可通过刻蚀去除突出部P,因此可降低光学收发器OTC的制造复杂度。
根据本公开的一些实施例,提供一种光学收发器,其包含光子集成电路组件、电子集成电路组件以及绝缘密封体。光子集成电路组件包含至少一个光学输入/输出部和位于所述至少一个光学输入/输出部附近的至少一个凹槽。电子集成电路组件安置于光子集成电路组件上且电性连接到所述光子集成电路组件。绝缘密封体安置于光子集成电路组件上且横向地包封电子集成电路组件,其中光子集成电路组件的至少一个凹槽和绝缘密封体适用于插入光子器件。
在一些实施例中,上述的电子集成电路组件通过多个微凸块来电性连接到所述光子集成电路组件。
在一些实施例中,上述的绝缘密封体的部分位于所述至少一个光学输入/ 输出部的部分上方,所述绝缘密封体的所述部分包括弯曲侧壁,且所述绝缘密封体的所述部分的顶部尺寸大于所述绝缘密封体的所述部分的底部尺寸。
在一些实施例中,上述的绝缘密封体的部分位于所述至少一个光学输入/ 输出部的部分上方,所述绝缘密封体的所述部分包括弯曲侧壁,且所述绝缘密封体的所述部分的顶部尺寸小于所述绝缘密封体的所述部分的底部尺寸。
在一些实施例中,上述的绝缘密封体的部分位于所述至少一个光学输入/ 输出部的部分上方,且所述绝缘密封体的所述部分的顶部尺寸大体上等于所述绝缘密封体的所述部分的底部尺寸。
在一些实施例中,上述的光学收发器进一步包括布线衬底。所述光子集成电路组件安置于所述布线衬底上且电性连接到所述布线衬底。
在一些实施例中,上述的光学收发器进一步包括多个导电凸块以及底填充物。底填充物安置于所述布线衬底与所述光子集成电路组件之间,其中所述光子集成电路组件通过所述多个导电凸块来电性连接到所述布线衬底,且所述多个导电凸块由所述底填充物包封。
在一些实施例中,上述的底填充物的部分位于所述至少一个凹槽下,所述底填充物的所述部分包括弯曲侧壁,且所述底填充物的所述部分的顶部尺寸大于所述底填充物的所述部分的底部尺寸。
在一些实施例中,上述的底填充物的部分位于所述至少一个凹槽下,所述底填充物的所述部分包括弯曲侧壁,且所述底填充物的所述部分的顶部尺寸小于所述底填充物的所述部分的底部尺寸。
在一些实施例中,上述的底填充物的部分位于所述至少一个凹槽下,且所述底填充物的所述部分的顶部尺寸大体上等于所述底填充物的所述部分的底部尺寸。
根据本公开的一些实施例,提供一种制造光学收发器的方法,其包含以下步骤。提供光子集成电路组件,其中所述光子集成电路组件包含至少一个光学输入/输出部和位于所述至少一个光学输入/输出部附近的至少一个凹槽。使电子集成电路组件与光子集成电路组件接合。在光子集成电路组件上形成突出部以覆盖至少一个凹槽。在光子集成电路组件上形成绝缘密封体以横向地包封电子集成电路组件和突出部。从光子集成电路组件去除突出部。
在一些实施例中,上述的在所述光子集成电路组件上形成所述绝缘密封体包括:在所述光子集成电路组件上形成绝缘材料以覆盖所述电子集成电路组件以及所述突出部;执行第一研磨工艺以部分地去除所述绝缘材料从而暴露所述电子集成电路组件;以及在执行所述第一研磨工艺后,执行第二研磨工艺以部分地去除所述绝缘材料且减小所述电子集成电路组件的厚度从而暴露所述突出部。
在一些实施例中,上述的方法进一步包括:在执行所述第一研磨工艺后以及在执行所述第二研磨工艺前,在所述光子集成电路组件上形成多个导电凸块,其中所述电子集成电路组件以及所述突出部形成于所述光子集成电路组件的第一表面上,所述多个导电凸块形成于所述光子集成电路组件的第二表面上,且所述第一表面与第二表面相对。
在一些实施例中,上述的方法进一步包括:通过所述多个导电凸块将所述光子集成电路组件电性连接到布线衬底;以及在所述布线衬底与所述光子集成电路组件之间形成底填充物以横向地包封所述多个导电凸块。
在一些实施例中,上述的方法进一步包括:在通过所述多个导电凸块将所述光子集成电路组件电性连接到所述布线衬底后以及在形成所述底填充物前,在所述布线衬底上形成约束结构以约束所述底填充物的分布;以及在形成所述底填充物后,去除所述约束结构。
根据本公开的一些实施例,提供一种制造光学收发器的方法,其包含以下步骤。提供包括多个光子集成电路组件的中介物,其中所述多个光子集成电路组件中的每一个包含至少一个光学输入/输出部和位于所述至少一个光学输入/ 输出部附近的至少一个凹槽。使多个电子集成电路组件与中介物接合。多个突出部形成于中介物上,其中多个突出部填充中介物的多个凹槽且从中介物突出。在中介物上形成绝缘密封体以形成结构,其中绝缘密封体横向地包封电子集成电路组件和多个突出部。使所述结构单体化以形成多个单体化光学收发器。从多个单体化光学收发器去除多个突出部。
在一些实施例中,上述的在所述中介物上形成所述绝缘密封体包括:在所述中介物上形成绝缘材料以覆盖所述多个电子集成电路组件以及所述多个突出部;执行第一研磨工艺以部分地去除所述绝缘材料从而暴露所述多个电子集成电路组件;以及在执行所述第一研磨工艺后,执行第二研磨工艺以部分地去除所述绝缘材料且减小所述多个电子集成电路组件的厚度从而暴露所述多个突出部。
在一些实施例中,上述的方法进一步包括:在执行所述第一研磨工艺后以及在执行所述第二研磨工艺前,在所述中介物上形成多个导电凸块,其中所述多个电子集成电路组件以及所述多个突出部形成于所述中介物的第一表面上,所述多个导电凸块形成于所述中介物的第二表面上,且所述第一表面与第二表面相对。
在一些实施例中,上述的方法进一步包括:通过所述多个导电凸块将所述多个单体化光学收发器中的至少一个电性连接到布线衬底;以及在所述布线衬底与所述多个单体化光学收发器中的所述至少一个之间形成底填充物以横向地包封所述多个导电凸块。
在一些实施例中,上述的方法进一步包括:在通过所述多个导电凸块将所述多个单体化光学收发器中的所述至少一个电性连接到所述布线衬底后以及在形成所述底填充物前,在所述布线衬底上形成约束结构以约束所述底填充物的分布;以及在形成所述底填充物后,去除所述约束结构。
前文概述若干实施例的特征以使得本领域的技术人员可更好地理解本公开的各方面。本领域的技术人员应了解,其可以易于使用本公开作为设计或修改用于进行本文中所引入的实施例的相同目的和/或获得相同优势的其它工艺和结构的基础。本领域的技术人员还应认识到,此类等效构造并不脱离本发明的精神和范围,且其可在不脱离本公开的精神和范围的情况下在本文中进行各种改变、替代和更改。
Claims (10)
1.一种制造光学收发器的方法,其特征在于,包括:
提供光子集成电路组件,其中所述光子集成电路组件包括至少一个光学输入/输出部,其中所述光子集成电路组件具有位于所述至少一个光学输入/输出部附近的至少一个凹槽;
使电子集成电路组件与所述光子集成电路组件电性连接;
在所述光子集成电路组件上形成突出部以覆盖所述至少一个凹槽以及所述至少一个光学输入/输出部的部分,且由所述突出部覆盖的所述至少一个光学输入/输出部的所述部分位在所述至少一个凹槽附近;
在所述光子集成电路组件上形成绝缘密封体以横向地包封所述电子集成电路组件以及所述突出部;以及
从所述光子集成电路组件去除所述突出部。
2.根据权利要求1所述的制造光学收发器的方法,其中在所述光子集成电路组件上形成所述绝缘密封体包括:
在所述光子集成电路组件上形成绝缘材料以覆盖所述电子集成电路组件以及所述突出部;
执行第一研磨工艺以部分地去除所述绝缘材料从而暴露所述电子集成电路组件;以及
在执行所述第一研磨工艺后,执行第二研磨工艺以部分地去除所述绝缘材料且减小所述电子集成电路组件的厚度从而暴露所述突出部。
3.根据权利要求2所述的制造光学收发器的方法,其特征在于,进一步包括:
在执行所述第一研磨工艺后以及在执行所述第二研磨工艺前,在所述光子集成电路组件上形成多个导电凸块,其中所述电子集成电路组件以及所述突出部形成于所述光子集成电路组件的第一表面上,所述多个导电凸块形成于所述光子集成电路组件的第二表面上,且所述第一表面与第二表面相对。
4.根据权利要求3所述的制造光学收发器的方法,其特征在于,进一步包括:
通过所述多个导电凸块将所述光子集成电路组件电性连接到布线衬底;以及
在所述布线衬底与所述光子集成电路组件之间形成底填充物以横向地包封所述多个导电凸块。
5.根据权利要求4所述的制造光学收发器的方法,其特征在于,进一步包括:
在通过所述多个导电凸块将所述光子集成电路组件电性连接到所述布线衬底后以及在形成所述底填充物前,在所述布线衬底上形成约束结构以约束所述底填充物的分布;以及
在形成所述底填充物后,去除所述约束结构。
6.一种制造光学收发器的方法,其特征在于,包括:
提供包括多个光子集成电路组件的中介物,且所述多个光子集成电路组件中的每一个包括至少一个光学输入/输出部,其中所述多个光子集成电路组件中的每一个具有位于所述至少一个光学输入/输出部附近的至少一个凹槽;
使多个电子集成电路组件与所述中介物电性连接;
在所述中介物上形成多个突出部,且所述多个突出部填充所述多个光子集成电路组件中的每一个的所述至少一个凹槽的每一个并从所述中介物突出;
在所述中介物上形成绝缘密封体以形成结构,其中所述绝缘密封体横向地包封所述多个电子集成电路组件以及所述多个突出部;
使所述结构单体化以形成多个单体化光学收发器;以及
从所述多个单体化光学收发器去除所述多个突出部。
7.根据权利要求6所述的制造光学收发器的方法,其中在所述中介物上形成所述绝缘密封体包括:
在所述中介物上形成绝缘材料以覆盖所述多个电子集成电路组件以及所述多个突出部;
执行第一研磨工艺以部分地去除所述绝缘材料从而暴露所述多个电子集成电路组件;以及
在执行所述第一研磨工艺后,执行第二研磨工艺以部分地去除所述绝缘材料且减小所述多个电子集成电路组件的厚度从而暴露所述多个突出部。
8.根据权利要求7所述的制造光学收发器的方法,进一步包括:
在执行所述第一研磨工艺后以及在执行所述第二研磨工艺前,在所述中介物上形成多个导电凸块,其中所述多个电子集成电路组件以及所述多个突出部形成于所述中介物的第一表面上,所述多个导电凸块形成于所述中介物的第二表面上,且所述第一表面与第二表面相对。
9.根据权利要求8所述的制造光学收发器的方法,进一步包括:
通过所述多个导电凸块将所述多个单体化光学收发器中的至少一个电性连接到布线衬底;以及
在所述布线衬底与所述多个单体化光学收发器中的所述至少一个之间形成底填充物以横向地包封所述多个导电凸块。
10.根据权利要求9所述的制造光学收发器的方法,进一步包括:
在通过所述多个导电凸块将所述多个单体化光学收发器中的所述至少一个电性连接到所述布线衬底后以及在形成所述底填充物前,在所述布线衬底上形成约束结构以约束所述底填充物的分布;以及
在形成所述底填充物后,去除所述约束结构。
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