CN1123957A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN1123957A
CN1123957A CN95115080A CN95115080A CN1123957A CN 1123957 A CN1123957 A CN 1123957A CN 95115080 A CN95115080 A CN 95115080A CN 95115080 A CN95115080 A CN 95115080A CN 1123957 A CN1123957 A CN 1123957A
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赵炳珍
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SK Hynix Inc
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Abstract

本发明的半导体器件是这样形成的：形成T形栅极；在T形栅极两侧下方的潜挖部位形成与T形栅极容性耦合的辅助栅极；利用掺杂氧化膜在硅衬底中辅助栅极之下形成轻掺杂区；并形成连至轻掺杂区的重掺杂区。
因此，本发明可形成高速集成电路器件所需的短沟道长度，并通过降低LDD结构的轻掺杂区的沟道电阻，大大提高器件的工作速度。

Description

半导体器件及其制造方法
本发明涉及一种半导体器件及其制造方法，更具体地讲是涉及一种具有超高速集成电路器件所要求的短沟道长度和高电流驱动能力的半导体器件。
对于诸如千兆的DRAM之类的超高速集成电路器件而言，要求MOS晶体管具有0.1μm以下的沟道长度。为满足这种要求，栅极宽度应等于沟道长度。但是，通过现有的I线(I-Line)分步器或准分子激光刻图技术不可能形成具有0.1μm的尺寸的图形。此外，LDD(轻掺杂漏极)结构的轻掺杂区(n-区或P-区)要求0.01-0.03μm的极浅结深度。在半导体器件工作时，浅结突然增大了沟道区的串联电阻，由此降低了电流驱动能力。另外，也降低了器件的工作速度。
因此，本发明的目的是要提供一种半导体器件及其制造方法，它可形成高速集成电路器件所需的短沟道长度，减小LDD结构中的轻掺杂区的沟道电阻，从而提高器件的工作速度。
为实现上述目的，根据本发明的半导体器件包括具有栅极及LDD结构的源和漏区的半导体器，其中还形成有辅助栅极，它们对轻掺杂区是电悬浮的，以便在电学上控制轻掺杂区的电阻。
根据本发明的制造半导体器件的方法包括下列各步骤：
在硅衬底上形成栅氧化膜和T形栅极；在包括T形栅极在内的硅衬底的整体结构的顶部依次形成掺杂氧化膜和厚的多晶硅层，然后，通过采用敷层蚀刻方法蚀刻多晶硅层和掺杂氧化膜而在T形栅极两侧下面潜挖的部分处形成辅助栅极；通过高浓度杂质注入方法在T形栅极两侧的硅衬底中形成重掺杂区；以及在包括T形栅极在内的硅衬底的整体结构上淀积中间绝缘层之后进行为表面平整而采取的热处理，并通过在热处理过程中掺杂氧化膜中所含的掺杂剂向硅衬底的扩散形成轻掺杂区。
为更好地理想本发明的本质和目的，下面将结合附图做详细描述，附图中：
图1是根据本发明制造的半导体器件的剖面图；
图2A-2F是半导体器件的剖面图，用于描绘根据本发明的第一实施例的制造半导体器件的各步骤；
图3A-3E是半导体器件的剖面图，用于描绘根据本发明的第二实施例的制造半导体器件的各步骤；
在各图中相同参考符号表示相同部分。
参照图1，在硅衬底1上形成有具有很小宽度的栅氧化膜10。在栅氧化膜10上形成具有垂直部分20A和水平部分20B的T形栅极20。在水平部分20B的底表面、垂直部分20A的表面以及硅衬底的选择部分上形成掺杂的或非掺杂的氧化膜30。在T形栅极20的潜挖部位的氧化膜30上形成有辅助栅极40，以使辅助栅极40电容性耦合至T形栅极20并与轻掺杂区50电悬浮。轻掺杂区50在辅助栅极40之下的硅衬底1中具有浅的深度，重掺杂区60连至轻掺杂区50。因此，LDD结构的源和漏区70由轻掺杂区50和重掺杂区60组成，由此形成一个存储单元。在包括存储单元在内的硅衬底1的整体结构上形成中间绝缘膜3。由金属接触工艺形成的金属布线4连接至T形栅极20和源及漏区70。
图2A-2F是显示根据本发明的第一实施例的制造具有上述结构的半导体器件的步骤的剖面图。
参照图2A，在硅衬底1上形成一个场氧化膜2，以限定一有源区。在整体结构上形成栅氧化膜10。在栅氧化膜10上依次形成掺杂的多晶硅层20A和未掺杂的多晶硅层20B。依次进行使用一栅极掩模的干法蚀刻工艺和湿法蚀刻工艺，从而形成具有潜挖部位的T形栅极20。通过清洗工艺除去栅氧化膜10的暴露部分。
在制造本发明的有NMOS结构的半导体器件的情况下，T形栅极20是连续地淀积掺有n-型杂质的硅和非掺杂的硅形成的，淀积条件是：在600℃下淀积非晶硅，以抑制掺杂物从掺杂硅层扩散至非掺杂硅层，经栅极掩模操作，通过现有曝光系统的I线分步器和准分子激光刻图使非掺杂硅层和掺杂硅层构成图形，此后，在600-750℃范围内通过0.5-5小时热处理激活掺杂硅层中的杂质，同时，在杂质不致扩散至非掺杂层的条件下使掺杂层多晶化，并在组分比为HNO3∶CH3COOH∶HF∶H2O＝21∶3∶0.25-1.0∶10-16的聚湿性蚀刻溶液中进行蚀刻处理。在采用曝光系统将多晶栅极刻成0.25-0.3μm的厚度的图形情况下，由于在聚湿性蚀刻溶液中掺杂多晶硅20A与非掺杂多晶硅20B的蚀刻比率为60-80∶1，这是一个很大的比值，因此，可以在保持上层非掺杂多晶层20B具有0.25-0.3μm的宽度的情况下，制备具有0.05-0.1μm的很小宽度的下层掺杂多晶硅层20A。
在制造本发明的有PMOS结构的半导体器件的情况下，制造工艺之差异仅在于以P型杂质替代n型杂质。
在上述工艺中，Sb.P和As等用作n型杂质，而硼(B)用作P型杂质。
图2B示出在包括T形栅极20在内的硅衬底1的整体表面上淀积形成薄的掺杂氧化膜30A。
掺杂氧化膜30A的厚度大致为100-200，对于NMOS结构而言，它是通过淀积PSG形成的，对于PMOS结构而言，它是通过淀积BSG或BPSG形成的。
图2C示出在掺杂氧化膜30上形成厚的多晶硅层40A。
多晶硅层40A的厚度大约为1000-2000，并可在不掺杂条件下形成，但是，对于NMOS结构最好采用n+型多晶硅，对于PMOS结构最好采用P+型多晶硅。
图2D示出通过依次蚀刻多晶硅层40A和掺杂氧化膜30A，在T形栅极20的潜挖部位形成辅助栅极40。
由于辅助栅极40通过掺杂的氧化膜30A而悬浮于T形栅极20和硅衬底1，因此它与T形栅极是电容耦合的。
图2E示出通过高浓度杂质注入工艺，在硅衬底1中形成重掺杂区60。同时，T形栅极20的上层即非掺杂的多晶硅层20B，通过此高浓度杂质注入工艺而转变成掺杂的多晶硅层20BB。
在杂质注入过程中，通过注入高浓度的As离子(对于NMOS结构)或硼(B)离子(对于PMOS结构)，重掺杂区60变成n+区或P+区。
图2F示出在包括T形栅极20在内的硅衬底1的整体结构上形成中间绝缘膜3，并在形成中间绝缘膜3时，通过栅极40之下的掺杂氧化膜部位30A所含的掺杂剂向硅衬底1的扩散而形成了与重掺杂区60相连的轻掺杂区50。
中间绝缘膜3通常是在淀积TEOS和BPSG之后，通过为平面化而进行的热处理工艺形成的。在用于形成中间绝缘膜3的热处理过程中，通过含在辅助栅极40之下的掺杂氧化膜部位30中的掺杂剂向硅衬底1的扩散，而形成了轻掺杂区50。也就是说，由于掺杂的氧化膜30A在NMOS情况下由PSG构成，而在PMOS情况下由BSG或BPSG构成，在为平面化而进行的热处理过程中，含在PSG中的P或含在BSG和BPSG中的B会使轻掺杂区50变成n-区或P-区。
此后，通过金属接触工艺形成如图1所示的分别连至T形栅极20以及源和漏区70的金属布线4，这样便制成了本发明的半导体器件。
图3A-3E是描绘根据本发明的第二实施例的制造半导体器件的各步骤的剖面图。
图3A示出在硅衬底1的表面上形成轻掺杂区50，这是通过与图2A所示工艺相同的工艺固相扩散形成的，在包括T形栅极20在内的衬底1的整体结构的顶部淀积厚的掺杂氧化膜100，其厚度在1000-2000的量级，并在820-900℃温度下热处理。
同时，作为T形栅极20的上层的非掺杂多晶硅层20B，由于掺杂剂从作为下层的掺杂多晶硅20A的扩散，而转变成掺杂的多晶硅层20BB。
掺杂的氧化膜100由PSG、BSG或BPSG构成，PSG、BSG或BPSG为制造半导体器件的工艺中所用的绝缘材料。在以NMOS结构制造本发明的半导体器件的情况下，掺杂的氧化膜100通过淀积PSG形成，通过含在PSG中的P的扩散形成的轻掺杂区50变成n-区。在以PMOS结构制造本发明的半导体器件的情况下，掺杂的氧化膜100通过淀积BSG或BPSG形成，通过含有BSG或BPSG中的硼(B)的扩散形成的轻掺杂区50变成P-区。
图3B示出在除去掺杂的氧化层100之后，在包括T形栅极20在内的硅衬底1的整体结构上淀积薄的非掺杂氧化膜30B。
非掺杂氧化膜30B由MTO(中温氧化物)或ONO(氧化物-氮化物-氧化物)形成，其厚度为100-200A。非掺杂氧化膜30B必须在800℃以下形成，以防止含在轻掺杂区50中的掺杂剂(P或B)的额外扩散。
图3C示出在非掺杂氧化膜30B的顶部形成厚的多晶硅层40A。
多晶硅层40A形成1000-2000的厚度，虽然它可在非掺杂状态下形成，但对于NMOS结构采用n-多晶硅，对于PMOS结构采用p-多晶硅。
图3D示出的T形栅极20的潜控部位形成辅助栅极40，这是通过敷层蚀刻工艺依次蚀刻多晶硅层40A和非掺杂氧化膜30B实现的。
由于辅助栅极40与T形栅极20和硅衬底1之间有非掺杂的氧化膜30B，辅助栅极40对T形栅极20和硅衬底1是电悬浮的，因而实现了它们间的电容性耦合。
图3E示出通过高浓度杂质注入工艺形成重掺杂区60。
在杂质注入工艺中，通过注入P、As的离子(在NMOS结构情况下)或B的离子(在PMOS结构情况下)，重掺杂区60变成n+区或P+区。
此后，通过金属接触工艺形成图1中所示的分别连至T形栅极20以及源和漏区70的金属布线4，这样便形成了本发明的半导体器件。
虽然第一和第二实施例描述了制造NMOS和PMOS结构的步骤，但采用本发明的上述原理也可制备CMOS器件。
采用上述方法制造半导体器件具有以下效果：
1)即使采用现有的I线分步器或准分子激光刻图技术，也可形成具有小于0.1μm的沟道长度的千兆级的DRAM晶体管。
2)栅极的上部宽度大，由此可降低接触电阻，而栅极的下部宽度小，由此可增强短沟道效应，从而可提高器件的工作速度。
3)通过形成耦合的多晶硅辅助栅极，可增加轻掺杂区的载流子浓度，在此处沟道串联电阻大为降低，从而增强了电流驱动能力。
4)在漏区边缘因轻掺杂区载流子的积累所产生峰值横向电场的区域，由于采用了耦合的多晶硅辅助栅极而移至真正的沟道中，因此由热载流子引起的间隔诱发变劣(spacer-induced-degradation)现象得以消除，从而可提高器件可靠性。
5)由于采用耦合的多晶硅辅助栅极降低了轻掺杂区的电阻，器件的工作不受进一步降低物理掺杂和结深度的影响，因此可大大改善极点0.1μm级器件的短沟道效应。
虽然已在其优选实施例中对本发明做了一定详细程度的说明，但本领域的技术人员可以理解，这里公开的优选实施例只是一个例子，在不脱离本发明的精神和范围的情况下，本发明的各组成部分的构造，组合及排列关系是可以改变的。

Claims (15)

1.一种半导体器件，具有栅极以及LDD结构的源和漏区，其中形成有辅助栅极，这些辅助栅极电性悬浮于轻掺杂区，在电学上控制所述轻掺杂区的电阻。
2.根据权利要求1的半导体器件，其中所述辅助栅极形成在T形栅极两侧下方的潜挖部位。
3.根据权利要求1的半导体器件，其中以PSG、BSG、BPSG、MTO和ONO中的一种形成一层薄的氧化膜。
5.根据权利要求3的半导体器件，其中所述的掺杂氧化膜形成100-200的厚度。
6.一种制造半导体器件的方法，包括以下步骤：
在硅衬底上形成栅氧化膜和T形栅极；
在包括所述的T形栅极在内的所述硅衬底的整体结构上依次形成薄的掺杂氧化膜和厚的多晶硅层，此后，通过按敷层蚀刻方法蚀刻所述多晶硅层和掺杂氧化膜，在所述T形栅极两侧下方的潜挖部位形成辅助栅极；
通过高浓度杂质注入方法，在所述硅衬底上所述T形栅极两侧形成重掺杂区；和
在包括所述T形栅极在内的所述硅衬底的整体结构上淀积中间绝缘膜之后，为表面平整化进行热处理，且在所述热处理过程中，通过含在所述掺杂氧化膜中的掺杂剂向所述硅衬底的扩散形成轻掺杂区。
7.根据权利要求6的方法，其中所述T形栅极是这样形成的：依次淀积掺杂硅和处于非晶态的非掺杂硅，进行栅极掩蔽操作和热处理，以及用聚湿性蚀刻溶液进行蚀刻。
8.根据权利要求7的方法，其中所述热处理是在600-750℃温度范围内进行0.5-5小时。
9.根据权利要求7的方法，其中所述聚湿性蚀刻溶液是按下列组分比组成的：NHO3∶CH3COOH∶HF∶H2O＝21∶3∶0.25-1.0∶15-16。
10.根据权利要求6的方法，其中在NMOS情况下所述掺杂氧化膜由PSG形成，在PMOS情况下所述掺杂氧化膜由BSG或BPSG形成。
11.根据权利要求6的方法，其中所述掺杂氧化膜形成至100-200的厚度。
12.根据权利要求6的方法，在NMOS情况下用n+多晶硅形成所述辅助栅极的多晶硅层，PMOS情况下用P+多晶硅形成所述辅助栅极的多晶硅层。
13.一种制造半导体器件的方法，包括下列步骤：
在硅衬底上形成栅氧化膜和T形栅极；
在包括所述T形栅极在内的所述硅衬底的整体结构的顶部淀积厚的掺杂氧化膜；
通过高温热处理过程中含于所述掺杂氧化膜中的杂质向所述硅衬底的扩散，形成轻掺杂区；
除去所述掺杂氧化膜，此后，在包括所述T形栅极在内的所述硅衬底的整体结构上依次形成薄的非掺杂氧化膜和厚的多晶硅层，并通过按敷层蚀刻方法蚀刻所述多晶硅层和非掺杂氧化膜，在所述T形栅极两侧下方的潜挖部位形成辅助栅极；和
通过高浓度杂质注入方法，在所述硅衬底中所述T形栅极的两侧形成重掺杂区。
14.根据权利要求13的方法，在NMOS情况下所述掺杂氧化膜由PSG形成，在PMOS情况下所述掺杂氧化膜由BSG或BPSG形成。
15.根据权利要求13的方法，其中所述非掺杂氧化膜由MTO或ONO形成。
16.根据权利要求13的方法，其中所述非掺杂氧化膜形成至100-200的厚度。
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KR960006004A (ko) 1996-02-23
GB2291741B (en) 1998-07-22
DE19527131A1 (de) 1996-02-01
CN1041471C (zh) 1998-12-30
JPH0846201A (ja) 1996-02-16
GB9515147D0 (en) 1995-09-20
GB2291741A (en) 1996-01-31
JP2774952B2 (ja) 1998-07-09

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