CN112349765A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN112349765A
CN112349765A CN202010145996.0A CN202010145996A CN112349765A CN 112349765 A CN112349765 A CN 112349765A CN 202010145996 A CN202010145996 A CN 202010145996A CN 112349765 A CN112349765 A CN 112349765A
Authority
CN
China
Prior art keywords
semiconductor
electrode
semiconductor layer
layer
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010145996.0A
Other languages
English (en)
Inventor
藤农佑树
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Electronic Devices and Storage Corp filed Critical Toshiba Corp
Publication of CN112349765A publication Critical patent/CN112349765A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/221—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities of killers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

实施方式涉及半导体装置及其制造方法。实施方式的半导体装置具备包含第1导电型的第1层的半导体部、设置于半导体部的背面侧的第1电极、设置于表面侧的第2电极、选择性设置于第2电极与半导体部之间的控制电极和将第2电极与半导体部电连接的接触部。半导体部进一步包含选择性设置于第1层与第2电极之间的第2导电型的第2层、选择性设置于第2层与第2电极之间的第1导电型的第3层、和选择性地设置于第2层与第2电极之间且包含与第2层的第2导电型杂质相比高浓度的第2导电型杂质的第2导电型的第4层。接触部包含与第3层相接并且被电连接的第1导电型的第1半导体区域和与第4层相接并且被电连接的第2导电型的第2半导体区域。

Description

半导体装置及其制造方法
关联申请
本申请享有以日本专利申请2019-145332号(申请日：2019年8月7日)作为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
实施方式涉及半导体装置及其制造方法。
背景技术
有使重金属在半导体中扩散而缩短了载流子的寿命的半导体装置。例如在具有MOS结构的半导体装置中，若使重金属从MOS结构侧的表面扩散，则半导体层中的重金属的浓度容易变得不均匀。
发明内容
实施方式提供能够抑制半导体层中的重金属的浓度变动的半导体装置及其制造方法。
实施方式的半导体装置具备：包含第1导电型的第1半导体层的半导体部、设置于上述半导体部的背面侧的第1电极、设置于上述半导体部的表面侧的第2电极、选择性地设置于上述第2电极与上述半导体部之间且介由第1绝缘膜与上述半导体部电绝缘且介由第2绝缘膜与上述第2电极电绝缘的控制电极、和将上述第2电极与上述半导体部电连接的接触部。上述半导体部进一步包含：选择性设置于上述第1半导体层与上述第2电极之间的第2导电型的第2半导体层、选择性设置于上述第2半导体层与上述第2电极之间的第1导电型的第3半导体层、和选择性地设置于上述第2半导体层与上述第2电极之间且包含与上述第2半导体层的第2导电型杂质相比高浓度的第2导电型杂质的第2导电型的第4半导体层。上述控制电极按照介由上述第1绝缘膜与上述第1半导体层及上述第2半导体层相对的方式配置。上述接触部包含与上述第3半导体层相接并且被电连接的第1导电型的第1半导体区域、和与上述第4半导体层相接并且被电连接的第2导电型的第2半导体区域。
附图说明
图1是表示实施方式的半导体装置的示意截面图。
图2A～图5B是表示实施方式的半导体装置的制造过程的示意截面图。
图6A及B是表示实施方式的第1变形例的半导体装置的制造过程的示意截面图。
图7A～C是表示实施方式的第2变形例的半导体装置的制造过程的示意截面图。
图8A～D是表示实施方式的第3变形例的半导体装置的制造过程的示意截面图。
图9A及B是表示实施方式的第3变形例的半导体装置的特性的示意截面图。
图10是表示实施方式的第4变形例的半导体装置的示意截面图。
具体实施方式
以下，参照附图对实施方式进行说明。对于附图中的同一部分标注同一序号并适当省略其详细说明，对不同的部分进行说明。需要说明的是，附图是示意性图或概念性图，各部分的厚度与宽度的关系、部分间的大小的比率等未必与现实的情况相同。另外，即使是表示相同部分的情况下，也有根据附图而彼此的尺寸或比率被不同表现的情况。
进而，使用各图中所示的X轴、Y轴及Z轴对各部分的配置及构成进行说明。X轴、Y轴、Z轴彼此正交，分别表示X方向、Y方向、Z方向。另外，有时以Z方向作为上方、以其相反方向作为下方进行说明。
图1是表示实施方式的半导体装置1的示意截面图。半导体装置1为功率MOSFET，例如具有平面型栅极结构。
半导体装置1包含半导体部10、漏极电极20(第1电极)、源极电极30(第2电极)和栅极电极40。半导体部10例如为硅。漏极电极20设置于半导体部10的背面侧。源极电极30设置于半导体部10的表面侧。
栅极电极40配置于半导体部10与源极电极30之间。栅极电极40介由栅极绝缘膜43与半导体部10电绝缘。另外，栅极电极40介由层间绝缘膜45与源极电极30电绝缘。
半导体部10包含n型漂移层11(第1半导体层)、p型基极层13(第2半导体层)、n型源极层15(第3半导体层)和p型接触层17(第4半导体层)。
n型漂移层11在漏极电极20与源极电极30之间延伸。n型漂移层11在断开时，通过对漏极电极20与源极电极30之间施加的漏极电压而被耗尽化，设置成给与规定的耐压的厚度。
p型基极层13位于n型漂移层11与源极电极30之间。p型基极层13包含与n型漂移层11的n型杂质的浓度相比高浓度的p型杂质。p型基极层13的一部分设置于介由栅极绝缘膜43与栅极电极40相对的位置。
n型源极层15选择性地设置于p型基极层13与源极电极30之间。n型源极层15包含与n型漂移层11的n型杂质的浓度相比高浓度的n型杂质。n型源极层15的一部分设置于介由栅极绝缘膜43与栅极电极40相对的位置。
p型接触层17选择性地设置于p型基极层13与源极电极30之间。p型接触层17包含与p型基极层13的p型杂质的浓度相比高浓度的p型杂质。p型接触层17例如在沿着半导体部10的表面的方向上与n型源极层15并列配置。
源极电极30在未设置栅极电极40的部分与n型源极层15及p型接触层17电连接。p型基极层13介由p型接触层17与源极电极30电连接。
在该例子中，设置接触部50，将n型源极层15与源极电极30之间、及p型接触层17与源极电极30之间电连接。接触部50包含n型半导体区域53、p型半导体区域55和硅化物区域57。
接触部50贯穿层间绝缘膜45在从源极电极30朝向半导体部10的方向上延伸。n型半导体区域53及p型半导体区域55位于半导体部10与硅化物区域57之间。源极电极30与硅化物区域57相接并且被电连接。
n型半导体区域53位于层间绝缘膜45与p型半导体区域55之间。n型半导体区域53与n型源极层15相接并且被电连接。另外，n型半导体区域53与硅化物区域57相接并且被电连接。
p型半导体区域55与p型接触层17相接并且被电连接。另外，p型半导体区域55与硅化物区域57相接并且被电连接。
半导体部10进一步包含n型半导体层19和n型漏极层23。n型半导体层19及n型漏极层23包含与n型漂移层11的n型杂质的浓度相比高浓度的n型杂质。另外，n型半导体层19的n型杂质的浓度比n型源极层15的n型杂质的浓度低。
n型半导体层19选择性地设置于n型漂移层11与栅极电极40之间。n型半导体层19按照与栅极绝缘膜43相接、且介由栅极绝缘膜43与栅极电极40相对的方式设置。n型半导体层19例如设置于在沿着半导体部10的表面的方向(例如X方向)上相邻的p型基极层13之间。p型基极层13的一部分在n型源极层15与n型半导体层19之间按照介由栅极绝缘膜43与栅极电极40相对的方式设置。
n型漏极层23位于n型漂移层11与漏极电极20之间。漏极电极20例如与n型漏极层23相接并且被电连接。
在实施方式的半导体装置1中，硅化物区域57例如包含铂(Pt)。即，硅化物区域57包含硅化铂。另外，n型半导体区域53及p型半导体区域55也包含铂(Pt)。进而，半导体部10包含从硅化物区域57介由n型半导体区域53及p型半导体区域55而扩散的铂(Pt)。由此，能够缩短半导体部10中的载流子的寿命，加快半导体装置1的开关速度。
需要说明的是，硅化物区域57及半导体部10中包含的金属元素并不限定于铂(Pt)，例如也可以是铂(Pt)、钌(Rh)、钯(Pd)、锇(Os)、铱(Ir)及金(Au)中的至少1种元素。
接着，参照图2A～图5B对实施方式的半导体装置1的制造方法进行说明。图2A～图5B是依次表示半导体装置1的制造过程的示意截面图。
如图2A中所示的那样，在半导体晶片100的表面侧形成p型基极层13、n型源极层15、p型接触层17、n型半导体层19、栅极电极40、栅极绝缘膜43及层间绝缘膜45后，在层间绝缘膜45中形成接触孔CH。接触孔CH按照与n型源极层15及p型接触层17连通的方式形成。半导体晶片100例如为n型硅片，包含与n型漂移层11的n型杂质相同浓度的n型杂质。
如图2B中所示的那样，在半导体晶片100的表面侧形成n型半导体膜101。n型半导体膜101例如是使用化学气相沉积(CVD，Chemical Vapor Deposition)而形成的多硅膜。n型半导体膜101按照在接触孔CH的内部残留空间、且覆盖层间绝缘膜45的上表面及接触孔CH的内表面的方式形成。n型半导体膜101包含例如在其沉积中添加的n型杂质。另外，也可以在沉积n型半导体膜101后，通过气相扩散而掺杂n型杂质例如磷(P)。
如图2C中所示的那样，保留沉积于接触孔CH的内壁上的部分，将n型半导体膜101选择性地除去。n型半导体膜101例如通过使用了反应离子蚀刻(RIE，Reactive IonEtching)的各向异性蚀刻而被选择性除去。
如图3A中所示的那样，在半导体晶片100的表面侧依次形成半导体膜103、p型杂质区域105及半导体膜107。
半导体膜103例如为使用CVD而形成的多硅膜。半导体膜103在未有意图地掺杂杂质的情况下形成。半导体膜103按照在接触孔CH的内部残留空间、且覆盖层间绝缘膜45的上表面及接触孔CH的内表面的方式形成。残留于接触孔CH的内壁上的n型半导体膜101位于层间绝缘膜45与半导体膜103之间。
接着，离子注入p型杂质例如硼(B)，形成p型杂质区域105。p型杂质区域105形成于半导体膜103的表面整体上。
进而，按照覆盖p型杂质区域105的方式形成半导体膜107。半导体膜107为例如使用CVD而形成的多硅膜，在未有意图地掺杂杂质的情况下形成。半导体膜107按照将接触孔CH内的空间埋入的方式形成。
如图3B中所示的那样，保留将接触孔CH埋入的部分，将形成于层间绝缘膜45上的半导体膜103、p型杂质区域105及半导体膜107选择性除去。半导体膜103、p型杂质区域105及半导体膜107例如使用化学机械抛光(CMP，Chemical Mechanical Polishing)而被除去。由此，残留在接触孔CH内的部分的上表面及层间绝缘膜45的上表面被平坦化。
如图3C中所示的那样，通过热处理使n型半导体膜101的n型杂质及p型杂质区域105的p型杂质扩散，形成n型半导体区域53及p型半导体区域55。n型半导体区域53按照与n型源极层15相接的方式形成。p型半导体区域55按照与p型接触层17相接的方式形成。
如图4A中所示的那样，在半导体晶片100的表面侧形成金属膜113。金属膜113例如使用溅射法而形成，包含铂(Pt)。金属膜113按照覆盖层间绝缘膜45、n型半导体区域53及p型半导体区域55的方式形成。
如图4B中所示的那样，形成覆盖n型半导体区域53及p型半导体区域55的硅化物区域57。硅化物区域57例如通过将金属膜113与n型半导体区域53的界面、及金属膜113与p型半导体区域55的界面通过热处理而硅化物化后将金属膜113的未反应的部分选择性除去而形成。
如图4C中所示的那样，使硅化物区域57中包含的铂(Pt)向半导体晶片100进行热扩散。铂(Pt)由于硅中的扩散系数大，所以通过实施热处理，经过n型半导体区域53及p型半导体区域55而扩散至半导体晶片100中。由此，能够使硅化物区域57的铂(Pt)向半导体晶片100均匀地扩散。
如图5A中所示的那样，在半导体晶片100的表面侧形成源极电极30。源极电极30按照覆盖层间绝缘膜45的方式形成，与硅化物区域57相接。源极电极30例如包含铝，介由硅化物区域57与n型半导体区域53及p型半导体区域55电连接。硅化物区域57将源极电极30与n型及p型半导体区域53、55之间的接触电阻降低。
如图5B中所示的那样，在半导体晶片100的背面侧形成n型漏极层23。例如，将半导体晶片100的背面侧磨削，薄层化至规定的厚度后，离子注入n型杂质例如磷(P)，形成n型漏极层23。离子注入的n型杂质例如使用激光退火在短时间内被热处理。由此，能够减轻对设置于半导体晶片100的表面侧的MOS结构给与的热处理的影响。
位于半导体晶片100的p型基极层13与n型漏极层23之间的部分成为n型漂移层11。进而，在n型漏极层23的背面上形成漏极电极20，完成半导体装置1。
在本实施方式的制造方法中，使铂(Pt)从形成于n型半导体区域53及p型半导体区域55上的硅化物区域57扩散至半导体部中，形成载流子陷阱。由此，变得能够形成从p型基极层13较深地分布至n型漂移层11中的载流子陷阱，能够提高半导体装置1的开关特性。
还有在半导体晶片100的表面侧形成例如包含源极电极30的MOS结构后从背面侧扩散铂(Pt)的方法。然而，在形成MOS结构后，为了不使MOS结构劣化，热处理的温度及时间受到限制。因此，变得难以使铂(Pt)较深地扩散至n型漂移层11中，有时开关特性的改善变得不充分。
与此相对，在实施方式的制造方法中，由于在形成源极电极30之前使铂(Pt)扩散，所以能够在更高的温度下实施长时间的热处理。由此，变得能够使铂(Pt)扩散至n型漂移层11的较深的位置，例如能够使载流子陷阱分布在n型漂移层11的整体中。另外，n型漏极层23中分布的铂的浓度与n型漂移层11中分布的铂的浓度相同或成为较低浓度。
另外，还有下述方法：如图2A中所示的那样，在层间绝缘膜45中形成接触孔CH后，按照与半导体部10(n型源极层15及p型接触层17)相接的方式形成金属膜113(参照图4A)，在半导体部10上直接形成含有铂(Pt)的硅化物区域。由此，能够使铂(Pt)扩散至半导体部10。然而，由于层间绝缘膜45例如硅氧化膜与包含铂(Pt)的金属膜113之间的密合强度低，所以在接触孔CH的底面，金属膜113变得容易从半导体部10剥离。因此，在用于硅化物化的热处理的过程中，有时金属膜113从半导体部10剥离，在接触孔CH的底面产生未形成硅化物区域的区域。例如若接触孔CH的长宽比(深度/宽度)变大，则变得无法形成硅化物区域。结果是，晶片间的铂(Pt)的扩散不稳定，半导体部10的铂浓度发生变动。
与此相对，在本实施方式的制造方法中，在n型半导体区域53、p型半导体区域55及层间绝缘膜45的平坦化的表面上形成金属膜113(参照图4A)。因此，能够在不使金属膜113从n型半导体区域53及p型半导体区域55剥离的情况下进行热处理。因此，能够使铂(Pt)介由n型半导体区域53及p型半导体区域55向半导体部10稳定地扩散。
需要说明的是，在上述的制造方法中，示出了使铂(Pt)向半导体部10扩散的例子，但实施方式并不限定于此。代替铂(Pt)，例如也可以使用钌(Rh)、钯(Pd)、锇(Os)、铱(Ir)、金(Au)等。通过使用这些元素，能够提高半导体装置1的开关特性。
图6A及B是表示实施方式的第1变形例的半导体装置1的制造方法的示意截面图。图6A表示紧接着图3C的制造过程。
如图6A中所示的那样，在半导体晶片100的表面侧离子注入铂(Pt)。即，代替图4A中所示的金属膜113，在n型半导体区域53的上表面侧及p型半导体区域55的上表面侧采用离子注入导入铂(Pt)。
接着，如图6B中所示的那样，通过热处理，使铂(Pt)介由n型半导体区域53及p型半导体区域55扩散至半导体部10。导入层间绝缘膜45中的铂(Pt)没有通过热处理而扩散，止于层间绝缘膜45中。
例如也可以如图2A中所示的那样，在层间绝缘膜45中形成接触孔CH后，将铂(Pt)直接离子注入到半导体部10中并使其扩散。然而，通过铂(Pt)的离子注入而形成的注入损伤有时会使FET特性劣化。
在该例子中，离子注入的损伤形成于n型半导体区域53及p型半导体区域55中。n型半导体区域53及p型半导体区域55例如为多硅区域，其特性不会因注入损伤而劣化。即，n型半导体区域53及p型半导体区域55只要将n型源极层15及p型接触层17与源极电极30之间电连接即可，其特性不会因注入损伤而劣化。因此，因形成于n型半导体区域53及p型半导体区域55中的注入损伤而产生的对FET特性的影响小、或能够避免影响。
图7A～C是表示实施方式的第2变形例的半导体装置的制造过程的示意截面图。图7A表示紧接着图4C的制造过程。
如图7A中所示的那样，使铂(Pt)扩散至半导体部10后，除去硅化物区域57，使n型半导体区域53及p型半导体区域55露出。硅化物区域57例如通过湿式蚀刻而除去。
如图7B中所示的那样，通过将n型半导体区域53及p型半导体区域55选择性除去而形成接触孔CH2。在接触孔CH2的底面，例如使n型源极层15及p型接触层17露出。
如图7C中所示的那样，在半导体晶片100的表面侧形成源极电极130。源极电极130例如包含阻挡膜123、埋入膜125和接合膜127。源极电极130按照将接触孔CH2埋入的方式设置，例如与n型源极层15及p型接触层17相接并且被电连接。
阻挡膜123按照覆盖层间绝缘膜45的上表面及接触孔CH2的内表面的方式形成。阻挡膜123按照与n型源极层15及p型接触层17相接的方式形成。阻挡膜123例如为氮化钛(TiN)膜。埋入膜125例如为钨膜，按照将接触孔CH2的内部埋入的方式形成。接合膜127例如为铝膜，形成于埋入膜125上。
在该例子中，通过将n型半导体区域53及p型半导体区域55置换成金属膜，能够降低将接触孔CH2的内部埋入的部分的电阻。
图8A～D是表示实施方式的第3变形例的半导体装置1的制造方法的示意截面图。图8A是表示紧接着图3C的制造过程的示意截面图。
如图8A中所示的那样，在半导体晶片100的表面侧形成绝缘膜135。绝缘膜135例如是使用CVD而形成的硅氮化膜、或通过将n型半导体区域53及p型半导体区域55的表面氧化而形成的硅氧化膜。在使用CVD来形成绝缘膜135的情况下，绝缘膜135将层间绝缘膜45、n型半导体区域53及p型半导体区域55覆盖。在通过氧化来形成绝缘膜135的情况下，绝缘膜135将n型半导体区域53及p型半导体区域55覆盖。
如图8B中所示的那样，将绝缘膜135选择性除去，使n型半导体区域53及p型半导体区域55露出。绝缘膜135例如使用抗蚀剂掩模140而被选择性除去。抗蚀剂掩模140使用光刻而形成。在本实施方式中，由于使n型半导体区域53及p型半导体区域55露出的层间绝缘膜45的表面被平坦化，所以利用光刻的图案化变得容易。
如图8C中所示的那样，在半导体晶片100的表面侧形成金属膜113。金属膜113例如使用溅射法而形成，包含铂(Pt)。金属膜113按照覆盖n型半导体区域53及p型半导体区域55以及绝缘膜135的方式形成。接着，通过实施热处理，在n型半导体区域53及p型半导体区域55与金属膜113的边界形成硅化物区域57。硅化物区域57包含铂(Pt)。在被绝缘膜135覆盖的n型半导体区域53及p型半导体区域55上，未形成硅化物区域57。
如图8D中所示的那样，保留与n型半导体区域53及p型半导体区域55反应而形成的硅化物区域57，将金属膜113除去。接着，使硅化物区域57的铂(Pt)介由n型半导体区域53及p型半导体区域55向半导体部10扩散。在该例子中，在未被绝缘膜135覆盖的区域中，能够使铂(Pt)选择性向半导体部10扩散。接着，将绝缘膜135除去，形成源极电极30。
铂(Pt)没有扩散至在上端未形成硅化物区域57的n型半导体区域53及p型半导体区域55。另外，即使铂介由半导体晶片100被扩散至n型半导体区域53及p型半导体区域55，其浓度与在上端形成有硅化物区域57的n型半导体区域53及p型半导体区域55中的铂(Pt)的浓度相比也为低浓度。
图9A及B是表示实施方式的第3变形例的半导体装置1的示意图。图9A是表示半导体晶片100的表面的平面图。图9B是表示半导体装置1的开关特性的示意图。
如图9A中所示的那样，绝缘膜135按照将扩散有铂(Pt)的器件区域DR包围的方式设置。绝缘膜135例如按照覆盖半导体装置1的终端区域的方式形成。即，铂(Pt)选择性扩散至半导体装置1的器件区域DR，形成载流子陷阱。因此，在终端区域，未形成载流子陷阱。
图9B表示经由图8A～D中所示的制造过程而制作的半导体装置1的开关特性。纵轴为在漏极、源极间流动的漏极电流，横轴为时间。
例如，在时间t1时，半导体装置1被关断，漏极电流的值下降。漏极电流例如在时间t2时从接通状态的值ION下降至最小值IMIN，之后，在时间t3时恢复成断开状态的值IOFF。
从时间t1至t2的期间Trr1例如依赖于载流子从n型漂移层11向漏极电极20及源极电极30的排出时间。因此，在半导体装置1中，通过使铂(Pt)扩散至n型漂移层11而形成载流子陷阱，能够缩短Trr1。由此，能够降低半导体装置1的开关损耗。
从时间t2至t3的期间Trr2例如依赖于终端区域中的载流子的排出时间。Trr2例如与开关噪声相关联，Trr2变得越长则越能够抑制噪声水平。在半导体装置1中，通过不使铂(Pt)扩散至终端区域，从而较长地保持Trr2，抑制开关噪声。
像这样，在半导体装置1中，通过使铂(Pt)选择性扩散至器件区域，抑制终端区域中的铂(Pt)的扩散，从而能够提高开关特性。
图10是表示实施方式的第4变形例的半导体装置2的示意截面图。半导体装置2包含半导体部110、漏极电极20、源极电极30和栅极电极40。漏极电极20设置于半导体部110的背面侧，源极电极30设置于半导体部110的表面侧。栅极电极40配置于半导体部110与源极电极30之间。
在该例子中，半导体部110包含多个p型半导体区域11P。p型半导体区域11P设置于n型漂移层11中。p型半导体区域11P分别配置于p型基极层13与n型漏极层23之间。另外，p型半导体区域11P按照与p型基极层13连接的方式设置。进而，多个p型半导体区域11P在沿着半导体部110的表面或背面的方向(例如X方向)上并列配置。
n型漂移层11包含n型半导体区域11N。n型半导体区域11N位于在X方向上相邻的p型半导体区域11P之间。p型半导体区域11P及n型半导体区域11N构成所谓的超级结结构。例如在X方向上邻接的p型半导体区域11P及n型半导体区域11N按照它们中包含的n型杂质的总量与p型杂质的总量变得大致相等的方式形成。
如图10中所示的那样，半导体装置2包含将源极电极30与半导体部110电连接的接触部150。接触部150包含n型半导体区域53、p型半导体区域55和硅化物区域57。
n型半导体区域53与n型源极层15相接并且被电连接。p型半导体区域55与p型接触层17相接并且被电连接。n型半导体区域53及p型半导体区域55介由硅化物区域57与源极电极30电连接。
半导体部110及接触部150例如按照包含铂(Pt)的方式设置。铂(Pt)从接触部150分布至p型基极层13、p型半导体区域11P及n型半导体区域11N。
在该例子中，也能够均匀地设置半导体部110中分布的铂(Pt)。由此，能够提高半导体装置2的开关特性。需要说明的是，半导体装置2可以使用上述的制造方法中的任一种来制造。
对本发明的几个实施方式进行了说明，但这些实施方式是作为例子提出的，并不意图限定发明的范围。这些新颖的实施方式可以以其它的各种方式实施，在不脱离发明的主旨的范围内，可以进行各种省略、置换、变更。这些实施方式或其变形包含于发明的范围、主旨中，同时包含于权利要求书中记载的发明和其同等的范围内。

Claims (16)

1.一种半导体装置，其具备：
半导体部，该半导体部包含第1导电型的第1半导体层；
第1电极，该第1电极设置于所述半导体部的背面侧；
第2电极，该第2电极设置于所述半导体部的表面侧；
控制电极，该控制电极选择性地设置于所述第2电极与所述半导体部之间，介由第1绝缘膜与所述半导体部电绝缘，且介由第2绝缘膜与所述第2电极电绝缘；和
接触部，该接触部将所述第2电极与所述半导体部电连接，
所述半导体部进一步包含：选择性设置于所述第1半导体层与所述第2电极之间的第2导电型的第2半导体层、选择性设置于所述第2半导体层与所述第2电极之间的第1导电型的第3半导体层、和选择性地设置于所述第2半导体层与所述第2电极之间且包含与所述第2半导体层的第2导电型杂质相比高浓度的第2导电型杂质的第2导电型的第4半导体层，
所述控制电极按照介由所述第1绝缘膜与所述第2半导体层相对的方式配置，
所述接触部包含与所述第3半导体层相接并且被电连接的第1导电型的第1半导体区域、和与所述第4半导体层相接并且被电连接的第2导电型的第2半导体区域。
2.根据权利要求1所述的半导体装置，其中，所述接触部及所述半导体部包含铂(Pt)、钌(Rh)、钯(Pd)、锇(Os)、铱(Ir)及金(Au)中的至少1种元素。
3.根据权利要求1所述的半导体装置，其中，所述接触部贯穿所述第2绝缘膜在从所述第2电极朝向所述半导体部的方向上延伸，
所述第1半导体区域位于所述第2绝缘膜与所述第2半导体区域之间。
4.根据权利要求1所述的半导体装置，其中，所述接触部包含位于所述第1半导体区域与所述第2电极之间及所述第2半导体区域与所述第2电极之间的硅化物区域，
所述硅化物区域与所述第2电极相接并且被电连接，包含铂(Pt)、钌(Rh)、钯(Pd)、锇(Os)、铱(Ir)及金(Au)中的至少1种元素。
5.根据权利要求1所述的半导体装置，其中，所述半导体部进一步包含所述第1导电型的第5半导体层，
所述第5半导体层选择性地设置于所述第1半导体层与所述控制电极之间，包含与所述第1半导体层的第1导电型杂质的浓度相比高浓度的第1导电型杂质，
所述第2半导体层包含位于所述第3半导体层与所述第5半导体层之间的部分。
6.一种半导体装置，其具备：
半导体部，该半导体部包含第1导电型的第1半导体层；
第1电极，该第1电极设置于所述半导体部的背面侧；
第2电极，该第2电极设置于所述半导体部的表面侧；
控制电极，该控制电极选择性地设置于所述第2电极与所述半导体部之间，介由第1绝缘膜与所述半导体部电绝缘，且介由第2绝缘膜与所述第2电极电绝缘；和
接触部，该接触部将所述第2电极与所述半导体部电连接，
所述半导体部进一步包含：选择性设置于所述第1半导体层与所述第2电极之间的第2导电型的第2半导体层、选择性设置于所述第2半导体层与所述第2电极之间的第1导电型的第3半导体层、和选择性地设置于所述第2半导体层与所述第2电极之间且包含与所述第2半导体层的第2导电型杂质相比高浓度的第2导电型杂质的第2导电型的第4半导体层，
所述控制电极按照介由所述第1绝缘膜与所述第1半导体层及所述第2半导体层相对的方式配置，
所述接触部包含与所述第3半导体层及所述第4半导体层相接并且被电连接的半导体区域，
所述半导体区域及所述半导体部包含铂(Pt)、钌(Rh)、钯(Pd)、锇(Os)、铱(Ir)及金(Au)中的至少1种元素。
7.根据权利要求6所述的半导体装置，其中，所述第2半导体层包含所述至少1种元素。
8.根据权利要求6所述的半导体装置，其中，所述半导体部进一步包含所述第1导电型的第6半导体层，
所述第6半导体层设置于所述第1半导体层与所述第1电极之间，包含与所述第1半导体层的第1导电型杂质的浓度相比高浓度的第1导电型杂质，包含与所述第1半导体层的所述至少1种元素的浓度相同或比其低浓度的所述至少1种元素。
9.根据权利要求6所述的半导体装置，其中，所述第2绝缘膜包含所述至少1种元素。
10.根据权利要求6所述的半导体装置，其中，所述接触部设置有多个，
所述多个接触部包含第1接触部及第2接触部，
所述第1接触部包含所述至少1种元素，
所述第2接触部包含与所述第1接触部中的所述至少1种元素的浓度相比低浓度的所述至少1种元素。
11.一种半导体装置的制造方法，其中，在半导体晶片上形成具有接触孔的绝缘膜，
形成将所述接触孔埋入且包含铂(Pt)、钌(Rh)、钯(Pd)、锇(Os)、铱(Ir)及金(Au)中的至少1种元素的半导体部分，
使所述至少1种元素介由所述半导体部分扩散至所述半导体晶片中。
12.根据权利要求11所述的制造方法，其中，形成覆盖所述绝缘膜及所述半导体部分、且包含所述至少1种元素的金属膜，使所述至少1种元素扩散至所述半导体部分。
13.根据权利要求11所述的制造方法，其中，使所述至少1种元素扩散至所述半导体晶片中后，将所述半导体部分除去。
14.根据权利要求12所述的制造方法，其中，在所述金属膜与包含硅的所述半导体部分之间形成包含所述至少1种元素的硅化物区域，所述至少1种元素介由所述硅化物区域扩散至所述半导体部分。
15.根据权利要求14所述的制造方法，其中，所述接触孔及所述半导体部分分别设置有多个，包含所述至少1种元素的区域形成于所述多个半导体部分的一部分上。
16.根据权利要求11所述的制造方法，其中，向所述半导体部分中离子注入铂(Pt)、钌(Rh)、钯(Pd)、锇(Os)、铱(Ir)及金(Au)中的至少1种元素，通过将所述半导体晶片进行热处理而使所述至少1种元素扩散至所述半导体部分中。
CN202010145996.0A 2019-08-07 2020-03-05 半导体装置及其制造方法 Pending CN112349765A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019-145332 2019-08-07
JP2019145332A JP7189848B2 (ja) 2019-08-07 2019-08-07 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
CN112349765A true CN112349765A (zh) 2021-02-09

Family

ID=74357166

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010145996.0A Pending CN112349765A (zh) 2019-08-07 2020-03-05 半导体装置及其制造方法

Country Status (3)

Country Link
US (2) US11081355B2 (zh)
JP (1) JP7189848B2 (zh)
CN (1) CN112349765A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022148177A (ja) 2021-03-24 2022-10-06 株式会社東芝 半導体装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63244777A (ja) * 1987-03-31 1988-10-12 Toshiba Corp Ｍｏｓ型電界効果トランジスタ
JP2009043880A (ja) * 2007-08-08 2009-02-26 Panasonic Corp 炭化珪素半導体装置の製造方法および炭化珪素半導体装置
CN101501859A (zh) * 2006-08-17 2009-08-05 克里公司 高功率绝缘栅双极晶体管
CN202394977U (zh) * 2010-10-29 2012-08-22 松下电器产业株式会社 半导体元件及半导体装置
US20130062622A1 (en) * 2011-09-08 2013-03-14 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20150123148A1 (en) * 2012-05-11 2015-05-07 Rohm Co., Ltd. Semiconductor device and method for producing semiconductor device

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5397716A (en) * 1993-05-03 1995-03-14 Motorola, Inc. Method of forming an insulated gate semiconductor device
JPH0758322A (ja) 1993-08-13 1995-03-03 Toshiba Corp 半導体装置及びその製造方法
JP4220459B2 (ja) * 2004-11-22 2009-02-04 株式会社東芝 半導体装置
EP1834360A2 (en) * 2004-12-30 2007-09-19 Koninklijke Philips Electronics N.V. Enhancement - depletion semiconductor structure and method for making it
US7504700B2 (en) * 2005-04-21 2009-03-17 International Business Machines Corporation Method of forming an ultra-thin [[HfSiO]] metal silicate film for high performance CMOS applications and semiconductor structure formed in said method
WO2006134930A1 (ja) 2005-06-13 2006-12-21 Hitachi Kokusai Electric Inc. 半導体装置の製造方法、及び基板処理装置
US7847315B2 (en) * 2007-03-09 2010-12-07 Diodes Fabtech Inc. High efficiency rectifier
JP5083885B2 (ja) 2007-11-20 2012-11-28 日本インター株式会社 Ｊｂｓおよびｍｏｓｆｅｔ
JP5671867B2 (ja) * 2010-08-04 2015-02-18 富士電機株式会社 半導体装置およびその製造方法
WO2012169053A1 (ja) 2011-06-09 2012-12-13 トヨタ自動車株式会社 半導体装置および半導体装置の製造方法
JP6111572B2 (ja) * 2012-09-12 2017-04-12 富士電機株式会社 半導体装置および半導体装置の製造方法
JP5983415B2 (ja) * 2013-01-15 2016-08-31 住友電気工業株式会社 炭化珪素半導体装置
JP6728096B2 (ja) * 2017-04-24 2020-07-22 株式会社東芝 半導体装置、半導体装置の製造方法、インバータ回路、駆動装置、車両、及び、昇降機
JP6377302B1 (ja) * 2017-10-05 2018-08-22 三菱電機株式会社 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63244777A (ja) * 1987-03-31 1988-10-12 Toshiba Corp Ｍｏｓ型電界効果トランジスタ
CN101501859A (zh) * 2006-08-17 2009-08-05 克里公司 高功率绝缘栅双极晶体管
JP2009043880A (ja) * 2007-08-08 2009-02-26 Panasonic Corp 炭化珪素半導体装置の製造方法および炭化珪素半導体装置
CN202394977U (zh) * 2010-10-29 2012-08-22 松下电器产业株式会社 半导体元件及半导体装置
US20130062622A1 (en) * 2011-09-08 2013-03-14 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20150123148A1 (en) * 2012-05-11 2015-05-07 Rohm Co., Ltd. Semiconductor device and method for producing semiconductor device

Also Published As

Publication number Publication date
JP7189848B2 (ja) 2022-12-14
US20210343532A1 (en) 2021-11-04
US20210043458A1 (en) 2021-02-11
US11081355B2 (en) 2021-08-03
JP2021027229A (ja) 2021-02-22
US11705334B2 (en) 2023-07-18

Similar Documents

Publication Publication Date Title
JP5316954B2 (ja) ダイレクトトレンチポリシリコンコンタクトを備える横型トレンチｍｏｓｆｅｔ
US8558308B1 (en) Method of manufacturing a semiconductor device using a contact implant and a metallic recombination element and semiconductor
US7867854B2 (en) Method of fabricating power semiconductor device
US7655974B2 (en) Semiconductor device
US20100200912A1 (en) Mosfets with terrace irench gate and improved source-body contact
US20150087128A1 (en) Method of manufacturing a semiconductor device that includes a misfet
TW201725728A (zh) 在垂直功率半導體裝置中之源極－閘極區域架構
TW201917900A (zh) 一種具有不同能障高度的二極體裝置的半導體裝置及其製造方法
US7843014B2 (en) Small size transistor semiconductor device capable of withstanding high voltage
CN113053995A (zh) 半导体装置
US11705334B2 (en) Semiconductor device and method of manufacturing same
US20080169505A1 (en) Structure of Trench MOSFET and Method for Manufacturing the same
US7166891B2 (en) Semiconductor device with etch resistant electrical insulation layer between gate electrode and source electrode
US20160172201A1 (en) Manufacturing method of semiconductor device
US20080173924A1 (en) Semiconductor device and method for manufacturing semiconductor device
CN111081548B (zh) 完全硅化栅控装置及其形成方法
US6316319B1 (en) Method of manufacturing a semiconductor device having shallow junctions
US11081556B2 (en) Silicon carbide semiconductor device
JP6243748B2 (ja) 半導体素子及びその製造方法
JP2023005683A (ja) 炭化珪素半導体装置およびその製造方法
JP4984697B2 (ja) 半導体装置の製造方法
JP2012099530A (ja) 半導体装置およびその製造方法
JP2023055162A (ja) 炭化珪素半導体装置
JP2024044655A (ja) 半導体装置およびその製造方法
US7999316B2 (en) Semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination