JP6728096B2 - 半導体装置、半導体装置の製造方法、インバータ回路、駆動装置、車両、及び、昇降機 - Google Patents
半導体装置、半導体装置の製造方法、インバータ回路、駆動装置、車両、及び、昇降機 Download PDFInfo
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- JP6728096B2 JP6728096B2 JP2017085421A JP2017085421A JP6728096B2 JP 6728096 B2 JP6728096 B2 JP 6728096B2 JP 2017085421 A JP2017085421 A JP 2017085421A JP 2017085421 A JP2017085421 A JP 2017085421A JP 6728096 B2 JP6728096 B2 JP 6728096B2
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- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
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- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
Description
本実施形態の半導体装置は、第1の電極と、第2の電極と、ゲート電極と、第1の電極と第2の電極との間及び、ゲート電極と第2の電極との間に位置するn型の第1の炭化珪素領域と、第1の電極と第1の炭化珪素領域との間に位置するp型の第2の炭化珪素領域と、第1の電極と第2の炭化珪素領域との間に位置し、第1の炭化珪素領域と離間し、ニッケル(Ni)、パラジウム(Pd)、及び、白金(Pt)から成る群から選ばれる少なくとも一つの元素を含む金属の第3の炭化珪素領域と、ゲート電極と第2の炭化珪素領域との間に位置するゲート絶縁層と、を備える。
本実施形態の半導体装置の製造方法は、熱処理の前に、炭化珪素層にp型不純物、上記少なくとも一つの元素、及び、炭素(C)をイオン注入して、p型の第4の炭化珪素領域を形成する点、すなわち、p型の第4の炭化珪素領域を形成する際、上記少なくとも一つの元素、及び、炭素(C)を追加でイオン注入する点で、第1の実施形態と異なっている。以下、第1の実施形態と重複する内容については一部記述を省略する。
本実施形態の半導体装置は、n型の第5の炭化珪素領域を備えない点で、第1の実施形態と異なる。以下、第1の実施形態と重複する内容については一部記述を省略する。
(第4の実施形態)
本実施形態の半導体装置は、第3の炭化珪素領域との間に第2の炭化珪素領域を挟んで位置し、ゲート絶縁層及び第1の炭化珪素領域に接し、上記少なくとも一つの元素を有する金属の第6の炭化珪素領域を、更に備える点で、第1の実施形態と異なる。以下、第1の実施形態と重複する内容については一部記述を省略する。
(第5の実施形態)
本実施形態の半導体装置は、ゲート絶縁層とゲート電極がトレンチ内に形成される、いわゆるトレンチMOSFETである点で、第1の実施形態と異なる。以下、第1の実施形態と重複する内容については一部記述を省略する。
本実施形態の半導体装置は、ゲート絶縁層とゲート電極がトレンチ内に形成される、いわゆるトレンチMOSFETである点で、第3の実施形態と異なる。また、半導体ソース領域28(第5の炭化珪素領域)を備えない点で、第5の実施形態と異なる。以下、第3及び第5の実施形態と重複する内容については一部記述を省略する。
本実施形態の半導体装置は、第3の炭化珪素領域との間に第2の炭化珪素領域を挟んで位置し、ゲート絶縁層及び第1の炭化珪素領域に接し、上記少なくとも一つの元素を有する金属の第6の炭化珪素領域を、更に備える点で、第5の実施形態と異なる。以下、第5の実施形態と重複する内容については一部記述を省略する。
本実施形態の半導体装置は、第3の炭化珪素領域を備えない点で、第7の実施形態と異なる。以下、第7の実施形態と重複する内容については一部記述を省略する。
本実施形態のインバータ回路及び駆動装置は、第1の実施形態の半導体装置を備える駆動装置である。
本実施形態の車両は、第1の実施形態の半導体装置を備える車両である。
本実施形態の車両は、第1の実施形態の半導体装置を備える車両である。
本実施形態の昇降機は、第1の実施形態の半導体装置を備える昇降機である。
14 ドレイン電極(第2の電極)
16 ゲート絶縁層
18 ゲート電極
20 層間絶縁層
22 ドレイン領域(第7の炭化珪素領域)
24 ドリフト領域(第1の炭化珪素領域)
26 ボディ領域(第2の炭化珪素領域)
28 半導体ソース領域(第5の炭化珪素領域)
30 金属ソース領域(第3の炭化珪素領域)
32 ボディコンタクト領域(第4の炭化珪素領域)
34 金属領域(第6の炭化珪素領域)
100 MOSFET(半導体装置)
200 MOSFET(半導体装置)
300 MOSFET(半導体装置)
400 MOSFET(半導体装置)
500 MOSFET(半導体装置)
600 MOSFET(半導体装置)
700 MOSFET(半導体装置)
800 駆動装置
900 車両
1000 車両
1100 昇降機
Claims (20)
- 第1の電極と、
第2の電極と、
ゲート電極と、
前記第1の電極と前記第2の電極との間及び、前記ゲート電極と前記第2の電極との間に位置するn型の第1の炭化珪素領域と、
前記第1の電極と前記第1の炭化珪素領域との間に位置するp型の第2の炭化珪素領域と、
前記第1の電極と前記第2の炭化珪素領域との間に位置し、前記第1の炭化珪素領域と離間し、ニッケル(Ni)、パラジウム(Pd)、及び、白金(Pt)から成る群から選ばれる少なくとも一つの元素を含む金属の第3の炭化珪素領域と、
前記ゲート電極と前記第2の炭化珪素領域との間に位置するゲート絶縁層と、
を備える半導体装置。 - 前記少なくとも一つの元素は、炭化珪素の結晶構造の炭素サイトに存在する請求項1記載の半導体装置。
- 前記第3の炭化珪素領域は、炭化珪素の結晶構造の炭素サイトに存在するシリコン(Si)を含む請求項1又は請求項2記載の半導体装置。
- 前記少なくとも一つの元素の前記第3の炭化珪素領域中の濃度は、1×1019cm−3以上5×1022cm−3以下である請求項1ないし請求項3いずれか一項記載の半導体装置。
- 前記第3の炭化珪素領域の前記第1の電極から前記第2の電極に向かう方向の厚さは、0.01μm以上0.5μm以下である請求項1ないし請求項4いずれか一項記載の半導体装置。
- 前記第3の炭化珪素領域のシート抵抗が0.5Ω/□以下である請求項1ないし請求項5いずれか一項記載の半導体装置。
- 前記第3の炭化珪素領域の仕事関数が3.7eV以下である請求項1ないし請求項6いずれか一項記載の半導体装置。
- 前記第2の炭化珪素領域と前記第1の電極との間に位置し、前記第2の炭化珪素領域よりもp型不純物の不純物濃度が高いp型の第4の炭化珪素領域を、更に備える請求項1ないし請求項7いずれか一項記載の半導体装置。
- 前記第4の炭化珪素領域は、炭化珪素の結晶構造のシリコンサイトに存在する前記少なくとも一つの元素を含む請求項8記載の半導体装置。
- 前記第2の炭化珪素領域と前記第3の炭化珪素領域との間にn型の第5の炭化珪素領域を、更に備える請求項1ないし請求項9いずれか一項記載の半導体装置。
- 前記第3の炭化珪素領域との間に前記第2の炭化珪素領域を挟んで位置し、前記ゲート絶縁層及び前記第1の炭化珪素領域に接し、前記少なくとも一つの元素を有する金属の第6の炭化珪素領域を、更に備える請求項1ないし請求項10いずれか一項記載の半導体装置。
- 前記第1の炭化珪素領域と前記第2の電極との間に位置し、前記第1の炭化珪素領域よりもn型不純物の不純物濃度の高いn型の第7の炭化珪素領域を、更に備える請求項1ないし請求項11いずれか一項記載の半導体装置。
- 請求項1ないし請求項12いずれか一項記載の半導体装置を備えるインバータ回路。
- 請求項1ないし請求項12いずれか一項記載の半導体装置を備える駆動装置。
- 請求項1ないし請求項12いずれか一項記載の半導体装置を備える車両。
- 請求項1ないし請求項12いずれか一項記載の半導体装置を備える昇降機。
- n型の第1の炭化珪素領域を有する炭化珪素層にp型不純物をイオン注入してp型の第2の炭化珪素領域を形成し、
前記炭化珪素層に、ニッケル(Ni)、パラジウム(Pd)、及び、白金(Pt)から成る群から選ばれる少なくとも一つの元素をイオン注入し、
前記少なくとも一つの元素をイオン注入した後に熱処理を行い、前記少なくとも一つの元素が注入された領域を金属化して金属の第3の炭化珪素領域を形成し、
前記第2の炭化珪素領域の上にゲート絶縁層を形成し、
前記ゲート絶縁層の上にゲート電極を形成し、
前記第3の炭化珪素領域の上に第1の電極を形成し、
前記第1の電極との間に前記炭化珪素層を挟んで、第2の電極を形成する半導体装置の製造方法。 - 前記熱処理の前に、前記炭化珪素層の前記少なくとも一つの元素をイオン注入する領域に、シリコン(Si)をイオン注入する請求項17記載の半導体装置の製造方法。
- 前記熱処理の前に、前記炭化珪素層にp型不純物、前記少なくとも一つの元素、及び、炭素(C)をイオン注入し、p型の第4の炭化珪素領域を形成する請求項17又は請求項18いずれか一項記載の半導体装置の製造方法。
- 前記熱処理の前に、前記炭化珪素層にn型不純物をイオン注入し、n型の第5の炭化珪素領域を形成する請求項17ないし請求項19いずれか一項記載の半導体装置の製造方法。
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