CN111819684A - 电子组件安装模块 - Google Patents
电子组件安装模块 Download PDFInfo
- Publication number
- CN111819684A CN111819684A CN201880090685.XA CN201880090685A CN111819684A CN 111819684 A CN111819684 A CN 111819684A CN 201880090685 A CN201880090685 A CN 201880090685A CN 111819684 A CN111819684 A CN 111819684A
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- CN
- China
- Prior art keywords
- electronic component
- lead frame
- bonded
- linear expansion
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 229910052802 copper Inorganic materials 0.000 claims abstract description 52
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- CRWNQZTZTZWPOF-UHFFFAOYSA-N 2-methyl-4-phenylpyridine Chemical compound C1=NC(C)=CC(C=2C=CC=CC=2)=C1 CRWNQZTZTZWPOF-UHFFFAOYSA-N 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- XNGYKPINNDWGGF-UHFFFAOYSA-L silver oxalate Chemical compound [Ag+].[Ag+].[O-]C(=O)C([O-])=O XNGYKPINNDWGGF-UHFFFAOYSA-L 0.000 description 1
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- FTNNQMMAOFBTNJ-UHFFFAOYSA-M silver;formate Chemical compound [Ag+].[O-]C=O FTNNQMMAOFBTNJ-UHFFFAOYSA-M 0.000 description 1
- CYLMOXYXYHNGHZ-UHFFFAOYSA-M silver;propanoate Chemical compound [Ag+].CCC([O-])=O CYLMOXYXYHNGHZ-UHFFFAOYSA-M 0.000 description 1
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- 239000010936 titanium Substances 0.000 description 1
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- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Abstract
电子组件安装模块具有:电子组件;第一银烧结接合层,与该电子组件的一个面接合;绝缘电路基板,具有与第一银烧结接合层接合且由铜或铜合金制成的电路层和与该电路层接合的陶瓷基板,所述绝缘电路基板的线膨胀系数比电子组件小;第二银烧结接合层,与电子组件的另一个面接合;及引线框,与第二银烧结接合层接合,所述引线框的线膨胀系数比电子组件小,所述引线框与绝缘电路基板的线膨胀系数之差为5ppm/℃以下。
Description
技术领域
本发明涉及一种在绝缘电路基板安装有功率元件、LED元件、热电元件、其他电子组件的电子组件安装模块。
背景技术
在电子组件安装模块中,在控制大电流、高电压的半导体装置中使用的功率模块中,要求对大电流容量的应对、配线电阻的减小。因此,例如在专利文献1中采用了如下结构:与半导体元件连接的配线通过引线框形成,该引线框由铜制成,利用环氧树脂等对电子组件(功率半导体元件、控制半导体元件)及引线框(外部引线框、内部引线框)的接合部分进行树脂密封。
并且,例如,如专利文献2所示,在电子组件安装模块中使用如下的绝缘电路基板(功率模块用基板):由铝板等制成的电路层与以氮化铝为首的绝缘基板的一个面接合,并且由铝板等制成的金属层与另一个面接合。由铜等制成的散热片与该绝缘电路基板的金属层接合。
在将电子组件及引线框接合到该绝缘电路基板来构成电子组件安装模块的情况下,例如,在将电路层及金属层接合到绝缘基板的两个面的绝缘电路基板的电路层上,通过银烧结接合或焊接等方法接合电子组件。之后,通过焊接等将由铜制成的引线框接合到该电子组件上。
专利文献1:日本特开2001-291823号公报
专利文献2:日本特开2005-328087号公报
在上述的电子组件安装模块中,与电子组件相比,电路层、引线框中所使用的铝或铝合金、或者铜或铜合金的线膨胀系数较大。因此,在通过焊接将电子组件、引线框安装于电路层的情况下,由于使用环境的变化、电子组件的电阻发热等,电子组件、引线框与电路层之间的焊锡接合层反复受到热应力,有可能会在焊锡接合层中产生裂纹。并且,在通过银烧结接合代替焊接来安装电子组件、引线框的情况下,与焊锡接合层相比,银烧结接合层在高温环境下的接合可靠性高,导热性优异。但是,与焊锡接合层相比,银烧结接合层薄且硬,因此强的热应力作用于电子组件本身,有可能会在电子组件中产生损伤。
发明内容
本发明是鉴于这种情况而完成的,其目的在于提供一种能够利用银烧结接合层提高电路层、电子组件及引线框的接合可靠性,并且能够防止电子组件的损伤的电子组件安装模块。
本发明的电子组件安装模块具有:电子组件;第一银烧结接合层,与所述电子组件的一个面接合;绝缘电路基板,具有与所述第一银烧结接合层接合且由铜或铜合金制成的电路层和与该电路层接合的陶瓷基板,所述绝缘电路基板的线膨胀系数比所述电子组件小;第二银烧结接合层,与所述电子组件的另一个面接合;及引线框,与所述第二银烧结接合层接合,所述引线框的线膨胀系数比所述电子组件小,所述引线框与所述绝缘电路基板的线膨胀系数之差为5ppm/℃以下。
电子组件安装模块中,对于绝缘电路基板及引线框而言,使用线膨胀系数比电子组件小的绝缘电路基板及引线框,经由银烧结接合层(第一银烧结接合层、第二银烧结接合层)将电子组件的两个面接合到绝缘电路基板及引线框,因此即使在高温环境下也具有高接合可靠性。并且,银烧结接合层的导热性优异,因此能够迅速地散发在电子组件中产生的热。而且,通过将线膨胀系数比电子组件小的部件接合到电子组件的两个面,减小与电子组件的线膨胀差,能够减少作用于电子组件的热应力,而防止其损伤。在该情况下,若绝缘电路基板与引线框的线膨胀系数之差超过5ppm/℃,则由于该线膨胀差而作用于电子组件的热应力变大,因此不优选。
作为本发明的电子组件安装模块的优选的实施方式,可以是如下的实施方式:所述电路层的厚度为t1,所述引线框的厚度为t2,所述厚度t1与所述厚度t2的比率(t1/t2)为0.2以上且5.0以下。并且,引线框可以由铜系低线膨胀材料制成,所述铜系低线膨胀材料具有:复合材料,组合铜与钨、钼、铬或其他低线膨胀率材料而得;及铜板,与该复合材料的两个面接合。电子组件安装模块还可以具有一体地密封所述绝缘电路基板、所述电子组件及所述引线框的模制树脂。
与电子组件相比,铜或铜合金本身的线膨胀系数大,但是绝缘电路基板中,由铜或铜合金制成的电路层以层叠状态接合到陶瓷基板,由此其线膨胀由陶瓷基板的线膨胀控制。因此,作为绝缘电路基板,相较于电子组件成为低线膨胀。在该情况下,若电路层的厚度t1与引线框的厚度t2的厚度比率(t1/t2)小于0.2或者超过5.0,则将由低线膨胀材料制成的绝缘电路基板和引线框配置于电子组件的两个面并使其均衡的效果受损。因此,由电路层或引线框中的厚度较厚的一方的线膨胀成为主导而有可能导致电子组件的破损。
本发明的电子组件安装模块具有:电子组件;第一银烧结接合层,与所述电子组件的一个面接合;绝缘电路基板,具有与所述第一银烧结接合层接合且线膨胀系数比所述电子组件小的垫片、与该垫片接合的第三银烧结接合层、与该第三银烧结接合层接合且由铝或铝合金制成的电路层及与该电路层接合的陶瓷基板;第二银烧结接合层,与所述电子组件的另一个面接合;及引线框,与所述第二银烧结接合层接合,所述引线框的线膨胀系数比所述电子组件小,所述引线框与所述垫片的线膨胀系数之差为5ppm/℃以下。
并且,作为本发明的电子组件安装模块的优选的实施方式,可以是如下的实施方式:所述垫片的厚度为t3,所述引线框的厚度为t2,所述厚度t3与所述厚度t2的比率(t3/t2)为0.2以上且5.0以下。并且,所述垫片及所述引线框可以由铜系低线膨胀材料制成,所述铜系低线膨胀材料具有:复合材料,组合铜与钨、钼、铬或其他低线膨胀率材料而得;及铜板,与该复合材料的两个面接合。电子组件安装模块还可以具有一体地密封所述绝缘电路基板、所述电子组件及所述引线框的模制树脂。
能够通过垫片来调整引线框的高度位置(层叠方向的位置),能够在适合的位置拉出引线框。在该情况下,垫片与引线框的厚度比率(t3/t2)也设定为0.2以上且5.0以下,以免导致电子组件的破损。
根据本发明的电子组件安装模块,通过利用银烧结接合层将线膨胀系数比电子组件小的低线膨胀材料接合到电子组件的两个面,减小两个低线膨胀材料的线膨胀差,能够提高接合可靠性、导热性,并且能够减少作用于电子组件的热应力,而防止其损伤。
附图说明
图1是本发明的第一实施方式的功率模块的剖视图。
图2是表示图1的功率模块的制造方法的流程图。
图3A是说明图2的制造方法中的功率模块用基板形成工序的剖视图。
图3B是功率模块用基板的剖视图。
图3C是说明图2的制造方法中的一并接合工序的剖视图。
图4是说明基底金属层的放大剖视图。
图5是本发明的第二实施方式的功率模块的剖视图。
具体实施方式
以下,参考附图,对本发明的实施方式进行说明。
1.第一实施方式
<整体结构>
第一实施方式中,对将电子组件安装模块适用于功率模块100的例子进行说明。如图1所示,功率模块100具备:半导体元件(本发明的电子组件)30;第一银烧结接合层711,与电子组件30的一个面接合;功率模块用基板(本发明的绝缘电路基板)10,与第一银烧结接合层711接合;第二银烧结接合层712,与半导体元件30的另一个面接合;引线框40,与第二银烧结接合层712接合;及模制树脂50,密封这些半导体元件30、功率模块用基板10及引线框40。
功率模块用基板10具有:垫片20,与第一银烧结接合层711接合;第三银烧结接合层713,与垫片20接合;电路层12,与第三银烧结接合层713接合;及陶瓷基板11,与电路层12接合。半导体元件30的一个面经由第三银烧结接合层713、垫片20及第一银烧结接合层711搭载于功率模块用基板10的电路层12的表面。并且,引线框40经由第二银烧结接合层712与半导体元件30的另一个面接合。
构成功率模块用基板10的陶瓷基板11例如能够使用AlN(氮化铝)、Si3N4(氮化硅)等氮化物系陶瓷或Al2O3(氧化铝)等氧化物系陶瓷。陶瓷基板11的厚度设定在0.2mm~1.5mm的范围内。
电路层12及散热层13由纯度为99.00质量%以上的铝(所谓的2N铝)、纯度为99.99质量%以上的铝(所谓的4N铝)或铝合金形成。电路层12及散热层13的厚度例如设为0.1mm~5.0mm的厚度。电路层12及散热层13通常形成为平面形状比陶瓷基板11小的矩形。并且,电路层12和散热层13通过Al-Si系、Al-Ge系、Al-Cu系、Al-Mg系或Al-Mn系等合金的钎料与陶瓷基板11接合。另外,电路层12和散热层13通过以下任一种方法形成为所期望的形状:将分别通过冲压加工冲切成所期望的外形的电路层12和散热层13接合到陶瓷基板11、或者将平板状的电路层12和散热层13接合到陶瓷基板11之后,通过蚀刻加工形成为所期望的外形。
垫片20由线膨胀系数比半导体元件30小的低线膨胀材料制成,例如由具有复合材料及与该复合材料的两个面接合的铜板的铜系低线膨胀材料制成,所述复合材料通过组合高导热性的铜(Cu)和钨(W)、钼(Mo)、铬(Cr)或其他低线膨胀率材料而得。垫片20的厚度t3可以设在0.5mm~6.0mm的范围内。作为该垫片20,例如,能够使用将厚度为0.1mm~2.0mm的纯铜板接合到厚度为0.3mm~5.0mm的复合材料的两个面的复合板。Cu-Mo的复合材料优选用作复合材料,在该情况下,可以在55质量%~75质量%的范围内含有Mo。Cu-Mo的复合材料通过将混合有Cu粉末和Mo粉末的混合粉末进行成形并进行烧结来形成。
另外,关于铜系低线膨胀材料,能够通过改变低线膨胀材料的含有比率及复合材料与包覆的铜板的厚度比率来调整线膨胀系数及导热系数。关于铜系低线膨胀材料的线膨胀系数,将在后面进行叙述。铜系低线膨胀材料的导热系数例如为180~200W/m·K。
图1中,两个垫片20沿着晶面方向并排接合到电路层12上。
半导体元件30为具备半导体的电子组件。关于半导体元件30,根据所需功能,选择IGBT(Insulated Gate Bipolar Transistor:绝缘栅双极型晶体管)、MOSFET(Metal OxideSemiconductor Field Effect Transistor:金属氧化物半导体场效应晶体管)、FWD(FreeWheeling Diode:续流二极管)等各种半导体元件。在这种半导体元件30的上表面及下表面设置有电极,在电路层12与引线框40之间设为电连接状态。在该情况下,半导体元件30与两个垫片20的每一个接合,在将这些半导体元件30相互连接的状态下设置有引线框40。
引线框40由线膨胀系数比半导体元件30小的低线膨胀材料制成。引线框40例如由与垫片20相同的铜系低线膨胀材料制成,并且形成为带板状。并且,引线框40的线膨胀系数与垫片20的线膨胀系数之差设为5ppm/℃以下。如前所述,关于铜系低线膨胀材料,能够根据复合材料中的铜与低线膨胀材料的含有比率或复合材料与包覆的铜板的厚度比率来调整线膨胀系数等。半导体元件30的线膨胀系数例如为20ppm/℃~30ppm/℃。引线框40的厚度t2可以设在0.05mm以上且3.0mm以下的范围内。并且,为了有效地发挥减小它们的线膨胀系数之差的效果,垫片20的厚度t3与引线框40的厚度t2的厚度比率(t3/t2)设定为0.2以上且5.0以下。
垫片20、半导体元件30、引线框40分别经由银烧结接合层711~713接合到功率模块用基板10的电路层12上。在本实施方式中,这些银烧结接合层711~713中,将接合半导体元件30与垫片20之间的银烧结接合层设为第一银烧结接合层711,将接合半导体元件30与引线框40之间的银烧结接合层设为第二银烧结接合层712,将接合垫片20与电路层12之间的银烧结接合层设为第三银烧结接合层713,区分各银烧结接合层711~713。
并且,为了通过第三银烧结接合层713接合垫片20,在电路层12的接合面形成由金(Au)、银(Ag)、镍(Ni)等制成的基底金属层60。另外,虽然省略图示,但是也可以通过电镀、溅射等在垫片20、半导体元件30、引线框40各自的接合面形成由金、银、镍等制成的基底金属层。
模制树脂50由环氧系树脂等制成。除功率模块用基板10的散热层13的背面以外,模制树脂50一体地密封散热层13的侧面、陶瓷基板11、电路层12、垫片20、半导体元件30及引线框40与半导体元件30的连接部分的周边。引线框40的端部从模制树脂50拉出到外部。
<第一实施方式的制造方法>
接着,对制造如此构成的功率模块100的方法进行说明。如图2所示,该功率模块制造方法通过如下方式来形成:形成功率模块用基板10[功率模块用基板形成工序],在该功率模块用基板10的电路层12的接合预定面形成基底金属层60[基底金属层形成工序]之后,在电路层12上依次层叠垫片20、半导体元件30、引线框40,并将它们一并接合[一并接合工序]之后,使用模制树脂50进行树脂密封[树脂密封工序]。以下,按工序顺序进行说明。
[功率模块用基板形成工序]
如图3A所示,在陶瓷基板11的各面经由钎料15层叠成为电路层12的铝板12′和成为散热层13的铝板13′。并且,将这些层叠结构体在层叠方向上施加压力的状态下进行加热,并使钎料15熔融,由此接合各铝板12′、13′和陶瓷基板11,形成具有电路层12和散热层13的功率模块用基板10(参考图3B)。具体而言,将层叠结构体在施加压力的状态下放入炉中,并在真空气氛中在610℃以上且650℃以下的温度下加热1分钟~60分钟。
[基底金属层形成工序]
在一并接合工序之前,在电路层12的接合预定面形成由金、银、镍等制成的基底金属层60。基底金属层15能够通过利用电镀、溅射将金、银、镍等形成为薄膜状来获得。并且,电路层12的表面的基底金属层60还能够通过涂布含有玻璃的银膏并进行煅烧来形成。
(使用含有玻璃的银膏的基底金属层形成方法)
对使用含有玻璃的银膏在电路层12的表面形成基底金属层60的方法进行说明。含有玻璃的银膏含有银粉末、玻璃(无铅玻璃)粉末、树脂、溶剂及分散剂,由银粉末和玻璃粉末构成的粉末成分的含量设为含有玻璃的银膏整体的60质量%以上且90质量%以下,剩余部分设为树脂、溶剂、分散剂。关于银粉末,其粒径设为0.05μm以上且1.0μm以下,例如优选平均粒径为0.8μm的银粉末。玻璃粉末包含氧化铋(Bi2O3)、氧化锌(ZnO)、氧化硼(B2O3)、氧化铅(PbO2)、氧化磷(P2O5)中的任意一种或两种以上作为主要成分,其玻璃化转变温度设为300℃以上且450℃以下,软化温度设为600℃以下,结晶化温度设为450℃以上。例如,优选含有氧化铅、氧化锌及氧化硼,且平均粒径为0.5μm的玻璃粉末。
并且,银粉末的重量A与玻璃粉末的重量G的重量比A/G调整在80/20至99/1的范围内、例如A/G=80/5。关于溶剂,沸点为200℃以上的溶剂较为合适,例如,可使用二乙二醇二丁醚。树脂用于调整含有玻璃的银膏的粘度,并且在350℃以上分解的树脂较为合适。例如,可使用乙基纤维素。并且,可适当地添加二羧酸系分散剂。可以在不添加分散剂的情况下构成含有玻璃的银膏。
该含有玻璃的银膏通过如下方式来制成:利用混合器将混合银粉末和玻璃粉末而得的混合粉末、及混合溶剂和树脂而得的有机混合物、与分散剂一起进行预混合,一边利用辊式捏合机混炼所获得的预混合物一边进行混合之后,利用浆料过滤器过滤所获得的混炼物。关于该含有玻璃的银膏,其粘度调整为10Pa·s以上且500Pa·s以下,更优选调整为50Pa·s以上且300Pa·s以下。
通过丝网印刷法等将该含有玻璃的银膏涂布于电路层12的接合预定面,干燥之后在350℃以上且645℃以下的温度下经1分钟以上且60分钟以下的时间进行煅烧。由此,如图4所示,形成双层结构的基底金属层60,该双层结构包括形成于接合预定面侧的玻璃层61和形成于该玻璃层61上的银层62。在形成玻璃层61时,熔融去除在电路层12的表面自然发生的氧化铝覆膜12a,在电路层12直接形成玻璃层61,在该玻璃层61上形成银层62。通过该玻璃层61牢固地粘着于电路层12,银层62可靠地保持固定于电路层12上。
含有银或铝中的至少一个的导电性粒子(结晶性粒子)63分散于玻璃层61。推测导电性粒子63在煅烧时析出到玻璃层61内部。并且,微细的玻璃粒子64还分散于银层62的内部。推测该玻璃粒子64是在进行银粒子的煅烧的过程中残留的玻璃成分凝聚而成的。
如此形成的基底金属层60中的银层62的平均晶体粒径调整在0.5μm以上且3.0μm以下的范围内。在此,在煅烧基底金属层60时的加热温度小于350℃及加热温度下的保持时间小于1分钟的情况下,煅烧不足,有可能无法充分地形成基底金属层60。另一方面,在加热温度超过645℃的情况及加热温度下的保持时间超过60分钟的情况下,过度进行煅烧,热处理之后形成的基底金属层60中的银层62的平均晶体粒径有可能不在0.5μm以上且3.0μm以下的范围内。
另外,为了可靠地形成基底金属层60,优选将热处理时的加热温度的下限设为400℃以上,更优选设为450℃以上。并且,加热温度下的保持时间优选设为5分钟以上,更优选设为10分钟以上。另一方面,为了可靠地抑制煅烧的进行,优选将热处理时的加热温度设为600℃以下,更优选设为575℃以下。并且,优选将加热温度下的保持时间设为45分钟以下,更优选设为30分钟以下。
(银膏层)
接着,在将银膏层70介于形成有基底金属层60的电路层12、垫片20、半导体元件30、引线框40之间的状态下,将它们进行层叠。
银膏层70为涂布银膏而形成的层,该银膏含有粒径为0.05μm~100μm的银粉末、树脂及溶剂而成。作为银膏中所使用的树脂,能够使用乙基纤维素等。作为银膏中所使用的溶剂,能够使用α-萜品醇等。作为银膏的组成,银粉末的含量可以设为银膏整体的60质量%以上且92质量%以下,树脂的含量可以设为银膏整体的1质量%以上且10质量%以下,剩余部分可以设为溶剂。
并且,在银膏中还能够含有银膏整体的0质量%以上且10质量%以下的甲酸银、乙酸银、丙酸银、苯甲酸银、草酸银等羧酸系金属盐等的有机金属化合物粉末。并且,根据需要,相对于银膏整体,还能够含有0质量%以上且10质量%以下的醇、有机酸等还原剂。另外,关于该银膏,其粘度调整为10Pa·s以上且100Pa·s以下,更优选调整为30Pa·s以上且80Pa·s以下。
例如通过丝网印刷法等将该银膏分别涂布于电路层12的基底金属层60上、垫片20的表面、引线框40的表面,并进行干燥,由此成为银膏层70。该银膏层70可以形成于接合时对置的接合预定面中的任一个表面。在图3C所示的例子中,在电路层12的表面、垫片20的与半导体元件30对置一侧的表面、引线框40的与半导体元件30对置一侧的表面分别形成有银膏层70。
另外,作为银膏层70,还能够使用将银粉末替换为氧化银粉末的氧化银膏。氧化银膏含有氧化银粉末、还原剂、树脂及溶剂,并且除此以外还含有有机金属化合物粉末。氧化银粉末的含量设为氧化银膏整体的60质量%以上且92质量%以下,还原剂的含量设为氧化银膏整体的5质量%以上且15质量%以下,有机金属化合物粉末的含量设为氧化银膏整体的0质量%以上且10质量%以下,剩余部分设为溶剂。
[一并接合工序]
如图3C所示,以在电路层12的银膏层70上重叠垫片20,在该垫片20的银膏层70上重叠半导体元件30,在该半导体元件30上重叠引线框40的银膏层70的方式将它们设为层叠状态。之后,在层叠方向上作用1MPa以上且20MPa以下的施加压力的状态下加热至180℃以上且350℃以下的温度。该温度的保持时间可以在1分钟以上且60分钟以下的范围内。通过该热处理,银膏层70烧结,在电路层12、垫片20、半导体元件30、引线框40相互之间形成银烧结接合层711~713,利用这些银烧结接合层711~713一体地接合电路层12、垫片20、半导体元件30、引线框40。
另外,在使用由包含氧化银和还原剂的氧化银膏制成的银膏层70的情况下,在接合(煅烧)时,通过氧化银被还原而析出的还原银粒子变得非常微细至例如粒径为10nm~1μm。因此,可形成致密的银烧结接合层711~713,能够更牢固地接合电路层12、垫片20、半导体元件30、引线框40。
[树脂密封工序]
以上述方式,将垫片20、半导体元件30及引线框40接合到功率模块用基板10之后,除功率模块基板10的散热层13的下表面以外,使用模制树脂50一体地密封功率模块用基板10、垫片20、半导体元件30及引线框40的连接部附近。具体而言,例如使用由环氧树脂等制成的密封材料、通过传递模塑方法形成模制树脂50并进行密封。使引线框40的外侧端部从模制树脂50暴露。
如此制造的功率模块100中,半导体元件30在夹在刚性高的功率模块用基板10与引线框40之间的状态下被接合,且被施加压力,由此可抑制翘曲的发生。因此,在不损坏半导体元件30情况下,半导体元件30、功率模块用基板10及引线框40能够获得良好的接合状态。并且,能够将垫片20、半导体元件30、引线框40一次接合到功率模块用基板10,制造也变得容易。
并且,在该功率模块100中,利用第一银烧结接合层711及第二银烧结接合层712将半导体元件30的两个面接合到垫片20及引线框40,因此即使在高温环境下也具有高接合可靠性。并且,各银烧结接合层711、712的导热性优异,因此能够迅速地散发在半导体元件30中产生的热。而且,配置于半导体元件30的两个面的垫片20及引线框40由铜系低线膨胀材料制成,减小这些垫片20及引线框40与半导体元件30的线膨胀差,由此能够减少作用于半导体元件30的热应力,而防止其损伤。
并且,在功率模块100中,通过模制树脂50一体地密封功率模块用基板10、半导体元件30及引线框40。因此,能够通过模制树脂50良好地保持各接合状态,可获得更高的接合可靠性。
2.第二实施方式
图5中示出第二实施方式的功率模块101。在第二实施方式的功率模块101中,没有在第一实施方式中设置的垫片20,半导体元件30的一个面经由第一银烧结接合层711与功率模块用基板16的电路层17接合,引线框40经由第二银烧结接合层712与该半导体元件30的另一个面接合。
图5中,作为电路层17的两个小电路部17a、17b在沿着面方向并排的状态下以层叠状态接合到功率模块用基板16的陶瓷基板1。并且,第一银烧结接合层711分别接合到各小电路部17a、17b上,半导体元件30接合到各第一银烧结接合层711上。
功率模块用基板16的电路层17及散热层18由铜或铜合金构成。铜或铜合金其本身的线膨胀系数相对较大,但是与第一实施方式的铝或其合金相比不易变形。因此,电路层17表面的线膨胀由陶瓷基板11的线膨胀控制。因此,作为功率模块用基板16整体,成为线膨胀系数比半导体元件30小的低线膨胀材料。在本实施方式中,作为电路层17及散热层18,使用无氧铜。
另外,以与第一实施方式相同的方式,引线框40由铜系低线膨胀材料制成,该铜系低线膨胀材料具有组合铜(Cu)和钨(W)、钼(Mo)、铬(Cr)或其他低线膨胀率材料而得的复合材料、及与复合材料的两个面接合的铜板。并且,该功率模块用基板16与引线框40的线膨胀系数之差设定为5ppm/℃以下。并且,功率模块用基板15的电路层16的厚度t1与引线框40的厚度t2的厚度比率(t1/t2)设定为0.2以上且5.0以下。
在功率模块101中,功率模块用基板16通过如下方式来制作:经由银钛(Ag-Ti)系钎料、银铜钛(Ag-Cu-Ti)系钎料等活性金属钎料将电路层17及散热层18层叠于陶瓷基板11的两个面,并在层叠方向上作用例如0.05MPa以上且1.0MPa以下的施加压力的状态下加热至800℃以上且930℃以下。之后,在将银膏层介于电路层17、半导体元件30、引线框40的各接合预定面的状态下进行层叠,并以与第一实施方式相同的方式一并加压、加热,由此经由第一银烧结接合层711接合电路层12和半导体元件30,经由第二银烧结接合层712接合半导体元件30和引线框40。最后,使用模制树脂50一体地密封功率模块用基板16与半导体元件30及引线框40的连接部附近。
该实施方式的功率模块用基板16的电路层17由铜或铜合金制成,因此无需设置形成于由第一实施方式的铝或其合金制成的电路层12的基底金属层60,但是可以形成相同的基底金属层。并且,可以通过电镀、溅射等在半导体元件30、引线框40的各接合预定面形成金、银、镍等的基底金属层。
如此制造的功率模块101中,配置于半导体元件30的两个面的引线框40及功率模块用基板15由线膨胀系数比半导体元件30小的铜系低线膨胀材料构成。因此,能够减少作用于半导体元件30的热应力,而有效地防止其破损。并且,功率模块101中,通过模制树脂50一体地密封功率模块用基板16和与功率模块用基板16接合的半导体元件30及引线框40,因此能够通过模制树脂50良好地保持各接合状态,可获得更高的接合可靠性。
除此以外,本发明并不限定于上述实施方式,能够在不脱离本发明的趣旨的范围内施加各种变更。
实施例
关于功率模块用基板的电路层、垫片、引线框,准备表1所示的材质、厚度的功率模块用基板的电路层、垫片、引线框,在它们的对置的接合预定面中的任一个面涂布银膏之后,将它们进行层叠并进行了一并接合。在该情况下,关于发明例1~发明例4、比较例1,使用上述的含有玻璃的银膏在由铝制成的电路层的表面形成了基底金属层。发明例5、发明例6及比较例2中,不使用垫片,而将半导体元件接合到电路层。无论在哪种情况下,接合时的温度均设为300℃,荷载均设为10MPa。
在ESPEC CORP.制造的液槽冷热冲击装置中,对接合了该半导体元件的功率模块实施了1000次低温侧-40℃、高温侧150℃的循环的冷热冲击试验,并评价了有无半导体元件的破损。关于有无半导体元件的破损,使用Insight CO.,LTD.制造的超声波图像诊断装置,将在半导体元件观察到裂纹的概率为10%以下的情况设为“良”,将在半导体元件观察到裂纹的概率超过10%的情况设为“不良”。
将这些结果示于表2中。并且,表1中,“4N-Al”表示纯度为99.99质量%以上的铝,“C1020”表示无氧铜,“Cu-Mo”表示纯铜/铜钼复合材料/纯铜的包覆材料,“Cu-W”表示纯铜/铜钨复合材料/纯铜的包覆材料。
[表1]
[表2]
根据表1及表2明确可知,半导体元件的两个面的材料的线膨胀系数差在5ppm/℃以内,且厚度比率(t1/t2)或厚度比率(t3/t2)为0.2以上且5.0以下的功率模块中,未确认到半导体元件的破损。
产业上的可利用性
经由银烧结接合层将线膨胀系数比电子组件小的低线膨胀材料接合到电子组件的两个面,减小两个低线膨胀材料的线膨胀差,由此能够提高电子组件安装模块的接合可靠性、导热性,并且能够减少作用于电子组件的热应力,而防止其损伤。
符号说明
10-功率模块用基板(绝缘电路基板),11-陶瓷基板,12-电路层,13-散热层,15-钎料,16-功率模块用基板(铜系低线膨胀材料、绝缘电路基板),17-电路层,17a、17b-小电路部,18-散热层,20-垫片(铜系低线膨胀材料),30-半导体元件(电子组件),40-引线框(铜系低线膨胀材料),50-模制树脂,60-基底金属层,61-玻璃层,62-银层,70-银膏层,711-第一银烧结接合层,712-第二银烧结接合层,713-第三银烧结接合层,100、101-功率模块(电子组件安装模块)。
Claims (8)
1.一种电子组件安装模块,其特征在于,具有:
电子组件;
第一银烧结接合层,与所述电子组件的一个面接合;
绝缘电路基板,具有与所述第一银烧结接合层接合且由铜或铜合金制成的电路层和与该电路层接合的陶瓷基板,所述绝缘电路基板的线膨胀系数比所述电子组件小;
第二银烧结接合层,与所述电子组件的另一个面接合;及
引线框,与所述第二银烧结接合层接合,所述引线框的线膨胀系数比所述电子组件小,所述引线框与所述绝缘电路基板的线膨胀系数之差为5ppm/℃以下。
2.根据权利要求1所述的电子组件安装模块,其特征在于,
所述电路层的厚度为t1,所述引线框的厚度为t2,所述厚度t1与所述厚度t2的厚度比率、即t1/t2为0.2以上且5.0以下。
3.根据权利要求1所述的电子组件安装模块,其特征在于,
所述引线框由铜系低线膨胀材料制成,
所述铜系低线膨胀材料具有:
复合材料,组合铜与钨、钼、铬或其他低线膨胀率材料而得;及
铜板,与该复合材料的两个面接合。
4.根据权利要求1所述的电子组件安装模块,其特征在于,还具有一体地密封所述绝缘电路基板、所述电子组件及所述引线框的模制树脂。
5.一种电子组件安装模块,其特征在于,具有:
电子组件;
第一银烧结接合层,与所述电子组件的一个面接合;
绝缘电路基板,具有与所述第一银烧结接合层接合且线膨胀系数比所述电子组件小的垫片、与该垫片接合的第三银烧结接合层、与该第三银烧结接合层接合且由铝或铝合金制成的电路层及与该电路层接合的陶瓷基板;
第二银烧结接合层,与所述电子组件的另一个面接合;及
引线框,与所述第二银烧结接合层接合,所述引线框的线膨胀系数比所述电子组件小,所述引线框与所述垫片的线膨胀系数之差为5ppm/℃以下。
6.根据权利要求5所述的电子组件安装模块,其特征在于,
所述垫片的厚度为t3,所述引线框的厚度为t2,所述厚度t1与所述厚度t2的厚度比率、即t3/t2为0.2以上且5.0以下。
7.根据权利要求5所述的电子组件安装模块,其特征在于,
所述垫片及所述引线框由铜系低线膨胀材料制成,
所述铜系低线膨胀材料具有:
复合材料,组合铜与钨、钼、铬或其他低线膨胀率材料而得;及
铜板,与该复合材料的两个面接合。
8.根据权利要求5所述的电子组件安装模块,其特征在于,还具有一体地密封所述绝缘电路基板、所述电子组件及所述引线框的模制树脂。
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