CN1116701C - 半导体器件的制造方法 - Google Patents
半导体器件的制造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 19
- 238000009413 insulation Methods 0.000 claims description 17
- 239000012535 impurity Substances 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 29
- 239000002184 metal Substances 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 6
- 239000002994 raw material Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 206010034133 Pathogen resistance Diseases 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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Abstract
本发明揭示一种半导体器件的制造方法,包括在半绝缘性半导体基片上有选择地形成电阻区域,在该电阻区域的两端部上有选择地形成欧姆电极。在电极间形成有开口部的光刻胶,使完全不横穿电阻区域。借助于一点一点不断地蚀刻除去所述开口内的电阻区域,得到所要的电阻值。本发明的半导体器件的制造方法,能事先防止电阻值变得无限大,能改善电阻值的控制性和均匀性,并能提高原材料的利用率。
Description
技术领域
本发明涉及在半绝缘性基片上形成的半导体器件的制造方法,特别涉及调整电阻值的电阻形成方法。
背景技术
在以往的电极间的电阻形成方法中,在电阻区域上利用光刻胶形成电阻调整用的开口部,借助于在开口部蚀刻电阻区域,在对电流进行监视的同时、得到所要的电阻值。
下面,参照图3所示的剖视图(A1~F1)和平面图(A2~F2)、对以往的基于使用光刻胶图形的电阻值调整法的电阻形成方法进行说明。
首先,在GaAs等的半绝缘性基片1上形成具有开口部2的光刻胶3,在半绝缘性基片1上进行杂质的离子注入,形成高杂质浓度的电阻接触区域4(图3的A1,A2)。
接着,除去光刻胶6,在半绝缘性基片1上形成具有开口部5的新的光刻胶6。然后,在半绝缘性基片1上进行杂质的离子注入,形成低杂质浓度的电阻接触区域7(图3的B1,B2)。
接着,除去光刻胶6,在半绝缘性基片1上形成具有电极形成用开口部8的光刻胶9(图3的C1,C2)。
接着,在形成金属膜后,除去光刻胶9,由剥离法形成欧姆电极10(图3的D1,D2)。
接着,在半绝缘性基片1上形成具有横穿电阻区域7的电阻调整用的开口部11的光刻胶12,在电阻区域7上施行蚀刻后,在测定电阻值的同时进行调整、以便成为所要的电阻值(图3的E1,E2)。
最后,借助于除去光刻胶12,形成电阻值被调整的电极间的电阻(图3的F1,F2)。
但是,在前述的电阻形成方法中,如图3的E2所示,因形成完全地横穿电阻区域7的光刻胶12的开口部11,所以如图4所示,在通过开口部11对电阻区域7进行蚀刻,并在监视电流的同时进行电阻值的调整时,因从某个蚀刻时间开始电阻值急剧地增高,所以仅仅稍微超过蚀刻调整时间就会穿通电阻区域7,使电阻成为无限大的电阻值
如图4所示,因用于使电阻值符合设计值范围的蚀刻时间以秒为单位非常地短,所以其问题在于,由于电阻值很难控制,其电阻值离散性较大,因此使合格率降低。
发明内容
为了提高原材料利用率,一般、在集成电路的电阻形成中,要求改善电极间的电阻值的控制性。本发明的目的是谋求在这种电极间的电阻形成中改善电阻值的控制性。
用于解决这种问题的本发明的电阻形成方法,包括:在半绝缘性半导体基片上利用离子注入或者扩散杂质有选择地形成电阻区域,在电阻区域的两端部上形成电极,在表面形成膜后、形成不横穿所述电阻区域的膜的开口部,借助于在开口部蚀刻露出的所述电阻区域、进行所述电阻区域的电阻值的调整。
因此,即使蚀刻达到穿通电阻区域的程度,电阻值也不会变成无限大,同时因能有充足的时间进行用于与设定值相符合的电阻值的调整的蚀刻,所以能谋得扩散电阻值的控制性的改善和原材料利用率的提高。
本发明第一方面的半导体器件制造方法,其特征在于,包括下述工序:
在半绝缘性基片上有选择地形成电阻区域的工序;
在所述电阻区域的两端部形成电极的工序;
在所述基片表面成膜后,形成多个不横穿所述电阻区域的、所述膜的开口部时使得其中2个开口部交错跨过所述电阻区域两侧部位的工序;以及
通过蚀刻所述开口部露出的所述电阻区域,对所述电阻区域的电阻值进行调整的工序。
本发明第二方面的半导体器件制造方法,在第一方面的基础上其特征在于,所述形成电阻区域的工序,通过离子注入杂质或扩散杂质形成。
按照本发明第一方面,所形成的开口部交错跨过电阻区域两侧部位,使电流路径形成为类似锯齿形状而变长,因而可取得通过蚀刻对电流路径长度的变动以抑制电阻值误差这种效果。
附图说明
图1表示本发明实施例的电阻形成方法的流程图。
图2表示本发明的对于蚀刻时间的薄膜电阻值的变化。
图3表示以往的电阻形成方法的流程图。
图4表示以往的对于蚀刻时间的薄膜电阻值的变化。
具体实施方式
下面,参照图1和图2对本发明的实施例进行说明。
实施例
下面,参照图1所示的剖视图(A1~F1)和平面图(A2~F2)、对本发明实施例的基于使用完全不横穿电阻区域的光刻胶图形的电阻值调整法的电阻形成方法进行说明。
首先,在GaAs等半导体的半绝缘性基片1上形成具有开口部2的光刻胶3,利用在半绝缘性基片1上进行杂质的离子注入或者杂质的扩散,形成高杂质浓度的电阻接触区域4(图1的A1,A2)。
接着,除去光刻胶3,在半绝缘性基片1上形成具有电阻区域形成用的开口部5的新的光刻胶6。然后,以光刻胶6作为掩模,在半绝缘性基片1上进行离子注入或者扩散,形成低杂质浓度的电阻区域7(图1的B1,B2)。
然后,除去光刻胶6,在半绝缘性基片1上形成具有电极形成用的开口部8的新的光刻胶9(图1的C1,C2)。
接着,在表面形成AuGeNi等的金属膜后,除去光刻胶9,由剥离法形成欧姆电极10(图1的D1,D2)。
接着,在半绝缘性基片1上形成具有不横穿电阻区域7的2个电阻调整用的开口部13的光刻胶14,浸润在蚀刻液中,并在开口部13对电阻区域7施行蚀刻。然后,从蚀刻液中取出半绝缘性基片1,将探针与一部分被开口的电极接触、流过电流,测定是否成为所要的电阻值。如果没有成为所要的电阻值,则再次进行蚀刻,然后取出并测定电阻值。借助于重复这种工序,进行调整、以便成为所要的电阻值(图1的E1,E2)。
最后,借助于除去光刻胶14,形成电阻值被调整后的电极间的电阻(图1的F1,F2)。
图2表示由本发明的实施例得到的蚀刻时间与薄膜电阻值的关系。
由图可知,与以往的电阻形成方法相比(参照图4),在本发明的电阻形成方法中,对于蚀刻时间的电阻值变化率小。为此,如图2的斜线部分所示,用于与设计值范围内的电阻值相符合的蚀刻时间比过去要长,所以即使稍稍超过蚀刻时间,电阻值也能保持在设计值内,能谋得电阻值的均匀性的改善和原材料利用率的提高。
因利用用于电阻值调整的蚀刻,即使例如穿通电阻区域,也能防止电阻值成为无限大,所以能比以往更安全地容易地进行电阻值调整。
此外,在实施例中,借助于形成例如2个电阻值调整用的开口部那样,形成偶数个开口部,能使电阻形状对称而取得平衡。但是,也可以将电阻值调整用的开口部的个数做成奇数个,尽管电阻的形状为非对称但前述的效果不变。
采用本发明的电阻形成方法,则因用于在设计值内的电阻值调整的蚀刻时间十分充足,并且用于电阻值调整用的蚀刻,即使导致例如穿通电阻区域,电阻值也不会成为无限大,所以容易进行电阻值的调整,同时因电阻值的离散性减小,所以能求得原材料利用率的提高。
Claims (2)
1.一种半导体器件制造方法,其特征在于,包括下述工序:
在半绝缘性基片上有选择地形成电阻区域的工序;
在所述电阻区域的两端部形成电极的工序;
在所述基片表面成膜后,形成多个不横穿所述电阻区域的、所述膜的开口部时使得其中2个开口部交错跨过所述电阻区域两侧部位的工序;以及
通过蚀刻所述开口部露出的所述电阻区域,对所述电阻区域的电阻值进行调整的工序。
2.如权利要求1所述的半导体器件制造方法,其特征在于,所述形成电阻区域的工序,通过离子注入杂质或扩散杂质形成。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP043234/1997 | 1997-02-27 | ||
JP9043234A JPH10242394A (ja) | 1997-02-27 | 1997-02-27 | 半導体装置の製造方法 |
JP043234/97 | 1997-02-27 |
Publications (2)
Publication Number | Publication Date |
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CN1192039A CN1192039A (zh) | 1998-09-02 |
CN1116701C true CN1116701C (zh) | 2003-07-30 |
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Application Number | Title | Priority Date | Filing Date |
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CN98105298.3A Expired - Fee Related CN1116701C (zh) | 1997-02-27 | 1998-02-27 | 半导体器件的制造方法 |
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US (1) | US6245628B1 (zh) |
JP (1) | JPH10242394A (zh) |
CN (1) | CN1116701C (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7884442B2 (en) | 2004-08-13 | 2011-02-08 | Raytheon Company | Integrated circuit resistor |
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US8546884B2 (en) * | 2002-10-29 | 2013-10-01 | Avago Technologies General Ip (Singapore) Pte. Ltd. | High value resistors in gallium arsenide |
US7911318B2 (en) * | 2007-02-16 | 2011-03-22 | Industrial Technology Research Institute | Circuit boards with embedded resistors |
CN106298117A (zh) * | 2015-06-11 | 2017-01-04 | 大量科技股份有限公司 | 电阻元件及其阻值修整方法 |
DE102016101248A1 (de) * | 2015-11-02 | 2017-05-04 | Epcos Ag | Sensorelement und Verfahren zur Herstellung eines Sensorelements |
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-
1997
- 1997-02-27 JP JP9043234A patent/JPH10242394A/ja active Pending
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1998
- 1998-02-26 US US09/031,039 patent/US6245628B1/en not_active Expired - Fee Related
- 1998-02-27 CN CN98105298.3A patent/CN1116701C/zh not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7884442B2 (en) | 2004-08-13 | 2011-02-08 | Raytheon Company | Integrated circuit resistor |
Also Published As
Publication number | Publication date |
---|---|
US6245628B1 (en) | 2001-06-12 |
CN1192039A (zh) | 1998-09-02 |
JPH10242394A (ja) | 1998-09-11 |
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