CN1114943C - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN1114943C CN1114943C CN99125526A CN99125526A CN1114943C CN 1114943 C CN1114943 C CN 1114943C CN 99125526 A CN99125526 A CN 99125526A CN 99125526 A CN99125526 A CN 99125526A CN 1114943 C CN1114943 C CN 1114943C
- Authority
- CN
- China
- Prior art keywords
- layer
- film
- copper interconnection
- interconnection layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010410 layer Substances 0.000 claims abstract description 109
- 239000010949 copper Substances 0.000 claims abstract description 89
- 229910052802 copper Inorganic materials 0.000 claims abstract description 89
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 87
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract 7
- 229910003481 amorphous carbon Inorganic materials 0.000 claims abstract 5
- 229910052731 fluorine Inorganic materials 0.000 claims abstract 4
- 239000011737 fluorine Substances 0.000 claims abstract 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract 4
- 238000000034 method Methods 0.000 claims description 39
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 18
- 239000001301 oxygen Substances 0.000 claims description 18
- 229910052760 oxygen Inorganic materials 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 10
- 230000000694 effects Effects 0.000 claims description 10
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract 1
- 239000006117 anti-reflective coating Substances 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 86
- 238000002310 reflectometry Methods 0.000 description 7
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 4
- 229910000077 silane Inorganic materials 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- VFQHLZMKZVVGFQ-UHFFFAOYSA-N [F].[Kr] Chemical compound [F].[Kr] VFQHLZMKZVVGFQ-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 150000001879 copper Chemical class 0.000 description 2
- 229960004643 cupric oxide Drugs 0.000 description 2
- 230000008595 infiltration Effects 0.000 description 2
- 238000001764 infiltration Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910016570 AlCu Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000005211 surface analysis Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
在本发明中,在此公开一种半导体器件,其铜互连层形成多级结构;其特征在于至少一个位于铜互连层之间的层间膜具有层状结构,其中按照次序从下层铜互连层一侧叠放一含氟的无定形碳膜与一SiO2膜;一层状结构,其中按次序叠放氮化硅,然后叠放氮氧化硅或碳化硅;或者包括单氮化硅层的的一种结构。这种层间膜作为防反射涂层。
Description
技术领域
本发明涉及一种半导体器件及其制造方法,特别涉及一种用于避免来自具有铜多级互连层的半导体器件中的较低级铜互连层的反射的方法。
背景技术
近几年来,人们不断尝试在大规模集成电路器件中实现更高的速度和更高的集成度,在此产生不但要在晶体管中而且还要在该互连层中实现进一步小型化和更密集的空间分布的需要。
作为金属互连材料,到目前为止主要采用铝,但是这已知会导致电迁移(EM)的问题;即,由于互连层的电流密度增加以及由整个器件所产生的热量而造成的温度升高使得在互连层中的一些金属原子发生运动,这在一些部位产生空缺,这些原子从该空缺移走并且因此会产生互连层的断开。另外,在金属原子积累的一些部分形成称为小丘的颗粒,并且对位于该互连层上的绝缘层产生应力,这可能会造成裂缝。
为了解决该问题,人们已经提出可以采用在铝中掺有非常少量的硅或铜的合金,但是如果要进一步实现小型化和更密集的空间分布的话,即使这样还不够,因此人们考虑使用仍然具有更高的可靠性的铜互连层。
在金属材料中,铜具有仅次于银的第二最小电阻率(银的电阻率为1.7-1.8μΩ-cm,而AlCu的电阻率为3.1μΩ-cm),并且具有优良的EM阻抗。从而,在实现更密集的空间分布的过程中,非常需要利用这些铜的特性的新技术。
例如,铜被用作为互连材料的技术公开于IEDM’97,pp.769-772中名为“利用铜金属化的高性能1.8V 0.2μm的CMOS技术”的文章,以及在IEDM’97,pp.769-772中名为“在低于0.25μm的CMOS超大规模集成电路技术中的完全铜布线”的文章。
铜是相对较难以通过蚀刻形成图案的金属。特别是在应用于低于0.25μm量级的半导体器件中,铜必须通过镶嵌金属化技术(在下文中简称为“镶嵌技术”)形成。
例如,这是按照图7中所示执行的。首先,在第一层间绝缘膜71上形成第一互连槽72(图7(a)),然后通过电镀方法、CVD(化学汽相淀积)方法等等在其上淀积阻挡金属层73和铜74(图7(b))。接着,通过化学机械抛光(CMP)方法进行抛光直到第一层间绝缘膜71的表面暴露出来,并且通过铜表面的平面化,以镶嵌形式完成第一级互连层75(图7(c))。为了在其上形成另一个铜互连层,在生长第二层间绝缘膜76之后,通过光刻方法形成与第一级互连层75相接触的第二互连槽78以及通孔77(图7(d)),然后按照类似方式用铜通过镶嵌形成第二级互连层79(图7(e))。顺便提一下,在上文所述的后一实例中,其中提到当形成测试芯片时形成作为倒装片模块的顶层铜互连层。
铜是相对较易被氧化的金属。当另一个铜互连层如上文所述置于较低层的铜互连层之上时,例如,如果采用氧化硅作为层间绝缘膜,则在形成氧化硅膜中(这通常是通过在氧化环境中利用硅烷进行的),下层铜也受到氧化。结果,在被氧化的铜表面上同时形成氧化硅膜,这可能发生薄膜的脱落,这导致不一定形成规定的层间绝缘膜的问题。对于上述实例,没有提到具体采用什么金属,但是这给出一个在形成氧化膜之后形成阻蚀层(氮化硅或类似材料通常被用作为该阻蚀层)的实例。
另外,当通过光刻对该层间绝缘膜进行构图时,如上文所述,光刻胶由于来自下层互连层的反射而曝光过度,这会造成不能形成规定图案的问题。上述氮化硅膜通常被用作为不具有防反射效果的阻蚀层。随着互连图案小型化的继续该问题会变得更加尖锐,并且需要一种适当的解决措施。
为了避免来自普通金属互连层的反射,采用SiON膜是一种公知的方法。在此,SiON膜的形成通常是在300至400℃左右的基片温度中把氧化氮气体或者氮气和氧气的混合物添加到硅烷气中而进行的。但是,如果这在铜互连层之上在这样的条件下进行SiON膜的形成,则在形成上述SiO2膜的情况下铜表面被氧化,从而产生不能够形成规定的防反射涂层(ARC)的问题。
发明内容
本发明提供一种可以克服上述问题的半导体器件。
就上述问题而言,本发明涉及一种半导体器件,其铜互连层形成多级结构;其特征在于至少一个位于铜互连层一侧的层间膜是具有防反射特性的单层或层状结构,与铜互连层接触的层是在不使用氧的条件下形成的。
另外,本发明涉及一种制造具有多层铜互连层的半导体器件的方法;其中包括如下步骤:在一铜互连层上形成一绝缘层;通过利用光刻工艺对所述绝缘层构图形成槽和/或通孔;在所述槽内通过镶嵌技术形成另一个铜互连层,和/或在所述通孔内形成与下层铜互连层连接的接触插件,从而以镶嵌的形式完成上级铜互连层;其特征在于所述绝缘层包含具有防反射效果的单层或层状结构的层间膜,与下层铜互连层接触的一层绝缘膜的形成是在不使用氧的条件下完成的。
在本发明中,当用于通过镶嵌技术形成铜互连层的槽或通孔被形成在另一个铜互连层上时,在该下层铜互连层上的膜的形成在无氧条件下执行,并且即使当用氧执行膜的形成时,该铜表面保持不被氧化,另外这样形成的膜具有防反射效果,使得可以易于实现互连图案的小型化。
附图说明
图1(a)至图1(d)为示出本发明一个实施例的制造方法的步骤的一系列示意截面图。
图2为示出本发明一个实施例的多级互连结构的示意截面图。
图3为示出在铜表面上的氧化铜的厚度与基片温度之间的关系的曲线图。
图4为示出当a-C:F膜形成在铜膜的表面上并且(b)在400℃和(c)在450℃的温度下在该膜上形成SiO2膜时,铜膜表面的成分分布的一组SIMS(二次离子质谱分析)图。图4(a)表示在退火以前的状态。
图5为示出在铜表面上形成(a)a-C:F膜、(b)SiN膜、以及(c)不形成其它膜的几种情况下,反射率与波长之间的关系的一组曲线图。
图6为示出本发明的另一个实施例的多级互连结构的示意截面图。
图7(a)至图7(e)为示出常规多级互连结构的制造方法的步骤的示意截面图。
具体实施方式
在本发明中,一层具有防氧化的保护效果的膜在无氧条件下形成,然后形成防反射涂层(ARC),或者在无氧条件下形成ARC。在效果上,形成ARC,而铜互连层表面被防止氧化,使得不被剥落,从而可以进一步使互连图案小型化。
图5为示出铜互连层的反射率与波长的关系的一组曲线图,在一例子中,SiN膜(厚度为500nm)形成在铜互连层上作为阻蚀层,并且在作为本发明一个实施例的例子中,a-C:F膜(厚度为500nm)形成在铜互连层上。从图中可以清楚看出,在用于光刻工艺中的i-线(360nm)和氪氟激光(248nm)的波长处的反射率比较表明,铜表面的反射率与其上形成有SiN膜的样本的反射率接近于40%,而根据本发明具有a-C:F膜的样本的反射率对于i-线为5%或更小,对于氪氟激光为10%或更小。尽管在本例中a-C:F膜形成厚度为500nm,但是该反射率不取决于该膜厚,并且该膜具有与其膜厚无关的防反射效果。
在空气中加热,当基片温度超过150℃,铜表面通常瞬间被氧化(图3中的曲线A)。与此相反,在铜表面上形成a-C:F膜(厚度为100nm)抑制该氧化过程(图3中的曲线B)。但是必须注意,a-C:F膜本身允许氧通过并且氧化下层的铜,如图中所示。但是,当在所述a-C:F膜上形成SiO2膜时,在SiO2膜形成开始时,一些氧可能通过该膜并氧化铜表面,但是一但形成SiO2膜,该SiO2膜阻止氧的渗透,从而停止进一步的氧化,使得铜和a-C:F膜紧紧地相互附着而没有障碍。
对于a-C:F膜的膜厚没有具体的限制。但是,由于太薄的膜具有让氧通过并氧化下层的铜的趋势,因此该膜优选至少具有50nm的厚度,最好具有100nm或更厚的厚度。其最大值可以根据设计而适当设定。
另外,在SiN膜作为防止氧渗透的保护层而形成并且在其上形成有SiON膜或SiC膜的情况下,SiN膜形成具有类似于作为通常阻蚀层的厚度即可,即,至少为50nm,最好为100nm左右。并且,对于形成在SiN膜上的SiON膜或SiC膜,所需膜厚同样为至少50nm并且最好为100nm左右。另外,在SiC膜的情况,由于在膜形成过程中不使用氧,因此该膜可以直接形成在铜互连层上,以同样作为ARC。
第一实施例
首先,参照附图描述作为本发明一个实施例的形成多级铜互连层的方法。
在基片1上形成SiO2膜2之后,形成厚度为500nm左右的a-C:F膜3。在其上,通过CVD方法进一步形成200nm厚的SiO2膜4(图1(a))。在按该方法形成的SiO2膜4上,施加一层光刻胶5,然后通过光刻方法构图。接着,在a-C:F膜3和SiO2膜4上通过蚀刻形成要用于通过镶嵌技术形成铜互连层的槽(宽度为0.15μm,深度为0.2μm)(图1(b))。在形成有槽6的基片的整个表面上,通过溅射方法或类似方法形成厚度为150nm的TiN膜7作为阻挡膜,通过CVD方法或类似方法在其上形成铜膜8(图1(c))。通过CMP(化学机械抛光)方法对铜膜8和TiN膜7进行抛光,直到SiO2膜2暴露出来,从而完成铜互连层9(图1(d))。
另外,在按这种方式形成的铜互连层9上,按照如上文所述的相同方式,在a-C:F膜3和SiO2膜4上通过蚀刻形成用于通过镶嵌技术形成另一个铜互连层的另一个槽和/或另一个通孔,类似地形成阻挡膜和铜膜,然后对该表面进行平面化。重复这些步骤,则可完成多级互连层。
图4示出通过对该样本进行SIMS(二次离子质谱测定法)的表面分析的结果,其中该样本形成有a-C:F膜,并且然后分别在400℃和450℃的退火温度下形成SiO2膜。在这种情况下,各个样本的SiO2膜在测量之前被除去。如图中所示,与退火之前相比,确认该铜表面在任何一个温度下退火之后几乎不被氧化。
在本实例中,如上述图5中所示,由于a-C:F膜3具有特别强的防反射效果,该光刻胶不会在光刻的时候破裂,从而可以成功地形成微小的图案。
同时,在如上文所述完成多级互连层之后,适合地对作为顶级层覆盖层10(可能具有与所述层间绝缘膜相同的成份)进行蚀刻,从而形成接合区部分12和熔丝部分11。在此,如图2所示,通过至少用除了铜之外一种合适的互连材料(在本例中为铝)形成熔丝部分11,并且最好形成这两个部分,可以获得如下优点。即,当施加可能对元件产生反作用的过量电流时,所述熔丝部分被熔断,从而该电路得到保护。另外,如果接合区部分也是由除了铜之外的材料所形成,则可以采用廉价的金丝接合13。如果成本允许的话,该接合区部分可以由铜形成,在这种情况下,作为常规实例,可以形成引线凸起以进行倒装片接合。不用说,可以用除了铜之外的其它金属形成的接合区部分进行倒装片接合。另外,尽管在图中所示的铜互连层9具有四层结构,应当知道这不是对本发明的限制。
第二实施例
参照图6,下面描述本发明的第二实施例。图6为示出本实施例的铜多级互连层的示意截面图。
在象SiO2膜61这样形成在一基片上的绝缘膜中,形成要通过镶嵌技术形成铜互连层的槽,然后如第一实施例那样形成一阻挡膜。通过CMP方法类似地对该表面进行平面化,从而完成第一级互连层62。接着,利用硅烷气和氨气通过CVD方法在该第一级互连层62上生长一层厚度为150nm的SiN膜63,在该膜上进一步利用硅烷气和氧化氮生长一层厚度为150nm的SiON膜。接着,在形成象SiO2膜65或类似的膜这样的绝缘膜之后,通过光刻方法形成要通过镶嵌技术形成第二级互连层66的另一个槽和/或另一个通孔。在其上,成功地形成规定的槽,而不从下层互连层接收反射或使得该光刻胶破裂。在此之后,按照如上文所述的相同方法形成阻挡膜和铜的镶嵌,并且从而形成第二级互连层66。进一步按照相同的方法重复这些步骤,可以完成镶嵌形式的多级互连层。另外,尽管在图6中所示的互连层仅有三层,但是应当知道该互连结构可以具有任何规定的级数。另外,如上文所述,通过至少用除了铜之外的其他合适材料形成顶层的熔丝部分,可以按上文所述完成具有优良特性的半导体器件。
另外,当使用SiC膜取代SiN膜时,可以获得类似的效果。另外,即使表面即使没有形成SiON膜,SiC膜本身可以获得足够的防反射效果。
Claims (12)
1.一种半导体器件,其铜互连层形成多级结构;其特征在于至少一个位于铜互连层一侧的层间膜是具有防反射特性的单层或层状结构,与铜互连层接触的层是在不使用氧的条件下形成的。
2.根据权利要求1所述的半导体器件,其特征在于,层间膜为层状结构,该层状结构中含氟的无定形碳膜和SiO2膜从下面的铜互连层的一侧按照该顺序叠放。
3.根据权利要求2所述的半导体器件,其特征在于所述层状结构位于形成在半导体基片上的氧化硅膜上,和通过镶嵌技术在所述层状结构中形成铜互连层,从而完成第一级互连。
4.根据权利要求1所述的半导体器件,其特征在于层间膜具有层状结构,其中氮化硅和氮氧化硅按照该次序从下层铜互连层一侧叠放。
5.根据权利要求1所述的半导体器件,其特征在于层间膜具有层状结构,其中氮化硅和碳化硅按照该次序从下层铜互连层一侧叠放。
6.根据权利要求所述的半导体器件,其特征在于层间膜是包括碳化硅层的单层。
7.一种制造具有多层铜互连层的半导体器件的方法;其中包括如下步骤:
在一铜互连层上形成一绝缘层;
通过利用光刻工艺对所述绝缘层构图形成槽和/或通孔;
在所述槽内通过镶嵌技术形成另一个铜互连层,和/或在所述通孔内形成与下层铜互连层连接的接触插件,从而以镶嵌的形式完成上级铜互连层;
其特征在于所述绝缘层包含具有防反射效果的单层或层状结构的层间膜,与下层铜互连层接触的一层绝缘膜的形成是在不使用氧的条件下完成的。
8.根据权利要求7所述的制造半导体器件的方法,其中层间膜为层状结构,该层状结构中含氟的无定形碳膜和SiO2膜按该顺序从下层铜互连层的一侧形成,无定形碳膜是在不使用氧的条件下形成的。
9.根据权利要求8所述的制造半导体器件的方法;其中进一步包括如下步骤:
在半导体基片上形成的氧化硅膜上形成由含氟的无定形碳膜和SiO2膜构成的层状结构;和
以镶嵌形式在所述层状结构中形成一个铜互连层,从而完成第一级互连。
10.根据权利要求7所述的制造半导体器件的方法,其中绝缘膜为层状结构,该层状结构中氮化硅和氮氧化硅按该顺序从下层铜互连层的一层叠放,并且氮化硅是在不使用氧的条件下形成的。
11.权利要求7所述的制造半导体器件的方法,其中绝缘膜为层状结构,该层状结构中氮化硅和碳化硅按该顺序从下层铜互连层的一层叠放,并且氮化硅和碳化硅是在不使用氧的条件下形成的。
12.根据权利要求7所述的制造半导体器件的方法,其中层间膜是包括在不使用氧的条件下形成的碳化硅层的单层。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34603198A JP3177968B2 (ja) | 1998-12-04 | 1998-12-04 | 半導体装置及びその製造方法 |
JP346031/1998 | 1998-12-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1256512A CN1256512A (zh) | 2000-06-14 |
CN1114943C true CN1114943C (zh) | 2003-07-16 |
Family
ID=18380675
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN99125526A Expired - Fee Related CN1114943C (zh) | 1998-12-04 | 1999-12-02 | 半导体器件及其制造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20010045655A1 (zh) |
JP (1) | JP3177968B2 (zh) |
KR (1) | KR100368568B1 (zh) |
CN (1) | CN1114943C (zh) |
GB (3) | GB2344464B (zh) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002043423A (ja) | 2000-07-24 | 2002-02-08 | Tokyo Ohka Kogyo Co Ltd | 被膜の処理方法およびこの方法を用いた半導体素子の製造方法 |
TW523792B (en) | 2000-09-07 | 2003-03-11 | Toshiba Corp | Semiconductor device and its manufacturing method |
US7170115B2 (en) * | 2000-10-17 | 2007-01-30 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device and method of producing the same |
US6465889B1 (en) * | 2001-02-07 | 2002-10-15 | Advanced Micro Devices, Inc. | Silicon carbide barc in dual damascene processing |
JP4124315B2 (ja) | 2001-05-01 | 2008-07-23 | 東京応化工業株式会社 | 被膜の処理方法およびこの方法を用いた半導体素子の製造方法 |
JP3530149B2 (ja) * | 2001-05-21 | 2004-05-24 | 新光電気工業株式会社 | 配線基板の製造方法及び半導体装置 |
KR100421278B1 (ko) * | 2001-06-26 | 2004-03-09 | 주식회사 하이닉스반도체 | 반도체소자의 제조방법 |
US20030027413A1 (en) * | 2001-08-01 | 2003-02-06 | Ting Tsui | Method to improve the adhesion of dielectric layers to copper |
DE10156865A1 (de) * | 2001-11-20 | 2003-05-28 | Infineon Technologies Ag | Verfahren zum Ausbilden einer Struktur in einem Halbleitersubstrat |
US20040079726A1 (en) * | 2002-07-03 | 2004-04-29 | Advanced Micro Devices, Inc. | Method of using an amorphous carbon layer for improved reticle fabrication |
JP4290953B2 (ja) * | 2002-09-26 | 2009-07-08 | 奇美電子股▲ふん▼有限公司 | 画像表示装置、有機el素子および画像表示装置の製造方法 |
CN101580928B (zh) * | 2003-02-26 | 2012-07-18 | 住友电气工业株式会社 | 无定形碳膜及其制备方法以及无定形碳膜涂敷的材料 |
DE10339988B4 (de) * | 2003-08-29 | 2008-06-12 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer antireflektierenden Schicht |
CN100456462C (zh) * | 2003-10-09 | 2009-01-28 | 飞思卡尔半导体公司 | 具有增强光刻胶黏性的无定形碳层的器件及其制造方法 |
JP4478038B2 (ja) | 2004-02-27 | 2010-06-09 | 株式会社半導体理工学研究センター | 半導体装置及びその製造方法 |
KR100539257B1 (ko) * | 2004-04-07 | 2005-12-27 | 삼성전자주식회사 | 패턴 형성을 위한 반도체 구조 및 패턴 형성 방법 |
US20060244156A1 (en) * | 2005-04-18 | 2006-11-02 | Tao Cheng | Bond pad structures and semiconductor devices using the same |
FR2910703B1 (fr) * | 2006-12-22 | 2009-03-20 | St Microelectronics Sa | Dispositif imageur dote d'un dernier niveau d'interconnexion a base de cuivre et d'aluminium |
CN101958310B (zh) * | 2009-07-16 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及半导体器件的形成方法 |
JP6209164B2 (ja) * | 2012-10-02 | 2017-10-04 | 日本碍子株式会社 | モジュール電池 |
US9087841B2 (en) * | 2013-10-29 | 2015-07-21 | International Business Machines Corporation | Self-correcting power grid for semiconductor structures method |
CN103646912A (zh) * | 2013-11-13 | 2014-03-19 | 上海华力微电子有限公司 | 通孔优先铜互连制作方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08148563A (ja) * | 1994-11-22 | 1996-06-07 | Nec Corp | 半導体装置の多層配線構造体の形成方法 |
JPH0945769A (ja) * | 1995-07-28 | 1997-02-14 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JPH1027844A (ja) * | 1996-07-10 | 1998-01-27 | Fujitsu Ltd | 半導体装置 |
JP3997494B2 (ja) * | 1996-09-17 | 2007-10-24 | ソニー株式会社 | 半導体装置 |
US6310300B1 (en) * | 1996-11-08 | 2001-10-30 | International Business Machines Corporation | Fluorine-free barrier layer between conductor and insulator for degradation prevention |
JP3228183B2 (ja) * | 1996-12-02 | 2001-11-12 | 日本電気株式会社 | 絶縁膜ならびにその絶縁膜を有する半導体装置とその製造方法 |
JPH10223758A (ja) * | 1996-12-06 | 1998-08-21 | Sony Corp | 半導体装置 |
US6104092A (en) * | 1997-04-02 | 2000-08-15 | Nec Corporation | Semiconductor device having amorphous carbon fluoride film of low dielectric constant as interlayer insulation material |
US6291334B1 (en) * | 1997-12-19 | 2001-09-18 | Applied Materials, Inc. | Etch stop layer for dual damascene process |
-
1998
- 1998-12-04 JP JP34603198A patent/JP3177968B2/ja not_active Expired - Fee Related
-
1999
- 1999-12-02 US US09/452,926 patent/US20010045655A1/en not_active Abandoned
- 1999-12-02 CN CN99125526A patent/CN1114943C/zh not_active Expired - Fee Related
- 1999-12-03 KR KR10-1999-0054686A patent/KR100368568B1/ko not_active IP Right Cessation
- 1999-12-03 GB GB9928740A patent/GB2344464B/en not_active Expired - Fee Related
-
2003
- 2003-10-27 GB GBGB0325009.9A patent/GB0325009D0/en not_active Ceased
- 2003-10-27 GB GBGB0325008.1A patent/GB0325008D0/en not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
GB2344464B (en) | 2004-02-25 |
GB9928740D0 (en) | 2000-02-02 |
GB0325008D0 (en) | 2003-11-26 |
GB2344464A (en) | 2000-06-07 |
KR20000047888A (ko) | 2000-07-25 |
US20010045655A1 (en) | 2001-11-29 |
CN1256512A (zh) | 2000-06-14 |
JP2000174023A (ja) | 2000-06-23 |
GB0325009D0 (en) | 2003-11-26 |
KR100368568B1 (ko) | 2003-01-24 |
JP3177968B2 (ja) | 2001-06-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1114943C (zh) | 半导体器件及其制造方法 | |
CA1248641A (en) | Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias | |
JP2811131B2 (ja) | 半導体装置の配線接続構造およびその製造方法 | |
KR100550304B1 (ko) | 하이드로겐-실세스퀴옥산(hsq)으로 갭이 채워진 패터닝된 금속층들을 갖는 경계없는 비아들 | |
EP0788156B1 (en) | Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD | |
US6368967B1 (en) | Method to control mechanical stress of copper interconnect line using post-plating copper anneal | |
EP1324383A2 (en) | Semiconductor device and method for manufacturing the same | |
JP3149846B2 (ja) | 半導体装置及びその製造方法 | |
US20050285272A1 (en) | Conductive structures in integrated circuits | |
EP0903781B1 (en) | Method of forming embedded copper interconnections | |
US5909635A (en) | Cladding of an interconnect for improved electromigration performance | |
US6638849B2 (en) | Method for manufacturing semiconductor devices having copper interconnect and low-K dielectric layer | |
EP0628998B1 (en) | Wiring layer for semi conductor device and method for manufacturing the same | |
US20100190335A1 (en) | Method of manufacturing semiconductor device | |
TWI227046B (en) | Process of metal interconnects | |
CN1315177C (zh) | 半导体器件及其制造方法 | |
US7446037B2 (en) | Cladded silver and silver alloy metallization for improved adhesion and electromigration resistance | |
US20010048162A1 (en) | Semiconductor device having a structure of a multilayer interconnection unit and manufacturing method thereof | |
US6319727B1 (en) | Method for manufacturing low stress metallic interconnect lines for use in integrated circuits | |
US6340638B1 (en) | Method for forming a passivation layer on copper conductive elements | |
JPH0621236A (ja) | 半導体装置およびその製造方法 | |
JP2002184858A (ja) | 半導体素子の製造方法 | |
KR930011541B1 (ko) | 반도체 장치의 평탄화 방법 | |
KR0167282B1 (ko) | 반도체 장치의 다층배선 형성방법 | |
KR0166826B1 (ko) | 반도체 소자의 층간 절연막 형성방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: NEC ELECTRONICS TAIWAN LTD. Free format text: FORMER OWNER: NIPPON ELECTRIC CO., LTD.; Effective date: 20040204 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20040204 Address after: Kanagawa, Japan Patentee after: NEC Corp. Address before: Tokyo, Japan Patentee before: NEC Corp. |
|
C19 | Lapse of patent right due to non-payment of the annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |