CN111276468B - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN111276468B
CN111276468B CN201911226106.2A CN201911226106A CN111276468B CN 111276468 B CN111276468 B CN 111276468B CN 201911226106 A CN201911226106 A CN 201911226106A CN 111276468 B CN111276468 B CN 111276468B
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die
conductive
forming
bottom wafer
front side
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CN111276468A (zh
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余振华
刘醇鸿
陈明发
史朝文
叶松峯
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

形成半导体结构的方法包括将顶部管芯的背面附接至底部晶圆的正面，底部晶圆包括多个底部管芯；在底部晶圆与顶部管芯相邻的正面上形成第一导电柱；在顶部管芯周围和第一导电柱周围的底部晶圆的正面上形成第一介电材料；并且切割底部晶圆以形成多个结构，多个结构中的每一个均包括至少一个顶部管芯和至少一个底部管芯。本发明的实施例还涉及半导体结构。

Description

半导体结构及其形成方法
技术领域
本发明的实施例涉及半导体结构及其形成方法。
背景技术
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体工业经历了快速的增长。在大部分情况下，集成密度的提高来自最小部件尺寸的不断减小，这使得更多的组件可以集成至给定区域中。
随着对缩小电子器件的需求的增长，已经出现了对更小且更具创造性的半导体管芯封装技术的需求。这种封装系统的一个实例是叠层封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部上，以提供高的集成度和组件密度。另一个实例是衬底上晶圆上芯片(CoWoS)结构，其中，半导体芯片附接至晶圆(例如，中介层)以形成晶圆上芯片(CoW)结构。然后将CoW结构附接至衬底(例如，印刷电路板)以形成CoWoS结构。这些以及其它先进的封装技术使得能够生产具有增强功能和小占位面积的半导体器件。
集成扇出(InFO)封装技术正变得越来越流行，特别是与晶圆级封装(WLP)技术接合使用时。使用InFO封装技术的封装结构可提供具有相对较低成本的高功能密度和高性能封装件。
发明内容
本发明的一些实施例提供了一种形成半导体结构的方法，所述方法包括：将顶部管芯的背面附接至底部晶圆的正面，所述底部晶圆包括多个底部管芯；在所述底部晶圆的与所述顶部管芯相邻的正面上形成第一导电柱；在所述顶部管芯周围和所述第一导电柱周围的所述底部晶圆的正面上形成第一介电材料；以及切割所述底部晶圆以形成多个结构，所述多个结构中的每一个均包括至少一个顶部管芯和至少一个底部管芯。
本发明的实施例还提供了一种形成半导体结构的方法，所述方法包括：形成集成电路器件，其中，形成所述集成电路器件包括：将第二管芯的背面附接至第一管芯的正面，其中，所述第一管芯在所述第一管芯的正面处具有第一导电焊盘，所述第一导电焊盘设置在所述第二管芯的边界外部；在所述第一管芯的正面和所述第二管芯周围形成介电材料；在所述介电材料中形成电连接至所述第一管芯的第一导电焊盘的第一导电柱；在所述介电材料上形成电连接至所述第二管芯和所述第一导电柱的再分布结构；以及在所述再分布结构上方形成连接件；将所述集成电路器件的连接件附接至中介层的第一侧；以及在所述集成电路器件周围的所述中介层的第一侧上形成模制材料；以及在所述中介层的第二侧上形成导电凸块。
本发明的另一实施例提供了一种半导体结构，包括：第一管芯，在所述第一管芯的第一侧具有第一导电焊盘；第二管芯，具有远离所述第一管芯的第一侧，并且具有附接至所述第一管芯的所述第一侧的第二侧，所述第二管芯在所述第二管芯的第一侧处具有第二导电焊盘；第一导电柱，附接至所述第一管芯的第一导电焊盘并且与所述第二管芯相邻；第一介电材料，位于所述第一管芯的所述第一侧上和所述第二管芯周围以及所述第一导电柱周围，其中，所述第一介电材料与所述第一管芯共末端；再分布结构，位于所述第一介电材料上，并且电连接至所述第二管芯的所述第一导电柱和所述第二导电焊盘；以及外部连接件，位于所述再分布结构的远离所述第二管芯的第一侧上。
附图说明
当接合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图3示出了根据实施例的形成多个管芯的工艺。
图4至图7示出了根据实施例的用于测试底部晶圆的电路探测工艺。
图8和图9示出了底部晶圆的额外实施例。
图10至图17示出了根据实施例的处于制造的各个阶段的半导体结构的截面图。
图18示出了根据实施例的半导体结构的截面图。
图19A和图19B示出了根据实施例的半导体结构的截面图。
图20A和图20B示出了根据实施例的半导体结构的截面图。
图21至图27示出了根据实施例的处于制造的各个阶段的集成芯片上系统(SoIC)的截面图。
图28至图33示出了根据实施例的处于制造的各个阶段的集成芯片上系统(SoIC)的截面图。
图34至图36、图37A、图37B和图38至图42示出了根据实施例的处于制造的各个阶段的半导体结构的截面图。
图43至图46、图47A、图47B、图48、图49和图50A至图50C示出了集成芯片上系统(SoIC)的各个实施例的截面图。
图51示出了在一些实施例中的用于形成半导体结构的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。在本文的整个说明书中，除非另有说明，否则不同附图中的相同参考标号指的是使用相同或类似材料通过相同或类似形成方法形成的相同或类似组件。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
在形成在导线之间具有精细间距和用于高性能应用的良好散热的堆叠半导体结构的上下文中讨论了本发明的实施例，高性能应用诸如现场可编程门阵列(FPGA)、图形处理单元(GPU)、存储器件等。在一些实施例中，为了形成集成芯片上系统(SoIC)，顶部管芯的背面通过熔融接合工艺接合至底部管芯的正面。导电柱形成在处于底部管芯的正面并且与顶部管芯相邻的底部管芯的接合焊盘上。介电材料形成在顶部管芯周围和导电柱周围的底部管芯的正面上。然后在介电材料上方形成再分布结构。可以集成SoIC以形成不同的半导体封装件，诸如具有衬底上晶圆上芯片(CoWoS)结构的封装件或集成扇出(InFO)封装件。
图1至图3示出了形成顶部管芯50的工艺，该顶部管芯50可以附接至底部管芯100以在随后的处理中形成集成芯片上系统(SoIC)(例如，见图11中的集成电路器件150)。首先参考图1，器件区域40形成在衬底51(例如，晶圆)中或衬底上。每个器件区域40中的导电部件互连以形成相应的顶部管芯的功能电路，并且随后的切割工艺将分割衬底51以形成多个顶部管芯50，如下文所讨论的。
衬底51可以是半导体衬底，诸如掺杂或未掺杂的硅，或者绝缘体上半导体(SOI)衬底的有源层。衬底51可以包括其它半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、氮化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用其它衬底，诸如多层或梯度衬底。诸如晶体管、二极管、电容器、电阻器的器件可以形成在衬底51内和/或衬底51上(例如，形成在器件区域40中)，并且可以通过金属化层53互连以形成功能电路。金属化层53可以包括使用诸如沉积、镶嵌、双镶嵌等或它们的组合的合适形成方法在衬底51上方的一个或多个介电层中形成的金属化图案(例如，金属线和通孔)。注意，为简单起见，在后续附图中可以不示出器件区域40。
可以在金属化层53上方形成第一钝化层(未示出)，以为下面的结构提供保护。第一钝化层可以由一种或多种合适的介电材料制成，诸如氧化硅、氮化硅、诸如碳掺杂的氧化物的低k电介质、诸如多孔碳掺杂的二氧化硅的极低k电介质、这些的组合等。第一钝化层可以通过诸如化学汽相沉积(CVD)的工艺形成，但是可以利用任何合适的工艺。
导电焊盘(例如，铝焊盘，未示出)可以形成在金属化层53上方并且与金属化层53电接触。导电焊盘可以延伸穿过第一钝化层以电连接至金属化层53。导电焊盘可以包括铝，但是可以可选地使用诸如铜的其它材料。可以使用诸如溅射的沉积工艺来形成导电焊盘，以形成材料层，并且然后可以通过合适的工艺(诸如光刻掩膜和蚀刻)去除材料层的部分，以形成导电焊盘。然而，可以利用任何其它合适的工艺来形成导电焊盘。
在第一钝化层上方形成包括合适的介电材料的第二钝化层52。第二钝化层52可以是诸如聚苯并恶唑(PBO)、聚酰亚胺(PI)、低温聚酰亚胺(LPTI)、苯并环丁烯(BCB)等的聚合物，并且可以通过旋涂、层压、化学汽相沉积(CVD)等形成。形成管芯连接件55，该管芯连接件55延伸穿过第二钝化层52以电连接至相应的导电焊盘。管芯连接件55可以是诸如铜柱的导电柱，并且可以通过诸如镀等形成。
在一些实施例中，在形成管芯连接件55之后，通过管芯连接件55的电路探测工艺来测试衬底51中的多个顶部管芯50，以识别已知良好管芯(KGD)。已知良好管芯用于在后续工艺中形成SoIC 150。
下一步，在图2中，第二钝化层52通过粘合剂层56附接至载体57。载体57可以由诸如玻璃、硅、聚合物、聚合物复合材料、金属箔、陶瓷、环氧玻璃、氧化铍、胶带的材料或用于结构支撑的其它合适的材料制成。在一些实施例中，粘合剂层56沉积或层压在载体57上方。在一些实施例中，粘合剂层56是管芯附接膜(DAF)。
下一步，实施减薄工艺以减小衬底51的厚度。使用研磨工艺和/或化学机械平坦化(CMP)工艺从衬底51的背面(例如，图2中的衬底51的下侧)实施减薄工艺。在一些实施例中，衬底的厚度从例如约780μm减小至在约1μm和约100μm之间(诸如约40μm)的厚度H1。
下一步，在衬底51的背面上方形成可选的氮化物层59，诸如氮化硅层。可以使用低温沉积工艺来形成氮化物层59，并且可以将其称为低温氮化硅层。在沉积之后，可以例如通过CMP工艺来平坦化氮化物层59。在一些实施例中，省略氮化物层59。氮化物层59可用于在随后的熔融接合工艺中在例如顶部管芯50和底部晶圆100’(见图10)之间形成更牢固的接合。
下一步，在图3中，将图2所示的结构附接至由框架63(例如，金属框架)支撑的切割带61上，并且通过载体剥离工艺去除载体57。在剥离载体57之后，可以实施清洁工艺(例如，DAF清洁工艺)以去除粘合剂层56的剩余部分。下一步，实施切割工艺以分割衬底51，并且形成多个顶部管芯50。形成管芯连接件55的图3中的顶部管芯50的上侧称为顶部管芯50的正面，并且图3中的顶部管芯50的下侧称为顶部管芯50的背面。
图4至图7示出了用于测试底部晶圆100’的电路探测工艺，该电路探测工艺之后，该底部晶圆100’将在随后的工艺中被分割以形成用于形成SoIC(见例如图11)的多个底部管芯100。参考图4，提供了底部晶圆100’，其包括衬底101、器件区域41(与图1中的器件区域40相同或类似)和位于衬底101的正面上方的金属化层108。图4进一步示出了位于金属化层108上方的一次性探测焊盘121。注意，为简单起见，在图4中未示出底部晶圆100’的所有部件，并且在后续附图中可能未示出器件区域41。
图5示出了图4的底部晶圆100’的部分106的放大图。如图5所示，底部晶圆100’包括衬底101、金属化层108、第一钝化层116、第二钝化层118、导电焊盘128、再分布线119和再分布通孔117。另外，图5示出了位于相应的导电焊盘128上方并且电连接至的相应的导电焊盘128的一次性探测焊盘121，以及位于一次性探测焊盘121上的焊帽123。
在图5的实例中，金属化层108包括下部金属化层108A和上部金属化层108B。下部金属化层108A包括由例如极低K(ELK)材料形成的多个介电层111，以及形成在介电层111中的导电部件(例如，金属线112、通孔110)。上金属化层108B包括由例如未掺杂的硅酸盐玻璃(USG)形成的多个介电层114，以及形成在介电层114中的导电部件(例如，金属线115、通孔113)。在一些实施例中，上部金属化层108B中的导电部件(例如，线、通孔)的尺寸(例如，金属线/通孔的厚度和/或宽度，或相邻金属线或通孔之间的间隔)大于下部金属化层108A中的导电部件的相应尺寸。金属化层108、第一钝化层116、第二钝化层118和导电焊盘128的形成方法与顶部管芯50的那些相同或类似，因此不再重复细节。
如图5所示，再分布线119(例如，金属线)形成在第一钝化层116上方并且附接至导电焊盘128(例如，铝焊盘)。再分布线119将导电焊盘128处的电信号重新布线至不同的位置，并且通过再分布通孔117电连接至例如金属化层108的最顶部金属部件(例如115)。如图5所示，再分布通孔117延伸穿过第一钝化层116，并且将再分布线119电连接至金属化层108。一次性探测焊盘121可以是铜柱，其延伸穿过第二钝化层118以电连接至相应的导电焊盘128。
在一些实施例中，第二钝化层118是具有约1000埃的厚度的氮化硅层，导电焊盘128是铝焊盘，其厚度(垂直于衬底101的上表面的方向测量)在约0.5μm和约5μm之间，诸如2.8μm。一次性探测焊盘121是铜柱，其厚度在约0.5μm和约10μm之间，诸如1μm，并且焊帽123(例如，无铅焊料区域)的厚度在约1μm和约20μm之间，诸如2μm。
在一些实施例中，实施电路探测工艺以测试底部晶圆100’中的管芯的功能，以识别已知良好管芯。电路探测工艺通过一次性探测焊盘121实施。在底部晶圆100’中识别出的已知良好管芯将用于形成SoIC。
下一步，在图6中，在完成用于底部晶圆100’的电路探测工艺之后，去除一次性探测焊盘121和焊帽123，并且暴露导电焊盘128。例如，可以实施使用硫酸(例如，H2SO4)的湿蚀刻工艺以去除一次性探测焊盘121和焊帽123。
下一步，在图7中，在第二钝化层118上方和导电焊盘128上方形成一个或多个介电层(例如，125和127)。例如，介电层125由诸如正硅酸乙酯(TEOS)的氧化物形成。在一些实施例中，介电层127由与介电层125相同的材料(例如，氧化物)形成。在其它实施例中，介电层127由与介电层125不同的介电材料形成。例如，介电层127可以由与介电层125不同的氧化物形成，诸如USG或高密度等离子体(HDP)化学汽相沉积氧化物。可以实施诸如CMP的平坦化工艺以平坦化所沉积的介电层125/127。
下一步，在介电层127/125中形成接合焊盘107。图7中的每个接合焊盘107包括焊盘金属(BPM)107T和焊盘通孔(BPV)107V。接合焊盘107由诸如铜的导电材料使用双镶嵌工艺形成。如图7所示，接合焊盘107从介电层127的上表面延伸至导电焊盘128。接合焊盘107的上表面与介电层127的上表面平齐，并且接合焊盘107的下表面接触导电焊盘128。在随后的工艺中，在接合焊盘107上形成导电柱131(见图10)以电连接至金属化层108。图7中的金属化层108和金属化层108上方的结构(诸如第一钝化层116、第二钝化层118、导电焊盘128、再分布线119、再分布通孔117、介电层125/127和接合焊盘107)可以统称为互连结构105。
在一些实施例中，焊盘金属107T的高度(沿垂直于衬底101的上表面的方向测量)在约0.1μm和约2μm之间，诸如0.85μm，并且焊盘通孔107V的高度在约0.5μm和约5μm之间，诸如2.4μm。
图8示出了接合焊盘107的另一实施例，其中，每个接合焊盘107在接合焊盘107的顶面和底面之间具有基本均匀的宽度。图8中的接合焊盘107可以通过单镶嵌工艺形成。
图9示出了接合焊盘107的又一实施例。图9中的接合焊盘107与图7中的那些类似，但是图9中的接合焊盘107直接连接至金属化层108中的顶部金属层Mz(例如，最顶部金属层)。换句话说，虽然图7和图8中的接合焊盘107直接连接至导电焊盘128，但是图9中的接合焊盘107直接连接至金属化层108的顶部金属层Mz。由于图9中的接合焊盘107在介电层127下方延伸地更深，因此图9中的焊盘通孔107V的高度(沿垂直于衬底101的上表面的方向测量)可以大于图7的高度，诸如具有约6μm的值。
注意，图7至图9示出了底部晶圆100’的部分，其中在底部晶圆100’的上表面处形成接合焊盘107。底部晶圆100’的上表面具有没有形成接合焊盘107的其它区域。在随后的工艺中，在一些实施例中，顶部管芯50将通过熔融接合工艺接合至底部晶圆100’的上表面的区域，而无需接合焊盘107。
图10至图17示出了根据实施例的处于制造的各个阶段的半导体封装件500(见图17)的截面图。半导体封装件500具有叠层封装(PoP)结构，并且包括附接至底部封装件510的顶部封装件520。底部封装件510是具有集成芯片上系统(SoIC)150(见图11)的集成扇出(InFO)封装件。下文将细节讨论。
参考图10，通过熔融接合工艺将多个顶部管芯50(诸如来自图3的已知良好管芯50)被附接至底部晶圆100’(诸如图7至图9中所示的那些)的正面。在所示的实施例中，在没有接合焊盘107的区域中，通过熔融接合工艺将顶部管芯50的背面接合至底部晶圆100’的最顶部介电层(例如，127)，其中最顶部介电层(例如，127)是诸如氧化硅层的氧化物层。在一些实施例中，在熔融接合工艺之前，施加机械应力以将顶部管芯50和底部晶圆100’压在一起。下一步，通过将顶部管芯50和底部晶圆100’加热至在约200℃和约500℃之间的温度来实施熔融接合工艺。熔融接合室(在熔融接合工艺中顶部管芯50和底部晶圆100’所在的位置)的压力可以在约0.1Torr和约100Torr之间。
回想在图2中，可以在顶部管芯50的背面上形成氮化物层59(例如，氮化硅层)。在顶部管芯50的背面上形成氮化物层59的实施例中，熔融接合工艺在氮化物层59和底部晶圆100’的最顶部介电层(例如，氧化硅层)之间形成接合。在省略氮化物层59的实施例中，熔融接合工艺在顶部管芯50的衬底的材料(例如，硅)和底部晶圆100’的最顶部介电层(例如，氧化硅层)之间形成接合。在一些实施例中，在氮化硅和氧化硅之间的接合比硅和氧化硅之间的接合更强，并且因此，在顶部管芯50的背面上形成氮化物层59提供了在顶部管芯50和底部晶圆100’之间的更牢固的接合。
仍然参考图10，在将顶部管芯50接合至底部晶圆100’之后，在底部晶圆的接合焊盘107上形成导电柱131。可以通过在底部晶圆100’上方形成具有开口的图案化掩模层(例如，图案化的光刻胶)来形成导电柱131，其中开口的位置对应于要形成的导电柱131的位置，并且开口暴露出下面的接合焊盘107。下一步，通过例如镀工艺在图案化的掩模层的开口中形成诸如铜的导电材料。在用导电材料填充开口之后，然后使用诸如灰化的合适的去除方法去除图案化的掩模层(例如，图案化的光刻胶)。导电柱131在随后的工艺中由介电材料围绕之后变成通孔。
在一些实施例中，导电柱131的高度H2在约10μm和约100μm之间，诸如约30μm。导电柱131的宽度在约10μm和约50μm之间，诸如约30μm，并且相邻的导电柱131之间的间距在约20μm和约100μm之间，诸如约70μm。
下一步，在图11中，在导电柱131周围和顶部管芯50周围的底部晶圆100’的正面上方形成介电材料133。介电材料133可以是聚酰亚胺、低温聚酰亚胺、模制材料等，并且可以通过例如涂覆工艺(诸如，旋涂)形成。在形成介电材料133之后，将载体附接至介电材料133，并且通过例如研磨工艺从背面减薄底部晶圆100’。
在背面研磨工艺之后，将底部晶圆100’的背面附接至切割带，并且实施切割工艺以将底部晶圆100’分成底部管芯100并且形成多个集成电路器件150。在实施例中，集成电路器件150是SoIC。每个SoIC 150包括底部管芯100、附接至底部管芯100正面的顶部管芯50、位于底部管芯100正面上的导电柱131，以及介电材料133。尽管图11仅示出了两个SoIC150，但是在切割工艺之后形成的SoIC 150的数量可以是任何合适的数量。另外，附接至底部管芯100的顶部管芯50的数量和SoIC 150的结构可以变化以具有不同的结构，其细节在下文中讨论。
在图11的实例中，SoIC 150包括顶部管芯50和底部管芯100，其中，顶部管芯50的背面附接至底部管芯100的正面。因此，SoIC 150也被称为具有背对面接合结构，或者被称为背对面SoIC。导电柱131形成在接合焊盘107上方。导电柱131和顶部管芯50由介电材料133围绕，该介电材料133与底部管芯100横向共末端。换句话说，介电材料133的侧壁与底部管芯100的相应侧壁对准。在一些实施例中，SoIC 150的高度H3在约100μm和约300μm之间，诸如约180μm。
下一步，在图12中，在载体135上方依次形成粘合剂层137和背面介电层139。载体135支撑形成在其上的半导体结构，并且可以由诸如硅、聚合物、聚合物复合材料、金属箔、陶瓷、玻璃、玻璃环氧树脂、氧化铍、带的材料或其它用于结构支撑的材料制成。在一些实施例中，载体135是玻璃载体。在一些实施例中，粘合剂层137沉积或层压在载体135上方。粘合剂层137可以是光敏的，并且可以通过在随后的载体剥离工艺中将例如紫外(UV)光照射在载体135上而容易地与载体135分离。例如，粘合剂层137可以是由明尼苏达州圣保罗的3M公司制造的光热转换(LTHC)涂层。
在一些实施例中，背面介电层139可以用作缓冲层，并且可以由诸如聚酰亚胺(PI)、聚苯并恶唑(PBO)或苯并环丁烯的聚合物制成。可以使用本领域中已知的任何合适方法，诸如物理汽相沉积(PVD)、化学汽相沉积(CVD)、印刷、旋涂、喷涂、烧结等来形成背面介电层139。
下一步，在背面介电层139上方形成牺牲材料(未示出)。牺牲材料可以包括例如光刻胶、有机材料、绝缘材料或其它材料，并且可以通过PVD、CVD、旋涂或其它合适的沉积技术来形成。使用例如光刻工艺或直接图案化工艺，将牺牲材料图案化为具有用于形成导电柱141的图案或开口。下一步，牺牲材料中的开口填充有导电材料以形成导电柱141。导电材料可以包括铜(Cu)，但是也可以使用其它合适的导电材料。在一些实施例中，镀工艺用于在牺牲材料的开口中形成导电材料。可以在镀工艺之前形成晶种层。镀工艺例如可以包括电化学镀(ECP)、化学镀或其它类型的镀工艺。在镀工艺之后，剥离或去除牺牲材料，并且在背面介电层139上方形成导电柱141，如图12所示。导电柱141在随后的工艺中由模制材料围绕之后变成通孔。导电柱141的高度H4可以在约100μm和约300μm之间，诸如约200μm。导电柱141的宽度可以在约50μm和约300μm之间，诸如约190μm，并且相邻的导电柱141之间的间距可以在约100μm和约400μm之间，诸如约300μm。
下一步，在图13中，使用诸如DAF的粘合剂膜146将诸如在图11的工艺之后形成的那些的多个SoIC 150附接至背面介电层139。
下一步，在图14中，将模制材料143设置在背面介电层139上方以及SoIC 150和导电柱141周围。例如，在模制材料143的自上而下视图中，模制材料143可以环绕SoIC 150和导电柱141。在图14的实例中，模制材料143围绕SoIC 150并且接触(例如，物理接触)介电材料133的侧壁。
模制材料143可以包括任何合适的材料，诸如环氧树脂、模制底部填充物等。用于形成模制材料143的合适的方法可以包括压缩模制、传递模制、液体密封模制等。在形成模制材料143之后，可以实施诸如CMP的平坦化工艺以实现用于模制材料143的水平上表面。在平坦化工艺之后，在模制材料143的上表面处暴露导电柱141、导电柱131和管芯连接件55。导电柱141在由模制材料143围绕之后变成通孔。
下一步，在图15中，再分布结构148形成在模制材料143上方，并且电连接至导电柱141、导电柱131和顶部管芯50的管芯连接件55。再分布结构148包括导电部件，诸如一层或多层导线147和形成在一个或多个介电层145中的通孔149。在一些实施例中，一个或多个介电层145由诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物形成。一个或多个介电层145可以通过任何可接受的沉积工艺形成，诸如旋涂、化学汽相沉积(CVD)、层压等或它们的组合。
在一些实施例中，再分布结构148的导电部件包括由诸如铜、钛、钨、铝等的合适的导电材料形成的导线147和通孔149。可以通过例如在介电层145中形成开口以暴露下面的导电部件，在介电层145上方和开口中形成晶种层，在晶种层上方形成具有设计图案的图案化光刻胶，在设计图案中和晶种层上方镀(例如，电镀或化学镀)导电材料，并且去除光刻胶和晶种层的其上未形成导电材料的部分来形成导电部件。
如图15所示，顶部管芯50和底部管芯100之间的通信通过再分布结构148进行。例如，来自底部管芯100的电信号在进入顶部管芯50的管芯连接件55之前，通过导电柱131行进至再分布结构148。
仍参考图15，在焊盘161上方形成电连接至再分布结构148的导电部件的外部连接件163(也可以称为导电凸块)。外部连接件163可以是焊球，诸如球栅阵列(BGA)球、可控塌陷芯片连接(C4)凸块、微凸块等。在一些实施例中，一个或多个集成无源器件(IPD)167电连接至微焊盘165，该微焊盘165电连接至再分布结构148的导电部件。在图15的实例中，IPD器件167的连接件168通过例如焊料区域接合至微焊盘165，并且底部填充材料162可以填充IPD器件167和再分布结构148之间的间隙。IPD器件中可以集成多种无源器件，诸如平衡转换器、连接器、分离器、滤波器和双工器。IPD器件可以替代传统的分立式表面安装器件(SMD)，以减小占位面积，降低成本并且提高性能。
下一步，在图16中，将图15所示的半导体结构翻转，并且将外部连接件163附接至例如由框架153支撑的切割带151。下一步，在载体剥离工艺中去除载体135。例如，可以通过化学湿蚀刻、等离子体干蚀刻、机械剥离、CMP、机械研磨、热烘烤、激光扫描或湿剥离来剥离载体135。在一些实施例中，载体135是玻璃载体，并且通过在玻璃载体上照射紫外线来剥离。在载体剥离之后，在背面介电层139中形成开口138以暴露导电柱141。开口138可以通过蚀刻工艺、激光钻孔工艺或其它合适的工艺形成。图16所示的半导体结构包括多个半导体封装件510。在随后的工艺中，沿着切割线154切割图16所示的半导体结构，以形成多个单独的半导体封装件510(也称为底部封装件，见图17)。
下一步，在图17中，将多个半导体封装件520(也称为顶部封装件)附接至图16所示的半导体结构。每个半导体封装件520与对应的半导体封装件510对准，使得半导体封装件520的外部连接件274的位置与导电柱141的顶面的位置匹配。每个半导体封装件520可以包括附接至衬底271的一个或多个管芯279，其中，管芯279周围具有模制塑料277。衬底271在衬底271的上表面和下表面上分别具有导电焊盘273和275。导电部件(例如，金属线、通孔)可以形成在衬底271中，并且将导电焊盘273与导电焊盘275电连接。在一些实施例中，在附接半导体封装件520之前，使用例如焊料印刷机将焊膏136沉积在导电柱141的暴露顶面上。在将半导体封装件520附接至半导体封装件510之后，可以实施回流工艺以将半导体封装件520接合至相应的半导体封装件510。可以形成底部填充材料166以填充半导体封装件510和半导体封装件520之间的间隙。
下一步，实施切割工艺以形成具有PoP结构的多个单独的半导体封装件500。图17示出了PoP封装件500，其包括接合至底部封装件510的顶部封装件520。顶部封装件520可以是存储器件并且包括多个存储管芯(例如279)，底部封装件510可以是逻辑器件并且包括SoIC 150(见图11)。
图18示出了根据实施例的半导体封装件510A的截面图。半导体封装件510A类似于图17中的半导体封装件510，但是具有不同的SoIC 150A(见虚线矩形)。SoIC 150A类似于图11中的SoIC 150，但是具有使用例如熔融接合工艺以背对面接合配置附接至顶部管芯50的第三管芯21。如图18所示，SoIC 150A进一步包括位于第三管芯21和顶部管芯50之间的再分布结构158、位于再分布结构158上和第三管芯21周围的介电材料159和导电柱132。导电柱132延伸穿过介电层133/159并且穿过再分布结构158，并且将底部管芯100电连接至再分布结构148。可以分别使用与再分布结构148和介电材料133相同或类似的形成方法来形成再分布结构158和介电材料159，因此不再重复细节。
在一些实施例中，在例如使用镶嵌或双镶嵌工艺形成介电材料159和介电材料133之后，在单个工艺步骤中形成导电柱132。在图18的实例中，底部管芯100通过导电柱131和再分布结构158与顶部管芯50连通；并且底部管芯50通过导电柱132和再分布结构148与管芯21连通。
图19A和图19B示出了根据实施例的半导体结构510B的截面图。半导体封装件510B类似于图17中的半导体封装件510，但是具有不同的SoIC150B(见虚线矩形)。图19A是沿着图19B中的截面A-A的半导体结构510B的截面图。
SoIC 150B与图11的SoIC 150类似，但有一个以上的顶部管芯50附接至底部管芯100。图19A示出了作为非限制性实例的附接至底部管芯100的四个顶部管芯50。可以将多于或少于四个的顶部管芯50附接至底部管芯100，这些和其它变型完全旨在包括在本发明的范围内。图19A和图19B进一步示出了在顶部管芯50周围和顶部管芯50之间形成的导电柱131。
图20A和图20B示出了根据实施例的半导体结构510C的截面图。半导体封装件510C类似于图19A和图19B中的半导体结构510B，但是具有不同的SoIC 150C(见虚线矩形)。图20A是沿着图20B中的截面B-B的半导体结构510C的截面图。
SoIC 150C与图19A和图19B的SoIC 150B类似，但没有在顶部管芯50之间设置导电柱131。换句话说，在图20A和图20B的实施例中，导电柱131仅设置在顶部管芯50周围。
图21至图27示出了根据实施例的在制造的各个阶段的集成芯片上系统(SoIC)150D的截面图。具体地，图21至图27示出了形成SoIC的方法，其中，在相同的工艺步骤中形成管芯连接件55和导电柱131。
参考图21，形成具有器件区域40、第一钝化层(未示出)和导电焊盘(例如铝焊盘，未示出)的衬底51(例如，顶部晶圆)。衬底51包括多个顶部管芯50。注意，在该工艺阶段，没有形成第二钝化层52和管芯连接件55(见图1)。通过导电焊盘实施电路探测工艺，以识别衬底51中的已知良好管芯。为了简单起见，在随后的附图中可以不示出器件区域40。
下一步，在图22中，使用诸如DAF的粘合剂层56将衬底51的正面附接至载体57。下一步，在图23中，对衬底51的背面实施减薄工艺以将衬底51的厚度减小至例如在约1μm和约100μm之间，诸如约40μm。作为实例，可以使用研磨工艺和/或CMP工艺来实施减薄工艺。
在减薄工艺之后，在衬底51的背面上形成可选的氮化物层59，诸如氮化硅层。如上所述，氮化物层59可用于在随后的熔融接合工艺中在顶部管芯50和底部管芯100之间形成更牢固的接合。在一些实施例中，省略氮化物层59。
下一步，将衬底51附接至由框架63支撑的切割带61上。剥离载体57，并且实施清洁工艺(例如，DAF清洁工艺)以去除粘合剂层56的残留物。然后切割衬底51以形成多个顶部管芯50。
下一步，在图25中，顶部管芯50的背面(例如，已知良好顶部管芯50)通过熔融接合工艺以背对面接合配置接合至底部晶圆100’的正面。在一些实施例中，将顶部管芯50接合至底部晶圆100’的最顶部介电层的不具有接合焊盘107的区域。
在一些实施例中，在例如图4至图7所示的工艺之后，在将顶部管芯50接合至底部晶圆100’之前，使用一次性探测焊盘来测试底部晶圆100’。测试之后的底部晶圆100’的结构可以与图7、图8或图9所示的那些相同或类似。
下一步，在图26中，在顶部管芯50上形成导电柱55，并且在接合焊盘107上形成导电柱131。导电柱55电连接至顶部管芯50的导电焊盘并且用作管芯连接件。在一些实施例中，使用与以上针对图10中的导电柱131所描述的方法类似的方法，在相同的工艺步骤中形成导电柱131和导电柱55，因此不再描述细节。
下一步，在图27中，介电材料133形成在底部晶圆100’上方和顶部管芯50周围以及导电柱131/55周围，该介电材料133可以是诸如聚酰亚胺、低温聚酰亚胺、PBO等的聚合物。可以实施诸如CMP的平坦化工艺以平坦化介电材料133。下一步，实施切割工艺以分割底部晶圆100’并且形成多个SoIC 150D，其中每个SoIC 150D均包括接合至底部晶圆100的顶部管芯50。如图27所示，介电材料133与底部管芯100横向共末端。
图28至图33示出了根据实施例的处于制造的各个阶段的集成芯片上系统(SoIC)150E的截面图。特别地，图28至图33示出了用于形成SoIC的方法，其中使用粘合剂膜54将顶部管芯50接合至底部管芯100。
参考图28，形成具有器件区域40、第一钝化层(未示出)、导电焊盘(例如铝焊盘，未示出)和管芯连接件55的衬底51(例如，顶部晶圆)。衬底51包括多个管芯(例如，顶部管芯50)。通过管芯连接件55实施电路探测工艺，以识别衬底51中的已知良好管芯。在电路探测工艺之后，第二钝化层52形成在衬底51上方。为了简单起见，在随后的附图中可以不示出器件区域40。
下一步，在图29中，使用粘合剂层56将载体57附接至第二钝化层，并且从衬底51的背面实施减薄工艺以将衬底51的厚度减小至在约1μm和约100μm之间，诸如约40μm。
下一步，在图30中，将衬底51附接至切割带61，并且实施切割工艺以将衬底51分离并且形成多个顶部管芯50。
下一步，在图31中，按照例如图4至图7中所示的工艺，使用一次性探测焊盘来测试底部晶圆100’。测试之后的底部晶圆100’的结构可以与图7、图8或图9所示的那些相同或类似。下一步，使用与图10中上述相同或类似的工艺，在底部晶圆100’的接合焊盘107上形成导电柱131。
下一步，在图32中，使用诸如DAF的粘合剂膜54将在图30中形成的顶部管芯50(例如，已知良好顶部管芯50)附接至底部晶圆100’的正面。在一些实施例中，将顶部管芯50附接至底部晶圆100’的最顶部介电层的不具有接合焊盘107的区域。
下一步，在图33中，可以在底部晶圆100’上形成介电材料133，该介电材料133可以是聚酰亚胺、低温聚酰亚胺、模制材料等。介电材料围绕顶部管芯50和导电柱131。在形成介电材料133之后，实施切割工艺以将底部晶圆100’分离并且形成多个SoIC 150E。
图34至图36、图37A、图37B和图38至图42示出了根据实施例的处于制造的各个阶段的半导体结构220(见图41和图42)的截面图。半导体结构220具有衬底上晶圆上芯片(CoWoS)结构，其包括附接至衬底201上的晶圆上芯片(CoW)结构190(见图40)，其细节在下文中描述。
参考图34，使用熔融接合工艺以背对面接合配置将多个顶部管芯50接合至底部晶圆100’。上面已经讨论了熔融接合工艺和背对面接合配置，因此可能不再重复细节。可以按照与图1至图3所示相同或类似的工艺来形成顶部管芯50。底部晶圆100’可以与图10的底部晶圆100’相同或类似。在一些实施例中，在将顶部管芯50接合至底部晶圆100’之前，按照与图4至图7所示相同或类似的工艺，使用一次性探测焊盘来测试底部晶圆100’。
在一些实施例中，在将顶部管芯50接合至底部晶圆100’之后，在顶部管芯50周围的底部晶圆100’上形成介电材料134。在所示的实施例中，介电材料134是氧化物，诸如氧化硅，并且通过诸如PCV、CVD等的合适的形成方法形成。使用氧化物作为介电材料134允许随后形成具有精细间距(例如，在约5μm和约30μm之间的间距)的导电柱131(下文中讨论)。尽管氧化物用作介电材料134的实例，但是介电材料134可以由其它合适的材料形成，诸如聚合物或模制材料。在其中聚合物或模制材料用作介电材料134的实施例中，随后形成的导电柱131之间的间距可以更大，诸如在约50μm和约100μm之间。
下一步，使用例如光刻和蚀刻技术(例如，干蚀刻)在介电材料134中形成开口。开口延伸穿过介电材料134，并且暴露出下面的接合焊盘107。下一步，在开口中形成诸如铜的导电材料以填充开口，从而形成导电柱131(也可以称为通孔)。作为实例，导电材料可以通过镀工艺(例如，电镀或化学镀)形成，但是也可以使用其它合适的方法。
在形成导电柱131之后，可以实施诸如CMP的平坦化工艺以实现介电材料134的水平上表面。在平坦化工艺之后，导电柱131的上表面和顶部管芯50的管芯连接件55的上表面在介电材料134的上表面处暴露。在一些实施例中，在平坦化工艺之后，顶部管芯50和/或导电柱131的H4的高度在约10μm和约100μm之间，诸如约30μm。导电柱131的宽度可以在约10μm和约50μm之间，诸如约30μm，并且相邻的导电柱之间的间距可以在约20μm和约100μm之间，诸如约70μm。
下一步，如图35所示，再分布结构148形成在介电材料134上方，并且电连接至导电柱131和顶部管芯50。再分布结构148包括多个介电层145和形成在介电层145中的导电部件(例如，导线147和通孔149)。诸如微凸块的外部连接件144形成在再分布结构148上方，并且电连接至再分布结构148的导电部件。图35中的再分布结构148的形成可以与图15中的再分布结构148的形成相同或类似，因此这里不再重复细节。下一步，实施切割工艺以将底部晶圆100’分离并且形成多个SoIC 150F。图35示出了在切割工艺之后形成的SoIC 150F。在图35的实例中，再分布结构148和介电材料134与底部管芯100横向共末端。
在一些实施例中，用于形成图35的再分布结构148的介电层145的材料被调整以适应关于再分布结构148的线间距(例如，相邻导线之间的间距)的不同的设计目标。例如，为了实现0.8μm或更小的线间距，可以使用氧化物(例如，氧化硅、未掺杂的硅酸盐玻璃(USG)等)来形成介电层145。为了实现10μm以上的线间隔，可以使用聚合物(例如，聚酰亚胺、LPTI等)来形成介电层145。
在一些实施例中，当使用氧化物来形成介电层145时，可以使用类似于镶嵌工艺的工艺步骤来形成导电部件(例如，线)并且实现0.8μm或更小的细线间隔。例如，在通过例如CVD形成氧化物之后，在氧化物上方形成图案化的光刻胶(例如，具有高分辨率的高质量光刻胶)。下一步，使用图案化的光刻胶作为蚀刻掩模来实施干蚀刻工艺，以在氧化物中形成开口。下一步，去除图案化的光刻胶(例如，通过灰化或剥离)，并且在氧化物的开口中形成阻挡层/晶种层。下一步，实施诸如电化学镀的镀工艺以用导电材料(例如，铜)填充开口，并且然后实施CMP以去除开口外部的导电材料部分。因此，开口中的导电材料的剩余部分形成导电部件。
在一些实施例中，当使用聚合物形成介电层145时，由于聚合物(例如，与氧化物相比更柔软)的物理性质，可以按照上面参考图15讨论的相同或类似的工艺步骤来形成再分布结构148的导电部件(例如，线、通孔)。形成在聚合物层上方的光刻胶也可能具有较低的质量和较低的分辨率。因此，当将聚合物用作再分布结构148的介电层145时，线间距较大(例如，10μm或更大)。
下一步，在图36中，通过将SoIC 150F的外部连接件144(见图35)接合至中介层170的上表面的外部连接件174(例如，微凸块，见图37A)，将多个SoIC 150F附接至中介层170。在SoIC 150F附接至中介层170之后，可在SoIC 150F和中介层170之间形成底部填充材料169。
图37A更详细地示出了图36中的中介层170的截面图。图37B是中介层170的部分的放大图。参考图37A，中介层170包括衬底171、衬底171中的衬底通孔(TSV)172、再分布结构173和外部连接件174。
参考图37B，衬底171可以是例如掺杂或未掺杂的硅衬底，或者绝缘体上硅(SOI)衬底的有源层。然而，衬底171可以可选地是玻璃衬底、陶瓷衬底、聚合物衬底或可以提供合适的保护和/或互连功能的任何其它衬底。这些和任何其它合适的材料可以可可选地用于衬底171。
在一些实施例中，衬底171可以包括电子组件，诸如电阻器、电容器、信号分布电路、这些的组合等。这些电子组件可以是有源的、无源的或它们的组合。在其它实施例中，衬底171中没有有源和无源电子组件。所有这些组合完全旨在包括在实施例的范围内。
可以通过在衬底171中形成开口并且用一种或多种导电材料填充开口来形成TSV172。在所示的实施例中，开口延伸至衬底171中而不延伸穿过衬底171。用于TSV 172的开口可以内衬有衬垫172L，并且填充有导电材料175。在实施例中，衬垫172L是通过诸如化学汽相沉积、氧化、物理汽相沉积、原子层沉积等的工艺形成的诸如氮化硅、氧化硅、介电聚合物、它们的组合等的介电材料。
在一些实施例中，导电材料175可以包括铜，但是可以可选地使用诸如铝、钨、合金、掺杂的多晶硅、它们的组合等的其它合适的材料。可以通过沉积晶种层，然后将铜电镀至晶种层上，填充和过填充用于TSV 172的开口来形成导电材料175。下一步可以实施诸如CMP的平坦化工艺以去除设置在用于TSV 172的开口外部的导电材料175的过量部分。
在示出的实施例中，在平坦化工艺之后，沿衬底171的上表面残留的衬垫172L的厚度在约0.7μm和约0.8μm之间，诸如0.75μm，并且沿开口的侧壁的衬垫172L具有例如约1μm的较大的厚度。如图37B所示，在最初形成之后，TSV 172不延伸穿过衬底171。在实施例中，TSV172的宽度在约5μm和约20μm之间，并且TSV 172的高度H5在约50μm和约150μm之间。
下一步，在衬底171上方形成电连接至TSV 172的再分布结构173。可以使用与图15中的再分布结构148相同或类似的方法来形成再分布结构173，因此可以不重复细节。在图37B的实例中，再分布结构173包括介电层176/177/178以及导电部件，诸如导线179L和通孔179V。在实施例中，介电层176由氮化硅(例如，SiN)形成，介电层177由碳化硅(例如，SiC)形成，并且介电层178由USG形成。
下一步，在再分布结构173上方形成介电层181(例如，氧化物层)，并且在介电层181中形成电连接至再分布结构173的导电部件的通孔188。下一步，在介电层181上方形成电连接至通孔188的导电焊盘189(例如，铝焊盘)。第一钝化层183(例如，氧化物层)形成在介电层181上方并且覆盖导电焊盘189的外围部分。在第一钝化层183上方形成第二钝化层185(例如，SiN层)。形成可包括导电凸块174A(例如微凸块，铜柱)和焊料盖174B的外部连接件174，外部连接件174延伸穿过第二钝化层185并且电连接至相应的导电焊盘189。凸块下金属(UBM)结构182可以形成在外部连接件174和导电焊盘189之间。
下一步，参考图38，在中介层170上方和SoIC 150F周围形成模制材料191。可以实施诸如CMP的平坦化工艺以去除沉积的模制材料191的过量部分。平坦化工艺还可以暴露SoIC 150F的背面。模制材料191物理接触再分布结构148(见图35)的侧壁、介电材料134(见图35)的侧壁以及SoIC 150F的底部管芯100的侧壁。
下一步，在图39中，将载体193附接至模制材料191，并且实施减薄工艺，例如，通过背面研磨，以减小衬底171的厚度。在背面减薄工艺之后，TSV 172在衬底171的表面171B处暴露。下一步，在TSV 172的暴露的端面上形成诸如C4凸块的导电凸块195。
下一步，在图40中，将图39中的半导体结构附接至由框架194支撑的带192，并且实施切割工艺以分割中介层170并且形成多个晶圆上芯片(CoW)结构190，其中每个CoW结构190均包括接合至中介层的一个或多个SoIC 150F。
下一步，在图41中，例如，通过将CoW结构190的导电凸块195接合至衬底201的上表面上的导电焊盘203，将图40的CoW结构190接合至衬底201，从而形成衬底上晶圆上芯片(CoWoS)结构220。底部填充材料204可以形成在CoW结构190和衬底201之间的间隙中。
在一些实施例中，衬底201是多层电路板(例如，印刷电路板(PCB))。在一些实施例中，衬底201包括双马来酰亚胺三嗪(BT)树脂、FR-4(由玻璃纤维布和阻燃的环氧树脂粘合剂组成的复合材料)、陶瓷、玻璃、塑料、带、膜或其它支撑材料。衬底201可以包括在衬底201中/上形成的导电部件(例如，导线和通孔)。如图41所示，衬底201具有形成在衬底201的上表面和下表面上的导电焊盘203，这些导电焊盘203电连接至衬底201的导电部件。
下一步，在图42中，使用例如粘合剂将盖211附接至衬底201的上表面。盖211可包括环绕CoWoS结构220的侧壁部分211S和位于CoWoS结构220上方的顶部211T。盖211可以由具有良好导热性的材料(例如，金属)形成，并且可以用作散热器件。盖211还提供对CoWoS结构220的保护。图42进一步示出了位于盖211的顶部211T和CoW结构190之间的热界面材料(TIM)213。TIM 213可以包括作为基底材料的聚合物、树脂或环氧树脂，以及用于提高其导热性的填料。填料可以包括介电填料，诸如氧化铝、氧化镁、氮化铝、氮化硼和金刚石粉末。填充物也可以是金属填充物，诸如银、铜、铝等。
图43至图46、图47A、图47B、图48、图49和图50A至图50C示出了集成芯片上系统(SoIC)的各个实施例的截面图。图43至图46、图47A、图47B、图48、图49和图50A至图50C中所示的SoIC可用于形成各个半导体结构，诸如CoWoS结构220和半导体封装件510。
图43示出了SoIC 150G的截面图，SoIC 150G包括在管芯301的正面处具有互连结构310管芯301，以及其背面附接至互连结构310的管芯302。例如，可以使用熔融接合工艺通过在管芯302的材料(例如，硅)和互连结构310的最顶部介电层的材料(例如，氧化物)之间形成硅与氧化物键来接合管芯302。互连结构310可以与图7、图8或图9所示的互连结构105相同或类似，并且包括形成在多个介电层311中的诸如导线315、通孔313和接合焊盘317的导电部件。
SoIC 150G进一步包括位于管芯302周围的介电层321，以及嵌入在介电层321中的导电柱323。介电层321可以由诸如氧化物(例如，氧化硅)、诸如聚酰亚胺或LTPI的聚合物、模制材料等的合适的材料形成。导电柱323延伸穿过介电层321，并且可以具有例如在约10μm和约200μm之间的高度。
图43进一步示出了与图15所示的再分布结构148相同或类似的再分布结构331。诸如微凸块、C4凸块、BGA等的导电凸块335形成在再分布结构331上方并且电连接至该再分布结构331。在图43的实例中，管芯301和管芯302通过再分布结构331和导电柱323通信。
图44所示了SoIC 150H的截面图，SoIC 150H与图43中的SoIC 150G类似。然而，图44中的管芯302通过诸如DAF的粘合剂膜318接合至管芯301。
图45所示了SoIC 150I的截面图，SoIC 150I与图43中的SoIC 150G类似，但具有额外层级的垂直堆叠件。特别地，在介电层321上方形成再分布结构331之后，使用背对面接合配置将管芯303接合(例如，使用融合接合工艺)至再分布结构331，并且在再分布结构331上形成可以与介电层321相同或类似的介电层321A。在形成介电层321A之后，在实施例中，在使用例如双镶嵌工艺或镶嵌工艺的单个工艺步骤中，形成延伸穿过介电层321/321A的可包括上部324U和下部324L的导电柱324。注意，在图45的实例中，在形成介电层321之后并且在形成再分布结构331之前形成导电柱323。在形成导电柱324之后，形成再分布结构341，随后，在再分布结构341上方形成电连接至再分布结构341的导电凸块335。
图46示出了SoIC 150J的截面图，SoIC 150J与图45中的SoIC 150I类似，但具有额外层级的垂直堆叠件。例如，与图45所示的SoIC 150I相比，形成了其它管芯(例如304和305)和其它再分布结构(例如351和361)。注意，在图46中，每个导电柱324延伸穿过两个相邻的介电层，并且可以在单个工艺步骤(例如，双镶嵌工艺)中形成。
图47A和图47B示出了SoIC 150K的截面图，SoIC 150K类似于图43中的SoIC 150G，但是具有多个管芯(见图47A中的302、303、304和305)在相同的垂直层级处彼此横向相邻设置。图47A示出了沿着图47B中的截面C-C的SoIC 150K的截面图。在图47A和图47B的实例中，四个管芯302-305接合至管芯301的正面(例如，使用熔融接合工艺)，其中，在管芯302-305周围形成有导电柱323。尽管在图47A中未在管芯302-305之间示出导电柱323，但是在其它实施例中，可在管芯302-305之间形成导电柱323。
图48示出了SoIC 150L的截面图，SoIC 150L类似于图47A和图47B中的SoIC 150K，但是具有额外层级的垂直堆叠件。特别地，四个额外的管芯306、307、308和309接合(例如，使用熔融接合工艺)至再分布结构331。注意，管芯308和309不在图48的截面中，因此未在图48中示出。另外，介电层321A、再分布结构341和导电柱323形成在再分布结构331上方。
图49示出了SoIC 150M的截面图，SoIC 150M与图48中的SoIC 150L类似，但是一个管芯306(而不是四个管芯306-309)接合至再分布结构331上。
图50A和图50B示出了SoIC 150N的截面图，SoIC 150N与图46中的SoIC 150J类似，但是预形成的连接件芯片325代替了图46中的导电柱323和324。图50A是沿着图50B的D-D线的SoIC 150N的截面图。
如图50A和图50B所示，预形成的连接件芯片325代替介电层321和321A-321C中的导电柱。例如，在使用例如熔融接合工艺将管芯302接合至管芯301的互连结构310之后，将预形成的连接件芯片325附接至邻近管芯302的互连结构310。连接件芯片325附接在预定位置，从而使得连接件芯片325的通孔329(也可以称为导电柱)与互连结构310的相应的接合焊盘317对准并且接触(例如，物理接触)。
参考图50C，其示出了连接件芯片325的截面图。预形成的连接件芯片325具有衬底327，衬底327具有延伸穿过衬底327的通孔329。衬底327可以是诸如块状硅的块状材料，但是也可以使用诸如玻璃、陶瓷、聚合物等的其它块状材料。通孔329由诸如铜、钨、铝等的导电材料形成。在一些实施例中，衬底327没有任何其它有源或无源电子组件，诸如晶体管、电容器等。图50A示出了连接件芯片325的俯视图。图50A和图50B所示的每个连接件芯片325中的通孔329的数量和通孔329的位置是非限制性实例。其它数量和其它位置也是可能的，并且完全旨在包括在本发明的范围内。
再次参考图50A和图50B，在附接预形成的连接件芯片325之后，在管芯301上并且在管芯302周围以及在连接件芯片325周围形成介电层321。可以实施CMP工艺以平坦化介电层321，并且然后在介电层321上方形成再分布结构331。可以重复类似的工艺以在再分布结构331上方形成额外层，以完成SoIC 150N的制造。
图51示出了在一些实施例中的用于形成半导体结构的方法的流程图。应该理解，图51所示的实施例方法仅仅是许多可能的实施例方法的实例。本领域普通技术人员将认识到许多变化、替换和修改。例如，可以添加、移除、替换、重新布置和重复如图51所示的各个步骤。
参考图51，如步骤1010，将顶部管芯的背面附接至底部晶圆的正面，底部晶圆包括多个底部管芯。在步骤1020中，在底部晶圆的与顶部管芯相邻的正面上形成第一导电柱。在步骤1030中，在顶部管芯周围和第一导电柱周围的底部晶圆的正面上形成第一介电材料。在步骤1040中，切割底部晶圆以形成多个结构，该多个结构中的每一个均包括至少一个顶部管芯和至少一个底部管芯。
实施例可以实现许多优势。例如，SoIC中的管芯通过SoIC中的导电柱和再分布结构相互通信，并且因此不需要延伸穿过管芯的衬底通孔(TSV)即可形成SoIC，这简化了管芯的制造，降低了管芯的生产成本，并且允许将多种类型的管芯(例如，逻辑管芯、存储器管芯)集成在一起以形成SoIC。如各个实施例所示，用于SoIC的柔性结构允许用于SoIC的柔性尺寸和柔性功能集成以实现高集成密度。形成的SoIC可以集成至不同的封装件类型中，诸如具有CoWoS结构的封装件、倒装芯片封装件或集成扇出(InFO)封装件。通过在再分布结构中使用氧化物，对于再分布结构实现了导线之间的精细间距(例如，≤0.8μm的线间距)，这在以前是无法实现的。通过在顶部管芯的背面上形成氮化物层，对于熔融接合工艺，可以实现更高的熔融接合强度。
根据实施例，形成半导体结构的方法包括将顶部管芯的背面附接至底部晶圆的正面，底部晶圆包括多个底部管芯；在底部晶圆的与顶部管芯相邻的正面上形成第一导电柱；在顶部管芯周围和第一导电柱周围的底部晶圆的正面上形成第一介电材料；并且切割底部晶圆以形成多个结构，所述多个结构中的每一个均包括至少一个顶部管芯和至少一个底部管芯。在实施例中，该方法还包括在附接之前，通过设置在底部晶圆的正面处的一次性探测焊盘来测试底部晶圆。在实施例中，该方法还包括在测试之后和附接之前：从底部晶圆上去除一次性探测焊盘；在去除一次性探测焊盘之后，在底部晶圆的正面上形成介电层；并且形成延伸穿过介电层并且电连接至底部管芯的接合焊盘，其中第一导电柱形成在相应的接合焊盘上方。在实施例中，顶部管芯的背面通过熔融接合工艺附接至底部晶圆的正面。在实施例中，顶部管芯的背面物理接触底部晶圆。在实施例中，该方法还包括在将顶部管芯的背面附接至底部晶圆的正面之前，在顶部管芯的背面上形成氮化物层。在实施例中，将顶部管芯的背面附接至底部晶圆的正面包括使用粘合剂膜将顶部管芯的背面附接至底部晶圆的正面。在实施例中，第一介电材料是氧化物并且在形成第一导电柱之前形成在底部晶圆的正面上。在实施例中，形成第一导电柱包括：在第一介电材料中形成开口，所述开口在底部晶圆的正面处暴露导电部件；并且用导电材料填充开口。在实施例中，该方法还包括在切割底部晶圆之前，在第一介电材料上形成再分布结构。在实施例中，该方法还包括在切割底部晶圆之后：将多个结构中的一个或多个接合至中介层的第一侧；在中介层的第二相对侧上形成外部连接件；并且将所述中介层的外部连接件接合至衬底。在实施例中，该方法进一步包括将盖附接至中介层周围和上方的衬底。在实施例中，该方法还包括在切割底部晶圆之后：将多个结构附接至载体；在载体上形成与多个结构相邻的第二导电柱；在多个结构周围和第二导电柱周围的载体上形成模制材料；并且在所述模制材料上方形成再分布结构。
根据实施例，形成半导体结构的方法包括形成集成电路器件，其中，形成集成电路器件包括：将第二管芯的背面附接至第一管芯的正面，其中，第一管芯在第一管芯的正面处具有第一导电焊盘，第一导电焊盘设置在第二管芯的边界外部；在第一管芯的正面和第二管芯周围形成介电材料；在介电材料中形成第一导电柱并且电连接至第一管芯的第一导电焊盘；在介电材料上形成电连接至第二管芯和第一导电柱的再分布结构；并且在再分布结构上方形成连接件；将集成电路器件的连接件附接至中介层的第一侧；并且在集成电路器件周围的中介层的第一侧上形成模制材料；并且在中介层的第二侧上形成导电凸块。在实施例中，该方法还包括：将中介层的第二侧上的导电凸块接合至衬底；以及将盖附接至衬底，其中，将集成电路器件和中介层设置在盖和衬底之间的封闭空间中。在实施例中，该方法还包括：在形成模制材料之后并且在形成导电凸块之前，将模制材料的第一侧在中介层的远侧附接至载体；并且研磨中介层的第二侧以减小中介层的厚度，其中，在研磨之后，暴露嵌入在中介层中的通孔的第一端面，其中，导电凸块形成在通孔的第一端面上。在实施例中，将第二管芯的背面附接至第一管芯的正面包括：在第二管芯的背面上形成氮化物层；并且在形成氮化物层之后，进行熔融接合工艺以将第二管芯的背面上的氮化物层接合至第一管芯的正面。
根据实施例，半导体结构包括：第一管芯，在第一管芯的第一侧处具有第一导电焊盘；第二管芯，具有远离第一管芯的第一侧并且具有附接至第一管芯的第一侧的第二侧，第二管芯在第二管芯的第一侧处具有第二导电焊盘；第一导电柱，附接至第一管芯的第一导电焊盘并且与第二管芯相邻；第一介电材料位于第一管芯的第一侧上和第二管芯周围以及第一导电柱周围，其中，第一介电材料与第一管芯共末端；位于第一介电材料上并且电连接至第二管芯的第一导电柱和第二导电焊盘的再分布结构；以及外部连接件，位于再分布结构的远离第二管芯的第一侧上。在实施例中，半导体结构还包括：位于第一管芯、第二管芯和第一介电材料周围的模制材料；以及第二导电柱，位于模制材料中并且电连接至再分布结构。在实施例中，第二管芯的第二侧接触第一管芯的第一侧。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (17)

1.一种形成半导体结构的方法，所述方法包括：
将顶部管芯的背面附接至底部晶圆的正面，所述底部晶圆包括多个底部管芯，其中，在所述附接之前，通过设置在所述底部晶圆的正面处的一次性探测焊盘测试所述底部晶圆；
在所述底部晶圆的与所述顶部管芯相邻的正面上形成第一导电柱；
在所述顶部管芯周围和所述第一导电柱周围的所述底部晶圆的正面上形成第一介电材料；以及
在测试所述底部晶圆之后，切割所述底部晶圆以形成多个结构，所述多个结构中的每一个均包括至少一个顶部管芯和至少一个底部管芯，
其中，所述一次性探测焊盘位于所述底部晶圆的相应的导电焊盘上，并且其中，所述方法还包括：在所述测试之后并且在所述附接之前：
从所述底部晶圆去除所述一次性探测焊盘；
在去除所述一次性探测焊盘之后，在所述底部晶圆的正面上方形成介电层；以及
形成延伸穿过所述介电层并且电连接至所述底部管芯的接合焊盘，
其中，所述接合焊盘越过所述导电焊盘并且从所述导电焊盘的一侧直接连接至所述导电焊盘下方的金属化层中的顶部金属层，
其中，将所述顶部管芯的背面附接至所述底部晶圆的正面包括将所述顶部管芯接合至所述底部晶圆的所述介电层的不具有接合焊盘的区域，并且其中，所述顶部管芯和所述底部晶圆之间的通信通过形成在相应的所述接合焊盘上方的所述第一导电柱以及形成在所述第一导电柱和所述顶部管芯上方的再分布结构进行。
2.根据权利要求1所述的方法，其中，所述一次性探测焊盘与所述相应的导电焊盘接触。
3.根据权利要求1所述的方法，其中，所述金属化层的上部金属化层中的导电部件的尺寸大于所述上部金属化层下方的下部金属化层中的导电部件的尺寸。
4.根据权利要求1所述的方法，其中，所述顶部管芯的背面通过熔融接合工艺附接至所述底部晶圆的正面。
5.根据权利要求4所述的方法，其中，所述顶部管芯的背面物理接触所述底部晶圆。
6.根据权利要求4所述的方法，还包括：在将所述顶部管芯的背面附接至所述底部晶圆的所述正面之前，在所述顶部管芯的背面上形成氮化物层。
7.根据权利要求1所述的方法，其中，将所述顶部管芯的背面附接至所述底部晶圆的正面包括使用粘合剂膜将所述顶部管芯的背面附接至所述底部晶圆的正面。
8.根据权利要求1所述的方法，其中，所述第一介电材料是氧化物，并且在形成所述第一导电柱之前形成在所述底部晶圆的正面上。
9.根据权利要求8所述的方法，其中，形成所述第一导电柱包括：
在所述第一介电材料中形成开口，所述开口在所述底部晶圆的正面处暴露导电部件；以及
用导电材料填充所述开口。
10.根据权利要求1所述的方法，还包括：在切割所述底部晶圆之前，在所述第一介电材料上形成再分布结构。
11.根据权利要求10所述的方法，还包括：在切割所述底部晶圆之后：
将所述多个结构中的一个或多个接合至中介层的第一侧；
在所述中介层的第二相对侧上形成外部连接件；以及
将所述中介层的所述外部连接件接合至衬底。
12.根据权利要求11所述的方法，还包括：将盖附接至所述中介层周围和所述衬底的上方。
13.根据权利要求1所述的方法，还包括：在切割所述底部晶圆之后：
将所述多个结构附接至载体；
在所述载体上形成与所述多个结构相邻的第二导电柱；
在所述多个结构周围和所述第二导电柱周围的所述载体上形成模制材料；以及
在所述模制材料上方形成所述再分布结构。
14.一种形成半导体结构的方法，所述方法包括：
形成集成电路器件，其中，形成所述集成电路器件包括：
将第二管芯的背面附接至第一管芯的正面，其中，所述第一管芯在所述第一管芯的正面处具有第一导电焊盘，所述第一导电焊盘设置在所述第二管芯的边界外部；
在所述第一管芯的正面和所述第二管芯周围形成介电材料；
在所述介电材料中形成电连接至所述第一管芯的第一导电焊盘的第一导电柱；
在所述介电材料上形成电连接至所述第二管芯和所述第一导电柱的再分布结构；以及
在所述再分布结构上方形成连接件；
将所述集成电路器件的连接件附接至中介层的第一侧；
在所述集成电路器件周围的所述中介层的第一侧上形成模制材料；以及
在所述中介层的第二侧上形成导电凸块；以及
将所述中介层的所述第二侧上的所述导电凸块接合至衬底；以及
将盖附接至所述衬底，其中，所述集成电路器件和所述中介层设置在所述盖和所述衬底之间的封闭空间中，
其中，热界面材料位于所述盖的顶部和所述集成电路器件之间，
其中，将所述第二管芯的背面附接至所述第一管芯的正面包括将所述第二管芯接合至所述第一管芯的不具有所述第一导电焊盘的区域，并且其中，所述第二管芯和所述第一管芯之间的通信通过形成在相应的所述第一导电焊盘上方的所述第一导电柱以及所述再分布结构进行。
15.根据权利要求14所述的方法，其中，所述热界面材料包括填料。
16.根据权利要求14所述的方法，还包括：
在形成所述模制材料之后并且在形成所述导电凸块之前，将所述模制材料的第一侧在所述中介层的远侧附接至载体；以及
研磨所述中介层的第二侧以减小所述中介层的厚度，其中，在所述研磨之后，暴露嵌入在所述中介层中的通孔的第一端面，其中，所述导电凸块形成在所述通孔的第一端面上。
17.根据权利要求14所述的方法，其中，将所述第二管芯的背面附接至所述第一管芯的正面包括：
在所述第二管芯的背面上形成氮化物层；以及
在形成所述氮化物层之后，实施熔融接合工艺以将所述第二管芯的背面上的所述氮化物层接合至所述第一管芯的正面。
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Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3449502B1 (en) 2016-04-26 2021-06-30 Linear Technology LLC Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
KR102574409B1 (ko) * 2019-07-01 2023-09-04 삼성전기주식회사 반도체 패키지
US11205630B2 (en) * 2019-09-27 2021-12-21 Intel Corporation Vias in composite IC chip structures
US11094672B2 (en) 2019-09-27 2021-08-17 Intel Corporation Composite IC chips including a chiplet embedded within metallization layers of a host IC chip
US12094800B2 (en) * 2019-12-19 2024-09-17 Intel Corporation Thermally conductive slugs/active dies to improve cooling of stacked bottom dies
US11227814B2 (en) * 2020-03-16 2022-01-18 Nanya Technology Corporation Three-dimensional semiconductor package with partially overlapping chips and manufacturing method thereof
DE102020128855A1 (de) * 2020-05-21 2021-11-25 Taiwan Semiconductor Manufacturing Co., Ltd. Chiplets-3d-soic-systemintegrations- und herstellungsverfahren
US11462495B2 (en) * 2020-05-21 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Chiplets 3D SoIC system integration and fabrication methods
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
KR20210152721A (ko) * 2020-06-09 2021-12-16 삼성전자주식회사 반도체 패키지
KR20210156446A (ko) * 2020-06-18 2021-12-27 삼성전자주식회사 반도체 패키지
CN111952201B (zh) * 2020-07-14 2022-02-18 珠海越亚半导体股份有限公司 一种嵌入式封装基板的制造方法
US11823989B2 (en) * 2020-07-17 2023-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-liner TSV structure and method forming same
US20220319954A1 (en) * 2021-03-31 2022-10-06 Texas Instruments Incorporated Package heat dissipation
US20230065941A1 (en) * 2021-08-29 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same
US11688708B2 (en) * 2021-08-30 2023-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Chip structure and method for forming the same
US12015002B2 (en) 2021-08-30 2024-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Chip structure and method for forming the same
TWI806263B (zh) * 2021-11-30 2023-06-21 矽品精密工業股份有限公司 電子封裝件及其製法
EP4432344A1 (de) * 2023-03-15 2024-09-18 Siemens Aktiengesellschaft Halbleiteranordnung mit einem halbleiterelement und einem substrat

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4822880B2 (ja) 2006-03-02 2011-11-24 株式会社リコー 半導体ウエハ、半導体装置及び半導体装置の製造方法
JP5358077B2 (ja) 2007-09-28 2013-12-04 スパンション エルエルシー 半導体装置及びその製造方法
US8354297B2 (en) * 2010-09-03 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die
US9064879B2 (en) * 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US20130040423A1 (en) 2011-08-10 2013-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Multi-Chip Wafer Level Packaging
US8557684B2 (en) * 2011-08-23 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit (3DIC) formation process
US8531032B2 (en) * 2011-09-02 2013-09-10 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally enhanced structure for multi-chip device
US9679863B2 (en) * 2011-09-23 2017-06-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interconnect substrate for FO-WLCSP
US9842798B2 (en) * 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
US9385006B2 (en) * 2012-06-21 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SOP fan-out package
KR101419597B1 (ko) 2012-11-06 2014-07-14 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9252076B2 (en) * 2013-08-07 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
DE102014201805B4 (de) 2014-01-31 2024-05-08 Siemens Healthineers Ag Bildgebendes medizinisches Gerät
US9899248B2 (en) * 2014-12-03 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
US9627288B2 (en) * 2015-05-29 2017-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures and methods of forming the same
US9484227B1 (en) * 2015-06-22 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Dicing in wafer level package
US10049953B2 (en) 2015-09-21 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US9704825B2 (en) 2015-09-30 2017-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacture thereof
US9620482B1 (en) 2015-10-19 2017-04-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9735131B2 (en) * 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US9773757B2 (en) 2016-01-19 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
US9741690B1 (en) * 2016-09-09 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
US9859245B1 (en) * 2016-09-19 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with bump and method for forming the same
US9768133B1 (en) * 2016-09-22 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US10186462B2 (en) 2016-11-29 2019-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method

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