CN111211109B - 顶电极互连结构 - Google Patents
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- 239000000463 material Substances 0.000 claims abstract description 89
- 238000000034 method Methods 0.000 claims abstract description 67
- 238000001465 metallisation Methods 0.000 claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 claims description 22
- 239000004020 conductor Substances 0.000 claims description 10
- 239000003989 dielectric material Substances 0.000 claims description 10
- 230000000873 masking effect Effects 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 230000008569 process Effects 0.000 description 53
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 230000004888 barrier function Effects 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 11
- 238000000059 patterning Methods 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 239000012212 insulator Substances 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000009977 dual effect Effects 0.000 description 6
- 239000010408 film Substances 0.000 description 6
- -1 SiCN Chemical class 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 239000007772 electrode material Substances 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 230000015654 memory Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910020776 SixNy Inorganic materials 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910020781 SixOy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Abstract
本公开涉及半导体结构,更具体地,顶电极互连结构以及制造方法。该结构包括:下金属化特征;上金属化特征;与下金属化特征直接接触的底电极;位于底电极之上的一种或多种开关材料;位于一种或多种开关材料之上的顶电极;以及与顶电极和上金属化特征接触的自对准过孔互连。
Description
技术领域
本公开涉及半导体结构,更具体地,嵌入在集成电路(IC)的互连结构中的存储器,以及制造方法。
背景技术
在诸如RRAM(电阻式RAM)、PRAM(相变RAM)、MRAM(磁性RAM)、FRAM(铁电RAM)等的嵌入式存储器件中形成用于顶电极的互连的当前方法中存在许多挑战。这些存储器件包括底金属化和顶金属化,在这些金属层之间具有顶电极、开关材料和底电极。
例如,当在执行镶嵌线蚀刻以露出顶电极期间形成顶电极互连时,存在挑战。在该减法方法中,对于该蚀刻减法工艺,存在窄工艺窗口。如果蚀刻太浅,则连接会具有高电阻。如果蚀刻太深,则存在开关层短路的风险。为了解决这些问题,通常使顶电极更厚,如果顶电极材料太厚而不能光学透明,则反过来又需要额外的覆盖掩模。
如果使用过孔孔(via hole)图案化工艺(而不是线),则在顶电极互连制造工艺期间也遇到挑战。在这种类型的工艺中,在非存储器过孔(via)着陆在下面的金属层级上之前,过孔可以很好地着陆在顶电极上。在这种情况下,顶电极在蚀刻工艺期间存在高损耗。因此使用较厚的顶电极,这导致与上述相同的问题。这种类型的顶电极互连也受到按比例缩放的限制,因为存储位的高度必须远小于单个过孔高度。
发明内容
在本公开的一方面,一种结构包括:下金属化特征;上金属化特征;与所述下金属化特征直接接触的底电极;位于所述底电极之上的一种或多种开关材料;位于所述一种或多种开关材料之上的顶电极;以及与所述顶电极和所述上金属化特征接触的自对准过孔互连。
在本公开的一方面,一种结构包括:存储器件,其包括:第一金属化层;第二金属化层;以及将所述第一金属化层连接到所述第二金属化层的垂直柱,所述垂直柱包括与所述垂直柱的顶电极和所述第二金属化层接触的自对准过孔互连;以及外围器件或逻辑器件,所述外围器件或逻辑器件包括通过没有所述自对准过孔互连和所述垂直柱的互连结构连接在一起的所述下金属化特征和所述上金属化特征。
在本公开的一方面,一种方法包括:形成垂直柱,所述垂直柱包括底电极、一种或多种开关材料、顶电极和位于所述顶电极上的掩蔽材料;在所述垂直柱之上形成层级间(interlevel)介电材料;对所述层级间介电材料进行开口以暴露所述掩蔽材料;选择性地去除所述顶电极之上的所述掩蔽材料以形成自对准过孔;由接触所述顶电极的所述自对准过孔互连中沉积的导电材料形成互连;以及在所述导电材料上形成金属化。
附图说明
借助本公开的示例性实施例的非限制性示例,参考所提到的多个附图,在下面的详细说明中描述了本公开。
图1示出了根据本公开的方面的顶电极、开关材料和底电极,以及其它特征和相应的制造工艺。
图2示出了根据本公开的方面的用于制造沟槽和过孔结构的后镶嵌光刻和蚀刻图案化。
图3示出了根据本公开的方面的与顶电极对准的自对准过孔,以及其它特征和相应的制造工艺。
图4示出了根据本公开的方面的自对准过孔内的后金属化结构,以及其它特征和相应的制造工艺。
图5和6示出了根据本公开的另外的方面的具有限定自对准过孔的间隔物(spacer)材料的替代结构,以及相应的制造工艺。
图7和8示出了根据本公开的另外的方面的具有限定自对准过孔的衬里(liner)材料的替代结构,以及相应的制造工艺。
图9示出了根据本公开的另外的方面的具有限定自对准过孔的间隔物材料和衬里材料的另一替代结构,以及相应的制造工艺。
具体实施方式
本公开涉及半导体结构,更具体地,顶电极互连结构,以及制造方法。更具体地说,本公开提供了嵌入在金属层中的存储器件的到布线顶电极的坚固互连结构以及制造方法。作为说明性非限制性示例,顶电极互连结构可以在诸如RRAM、PRAM和MRAM之类的存储器件中实现。
有利地,本公开提供了一种缩小顶电极材料厚度的手段,其中顶电极的电阻较低,以便互连到上布线层。此外,本公开以与双过孔图案化工艺相比降低的成本,针对到顶电极的上金属连接提供了更宽的蚀刻工艺窗口。本文所述的工艺还为顶电极互连结构提供了自形成过孔。另外,几乎没有或根本没有诸如用于过孔图案化的非挥发性硬聚合物之类的缺陷。此外,实现本文公开的结构和方法提供了去除用于双镶嵌图案化(其中顶电极金属在湿法蚀刻或清洁工艺期间受到保护)的硬掩模(例如,TiN)的自由。
在实施例中,顶电极是下金属结构和上金属结构之间的互连结构的一部分。互连结构例如包括使用自形成过孔图案化工艺而被互连到顶电极的柱特征的上金属。可以在不使用过孔光掩模的情况下形成到顶电极的互连结构,从而节省了相当大的成本。在另外的实施例中,顶电极自形成过孔源于顶电极顶部上的牺牲硬掩模材料(其已用于顶电极光刻和蚀刻图案化工艺)并由其生成。在实施例中,硬掩模材料可以在形成顶电极/开关材料/底电极之后被留下,然后通过在用于到上金属层的互连结构的图案化工艺期间(例如,在层级间介电材料的沉积和平坦化工艺之后)采用的干法或湿法蚀刻工艺选择性地被去除。作为示例,自形成过孔包括具有介电衬里或间隔物的各种类型的特征。
可以使用许多不同的工具以多种方式制造本公开的结构。但是,一般而言,这些方法和工具用于形成尺寸为微米和纳米级的结构。用于制造本公开的结构的方法(即,技术)已经从集成电路(IC)技术中采用。例如,该结构构建在晶片上,并且通过在晶片顶部执行光刻工艺而图案化的材料膜实现。具体而言,结构的制造使用三个基本构建块:(i)在衬底上沉积材料薄膜,(ii)通过光刻成像在膜的顶上施加图案化掩模,以及(iii)对掩模选择性地蚀刻所述膜。
图1示出了根据本公开的方面的顶电极、开关材料和底电极,以及其它特征和相应的制造工艺。更具体地说,图1的结构10包括下金属化特征12,例如导电布线结构,其嵌入在绝缘体材料14内。在实施例中,导电布线结构12可以包括用于逻辑或外围器件的导电布线结构12a和用于存储位单元阵列的导电布线结构12b。导电布线结构12a、12b可以由任何常规使用的金属或金属合金材料形成。例如,导电布线结构12a、12b可以是铜。作为示例,绝缘体材料14可以是基于氧化物的材料。在实施例中,绝缘体材料14可以是例如SiO2、TEOS、FTEOS、低k或超低k SiCOH等。
在实施例中,导电布线结构12a、12b通过本领域技术人员公知的常规光刻、蚀刻和沉积方法形成。例如,在绝缘体材料14之上形成的抗蚀剂暴露于能量(光)下以形成图案(开口)。将使用具有选择性化学过程的蚀刻工艺(例如反应离子蚀刻(RIE)),通过抗蚀剂的开口在绝缘体材料14中形成一个或多个沟槽。然后可以通过常规的氧灰化工艺或其它公知的剥离剂去除抗蚀剂。在去除抗蚀剂之后,可以通过任何常规的沉积工艺(例如化学气相沉积(CVD)工艺)来沉积导电材料。可以通过常规的化学机械抛光(CMP)工艺去除绝缘体材料14的表面上的任何残余材料。
仍然参考图1,在形成导电布线结构12之后,可以在位于导电布线结构12之上的绝缘体材料14的表面上沉积蚀刻停止层或扩散阻挡层16。蚀刻停止层或扩散阻挡层16例如可以是氮化物,诸如SiCN、SiN、AlN等。在蚀刻停止层或扩散阻挡层16中形成开口,以暴露导电布线结构12b的表面。
底电极材料18、开关材料20、顶电极材料22和硬掩蔽材料24依次沉积在蚀刻停止层或扩散阻挡层16之上。在实施例中,这些材料的沉积可以通过任何常规的沉积工艺实现,其中包括例如物理气相沉积(PVD)、化学气相沉积(CVD)、等离子体增强CVD(PECVD)工艺、原子层沉积(ALD)等等。底电极材料18与导电布线结构12b直接电接触。
材料18、20、22例如可以是TiN、TaN、WN、Al、Ru、Ir、Pt、Ag、Au、Co、W、Cu或多层导电膜的组合。顶电极22上的硬掩蔽材料24可以是基于碳的有机物,诸如CxHy、CxHyNz;氧化物,诸如SixOy、AlxOy、SiOxCy、高k氧化物;氮化物,诸如SixNy、SiOxNy、AlxNy、AlOxNy;非晶或多晶Si,或它们的多堆叠材料。在进一步的实施例中,硬掩蔽材料24可以是单膜层或多层膜,其中氧化物、氮化物、Si和有机物与本文所述的任何材料结合。材料18、20、22和24通过常规的光刻和蚀刻工艺而被图案化以形成具有垂直对准的侧壁的垂直柱26。垂直柱26与导电布线结构12b直接接触。
仍然参考图1,在垂直柱26和蚀刻停止层或扩散阻挡层16之上沉积介电材料28。介电材料28可以是氧化物材料,诸如SiO2、TEOS、FTEOS、低k或超低SiCOH等,或它们的任何组合。可以通过常规的CVD、PECVD或ALD工艺沉积介电材料28,然后执行平面化工艺。在实施例中,平面化工艺可以是CMP或回蚀工艺。或者,可以通过旋涂和固化/干燥工艺施加介电材料28。
图2示出了用于制造沟槽Mx+1和过孔Vx的后镶嵌光刻和蚀刻图案化工艺。更具体地说,在图2中,沟槽Mx+1和过孔Vx可以使用双镶嵌工艺或多个单镶嵌工艺形成。在实施例中,在去除硬掩蔽材料24之前,可以在过孔Vx中留下或清除蚀刻停止层或扩散阻挡层16。在实施例中,用于沟槽Mx+1的蚀刻工艺可以比材料叠层(例如,垂直柱26)宽,从而允许改善自对准特征的裕量(margin)。过孔Vx将暴露导电布线结构12a的表面。
在图3中,通过干法或湿法蚀刻工艺去除硬掩蔽材料24。干法或湿法蚀刻工艺将对于硬掩蔽材料24的材料具有选择性,从而消除了对任何掩蔽步骤的需要。硬掩蔽材料24的去除将形成自对准过孔30,从而暴露顶电极22。在实施例中,可以在硬掩蔽材料的去除期间或之后去除蚀刻停止层或扩散阻挡层16。在任一种情况下,蚀刻停止层或扩散阻挡层16的去除将暴露导电布线结构12a的表面。
图4示出了根据本公开的方面的后金属化结构和相应的制造工艺。在实施例中,在自对准过孔30、沟槽Mx+1和过孔Vx内沉积导电材料32。自对准过孔30内的导电材料32将是与顶电极22和上金属Mx+1直接电接触的互连29。这可以在不需要额外的掩蔽步骤的情况下实现。互连29将具有与垂直柱26对准的垂直侧壁。对于互连和布线结构,金属化可以结合使用诸如Cu、W、Al、Co、Ru等之类的金属和诸如TiN、TaN、WN等之类的扩散阻挡材料。在金属化(例如,沉积金属和阻挡材料)之后,将使用CMP工艺去除任何多余的材料。
图5和6示出了根据本公开的另外的方面的具有间隔物材料的替代结构以及相应的制造工艺。在图5所示的结构10a中,在垂直柱26上的硬掩蔽材料24的侧壁上设置间隔物材料24a。在实施例中,可以在通过常规沉积、光刻和蚀刻工艺沉积并图案化硬掩蔽材料24之后沉积间隔物材料24a。间隔物材料24a可以是氮化物材料,诸如SixNy、SiCxNy、AlxNy、SiOxNy、AlOxNy等;或氧化物材料,诸如SiOx、SiOxCy、TiOx、AlOx等。
在图6中,沟槽Mx+1和过孔Vx使用双镶嵌或多个单镶嵌工艺形成,如关于图2所述。硬掩蔽材料24通过干法或湿法蚀刻工艺去除,如关于图3所述。然而,在此工艺中,将不去除间隔物材料24a,从而限定(围绕)自对准过孔30。在实施例中,导电材料32被沉积在自对准过孔30、沟槽Mx+1和过孔Vx内,如关于图4详细描述的。在该实施例中,互连29将具有台阶式或比垂直柱26的轮廓更窄的横截面。
图7和8示出了根据本公开的另外的方面的具有衬里材料的替代结构以及相应的制造工艺。在图7所示的结构10b中,在整个垂直柱26的侧壁上,例如,在材料18、20、22、24上,设置衬里材料24b。在实施例中,衬里材料24b通过常规沉积工艺(例如,CVD)而被沉积在垂直柱26上,厚度为约1nm至约5nm。衬里材料24b可以是氮化物材料,诸如SixNy、SiCxNy、AlxNy、SiOxNy、AlOxNy等;或氧化物材料,诸如SiOx、SiOxCy、TiOx、AlOx等。在沉积衬里材料24b之后,执行各向异性蚀刻工艺以从结构10a的水平表面,例如,硬掩蔽材料24和蚀刻停止层或扩散阻挡层16上方,去除衬里材料24b。
在图8中,在垂直柱26(包括衬里材料24b)和蚀刻停止层或扩散阻挡层16之上沉积介电材料28,如关于图1所述。使用双镶嵌或多个单镶嵌工艺形成沟槽Mx+1和过孔Vx,如关于图2所述。通过干法或湿法蚀刻工艺去除硬掩蔽材料,如关于图3所述。然而,在此工艺中,将不去除衬里材料24b,从而限定(围绕)自对准过孔30。在实施例中,在自对准过孔30、沟槽Mx+1和过孔Vx内沉积导电材料32,如关于图4详细描述的。互连29将具有与垂直柱26对准的垂直侧壁。
图9示出了根据本公开的另外的方面的替代结构10c以及相应的制造工艺。在实施例中,替代结构10c包括限定自对准过孔30的双间隔物,即,间隔物材料24a和衬里材料24b。本领域普通技术人员应该理解,用于构造图9的结构10c的制造工艺是图5至图8的结构和相应制造工艺的组合,因此在此不需要进一步说明。
上述方法用于集成电路芯片的制造。所得到的集成电路芯片可以由制造商以原始晶片形式(即,作为具有多个未封装芯片的单个晶片),作为裸管芯或以封装形式分发。在后一种情况下,芯片以单芯片封装(例如塑料载体,其引线固定到母板或其它更高级别的载体)或多芯片封装(例如陶瓷载体,其具有表面互连和/或掩埋互连)的形式安装。在任何情况下,芯片然后与其它芯片、分立电路元件和/或其它信号处理器件集成,作为(a)中间产品(例如母板)或(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品,其范围从玩具和其它低端应用到具有显示器、键盘或其它输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已经出于说明的目的给出,但并非旨在是穷举的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下,许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的选择旨在最好地解释各实施例的原理、实际应用或对市场中发现的技术的技术改进,或者使本技术领域的其他普通技术人员能理解本文披露的各实施例。
Claims (20)
1.一种半导体结构,包括:
下金属化特征;
上金属化特征;
与所述下金属化特征直接接触的底电极;
位于所述底电极之上的一种或多种开关材料;
位于所述一种或多种开关材料之上的顶电极;
与所述顶电极和所述上金属化特征接触的自对准过孔互连;以及
侧壁间隔物,其接触并完全围绕所述过孔互连的整个侧壁,仅在由所述顶电极的顶表面和所述上金属化特征的底表面限定的空间内延伸,并且接触所述顶电极的所述顶表面和所述上金属化特征的所述底表面。
2.根据权利要求1所述的结构,其中所述结构是存储器件。
3.根据权利要求2所述的结构,其中所述存储器件是电阻式RAM、相变RAM或磁性RAM。
4.根据权利要求2所述的结构,进一步包括外围器件或逻辑器件,所述外围器件或逻辑器件包括通过没有任何介于中间的材料的互连结构而被连接在一起的所述下金属化特征和所述上金属化特征。
5.根据权利要求1所述的结构,其中所述自对准过孔互连位于暴露所述顶电极的自形成自对准过孔中。
6.根据权利要求5所述的结构,其中所述侧壁间隔物限定所述自形成自对准过孔并围绕所述自对准过孔互连。
7.根据权利要求5所述的结构,进一步包括衬里材料,所述衬里材料限定所述自形成自对准过孔并围绕所述顶电极、所述一种或多种开关材料、所述底电极和所述自对准过孔互连。
8.根据权利要求7所述的结构,其中所述侧壁间隔物位于所述衬里材料的内侧上,所述间隔物材料限定所述自形成自对准过孔并围绕所述自对准过孔互连。
9.根据权利要求1所述的结构,其中所述顶电极由一种或多种导电材料形成,所述导电材料包括:TiN、TaN、WN、Al、Ru、Ir、Pt、Ag、Au、Co、W、Cu或它们的多层膜组合。
10.根据权利要求1所述的结构,其中所述底电极、所述一种或多种开关材料、所述顶电极和围绕所述自对准过孔互连的所述侧壁间隔物具有垂直对准的侧壁,从而形成垂直柱结构。
11.一种半导体结构,包括:
存储器件,其包括:
第一金属化层;
第二金属化层;
将所述第一金属化层连接到所述第二金属化层的垂直柱,所述垂直柱包括与所述垂直柱的顶电极和所述第二金属化层接触的自对准过孔互连;以及
侧壁间隔物,其接触并完全围绕所述过孔互连的整个侧壁,仅在由所述顶电极的顶表面和所述第二金属化层的底表面限定的空间内延伸,并接触所述顶电极的所述顶表面和所述第二金属化层的所述底表面;以及
外围器件或逻辑器件,所述外围器件或逻辑器件包括通过没有所述自对准过孔互连和所述垂直柱的互连结构而被连接在一起的所述第一金属化层和所述第二金属化层。
12.根据权利要求11所述的结构,其中所述存储器件是电阻式RAM、相变RAM或磁性RAM。
13.根据权利要求11所述的结构,其中所述自对准过孔互连位于暴露所述顶电极的自形成自对准过孔中。
14.根据权利要求13所述的结构,其中所述侧壁间隔物限定所述自形成自对准过孔并围绕所述自对准过孔互连。
15.根据权利要求13所述的结构,其中所述垂直柱在所述自形成自对准过孔处具有比所述顶电极更窄的横截面。
16.根据权利要求14所述的结构,进一步包括衬里材料,所述衬里材料限定所述自形成自对准过孔并围绕所述垂直柱和所述自对准过孔互连。
17.根据权利要求11所述的结构,其中所述垂直柱和围绕所述自对准过孔互连的所述侧壁间隔物具有垂直对准的侧壁,从而形成垂直柱结构。
18.一种制造半导体结构的方法,包括:
形成垂直柱,所述垂直柱包括底电极、一种或多种开关材料、顶电极和位于所述顶电极上的掩蔽材料,所述掩蔽材料的侧壁具有设置在其上的侧壁间隔物;
在所述垂直柱之上形成层级间介电材料;
对所述层级间介电材料进行开口以暴露所述掩蔽材料;
选择性地去除所述顶电极之上的所述掩蔽材料以形成自对准过孔;
由接触所述顶电极的所述自对准过孔中沉积的导电材料形成过孔互连;以及
在所述导电材料上形成金属化,
其中,所述侧壁间隔物接触并完全围绕所述过孔互连的整个侧壁,仅在由所述顶电极的顶表面和所述金属化的底表面限定的空间内延伸,并且接触所述顶电极的所述顶表面和所述金属化的所述底表面。
19.根据权利要求18所述的方法,其中所述掩蔽材料是基于碳的有机物、氧化物、氮化物、非晶或多晶Si,或它们的组合。
20.根据权利要求18所述的方法,进一步包括在去除之前位于所述侧壁间隔物的外侧壁上的衬里,在去除后,所述侧壁间隔物限定所述过孔互连。
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Also Published As
Publication number | Publication date |
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CN111211109A (zh) | 2020-05-29 |
TWI745765B (zh) | 2021-11-11 |
US20200161236A1 (en) | 2020-05-21 |
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US11810853B2 (en) | 2023-11-07 |
US20220216148A1 (en) | 2022-07-07 |
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TW202027224A (zh) | 2020-07-16 |
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