TWI745765B - 頂部電極互連結構 - Google Patents
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- TWI745765B TWI745765B TW108137702A TW108137702A TWI745765B TW I745765 B TWI745765 B TW I745765B TW 108137702 A TW108137702 A TW 108137702A TW 108137702 A TW108137702 A TW 108137702A TW I745765 B TWI745765 B TW I745765B
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Abstract
本發明有關於半導體結構且特別是有關於頂部電極互連結構與製造方法。該結構包含:一下部金屬化特徵;一上部金屬化特徵;一底部電極,與該下部金屬化特徵直接接觸;一或多個開關材料,在該底部電極上方;一頂部電極,在該一或多個開關材料上方;以及一自對準通孔互連,與該頂部電極和該上部金屬化特徵接觸。
Description
本發明有關於半導體結構且特別是有關於嵌入於積體電路(IC)之互連結構的記憶體與製造方法。
在例如RRAM(電阻RAM)、PRAM(相變RAM)、MRAM(磁性RAM)、FRAM(鐵電RAM)等嵌入式記憶體裝置中形成用於頂部電極的互連的當前方法面臨許多挑戰。這些記憶體裝置包含底部金屬化和頂部金屬化,其中在這些金屬層之間具有頂部電極、開關材料和底部電極。
舉例來說,當在鑲嵌線蝕刻的過程中形成頂部電極互連以露出頂部電極時,存在挑戰。在這種相減方法中,對蝕刻減法製程存在狹窄的製程窗口。如果蝕刻太淺,則連接具有高電阻。如果蝕刻太深,則存在短路到開關層的風險。為了解決這些問題,通常將頂部電極製造得較厚,而如果頂部電極材料太厚而不能光學透明,則反過來又需要額外的覆蓋遮罩。
如果使用通孔圖案化製程(而不是線),則在頂部電極互連製造程序期間也遇到挑戰。在這種類型的製程中,通孔可能會在非記憶體通孔落在下面的金屬層上之前先落在頂部電極上。在這種情況下,頂部電極在蝕刻製程期間的損耗很高。因此,使用了較厚的頂部電極,這會導致上述問題。由於記憶體位元的高度必須遠小於單一通孔高度,因此這類型的
頂部電極互連也受到縮放的限制。
在本發明一態樣中,一種結構包含:一下部金屬化特徵;一上部金屬化特徵;一底部電極,與該下部金屬化特徵直接接觸;一或多個開關材料,在該底部電極上方;一頂部電極,在該一或多個開關材料上方;以及一自對準通孔互連,與該頂部電極和該上部金屬化特徵接觸。
在本發明一態樣中,一種結構,包含:一記憶體裝置,包含:一第一金屬化層;一第二金屬化層;以及一垂直柱,其將該第一金屬化層連接至該第二金屬化層,該垂直柱包含與該垂直柱的一頂部電極和該第二金屬化層接觸的一自對準通孔互連;以及一週邊裝置或邏輯裝置,其包含該下部金屬化特徵和該上部金屬化特徵,該下部金屬化特徵和該上部金屬化特徵藉由沒有該自對準通孔互連和該垂直柱的一互連結構連接在一起。
在本發明一態樣中,一種方法,包含:形成一垂直柱,其包含一底部電極、一或多個開關材料、一頂部電極、以及在該頂部電極上的一遮罩材料;在該垂直柱上形成一層間介電材料;打開該層間介電材料以暴露該遮罩材料;選擇性地移除在該頂部電極上的該遮罩材料,以形成一自對準通孔;藉由在該自對準通孔互連中的沉積導電材料來形成一互連,其與該頂部電極接觸;以及在該導電材料上形成一金屬化層。
10:結構
10a:結構
10b:結構
10c:結構
12:導電佈線結構
12a:導電佈線結構
12b:導電佈線結構
14:絕緣體材料
16:蝕刻停止層或擴散阻擋層
18:底部電極材料
20:開關材料
22:頂部電極材料
24:硬式遮罩材料
24a:間隙壁材料
24b:襯層材料
26:垂直柱
28:介電材料
29:互連
30:自對準通孔
32:導電材料
Mx+1:溝槽
Vx:通孔
利用本發明示範具體實施例的非限制範例,參考提及的許多圖式,從下列詳細描述當中描述本發明。
圖1顯示了根據本發明各態樣的頂部電極、開關材料、和底部電極及其他特徵以及相應的製造程序。
圖2顯示了根據本發明各態樣的後鑲嵌微影和蝕刻圖案化製程,用以製造溝槽和通孔結構。
圖3顯示了根據本發明各態樣的與一頂部電極對準的自對準通孔及其他特徵以及相應的製造程序。
圖4顯示了根據本發明各態樣的在自對準通孔內的後金屬化結構和相應的製造程序。
圖5和圖6顯示根據本發明另一態樣的定義自對準通孔具有間隙壁材料的替代結構以及相應的製造程序。
圖7和圖8顯示了根據本發明另一態樣的定義自對準通孔具有襯層材料的替代結構和相應的製造程序。
圖9顯示了根據本發明另外態樣的定義自對準通孔具有間隙壁材料與襯層材料的替代結構和相應的製造程序。
本發明有關於半導體結構且特別是有關於頂部電極互連結構與製造方法。更具體而言,本發明提供堅固的互連結構以金屬線連接內嵌於金屬層的記憶體裝置的頂部電極與製造方法。頂部電極互連結構可施作於記憶體裝置,例如RRAM、PRAM與MRAM,其作為舉例而非限定的實施例。
有利地,本發明提供了一種縮減頂部電極材料厚度的手段,其具有較低的頂部電極電阻用於互連至上部佈線層。此外,本發明針對上部金屬與頂部電極的連接提供了更寬的蝕刻製程窗口,其成本低於雙通孔圖案化製程。本文所述的製程還提供了用於頂部電極互連結構的自形成通孔。此外,幾乎沒有缺陷,例如用於通孔圖案化的非揮發性硬質聚合物。此外,實施本文所揭露的結構和方法提供了移除硬式遮罩(例如,TiN)的自由,其中硬式遮罩用於雙鑲嵌圖案化以在濕式蝕刻或清潔製程期間保
護頂部電極金屬。
在具體實施例中,頂部電極是下部和上部金屬結構之間的互連結構的一部分。舉例來說,互連結構包含使用自形成通孔圖案化製程而互連到頂部電極的柱狀特徵的上部金屬。可在沒有通孔遮罩的情況下形成到頂部電極的互連結構,從而節省了可觀的成本。在另外的具體實施例中,頂部電極自形成通孔是由在頂部電極的頂部上的犧牲硬式遮罩材料所開始和產生的,其已用於頂部電極微影和蝕刻圖案化製程。在具體實施例中,可在形成頂部電極/開關材料/底部電極之後留下硬式遮罩材料,然後藉由在互連結構到上部金屬層的圖案化製程期間揭示的乾式或濕式蝕刻製程來選擇性地移除硬式遮罩材料(例如,在層間介電材料的沉積和平坦化製程之後)。作為示例,自形成通孔包含帶有介電襯層或間隙壁的各種類型的特徵。
本發明的結構可用許多不同工具以許多方式來製造。一般來說,該等方法與工具用來形成尺寸為毫米與奈米等級的結構。用來製造本發明結構的該等方法,即技術,採用積體電路(IC)技術,例如:這些結構建立在晶圓上,並且藉由在晶圓頂部上以光微影蝕刻處理來製作圖案的材料膜來實現。尤其是,該等結構的製造使用三種基本構件:(i)將材料薄膜沉積在一基材上,(ii)利用光微影蝕刻成像將一製圖光罩應用於該等薄膜頂端上,以及(iii)依照該光罩的選擇來蝕刻該等薄膜。
圖1顯示了根據本發明各態樣的頂部電極、開關材料、和底部電極及其他特徵以及相應的製造程序。更具體地,圖1的結構10包含嵌入在絕緣體材料14內的下部金屬化特徵12(例如導電佈線結構)。在具體實施例中,導電佈線結構12可包含用於邏輯或週邊裝置的導電佈線結構12a以及用於記憶體位元胞陣列的導電佈線結構12b。導電佈線結構12a、12b可由任何傳統使用的金屬或金屬合金材料形成。舉例來說,導電佈線結構12a、12b可為銅。舉例來說,絕緣體材料14可為基於氧化物的材料。在具體實施例
中,絕緣體材料14可例如為SiO2、TEOS、FTEOS、低k或超低k SiCOH等。
在具體實施例中,藉由所屬技術領域中具有通常知識者已知的傳統微影、蝕刻和沈積方法來形成導電佈線結構12a、12b。舉例來說,將形成在絕緣體材料14上的抗蝕劑暴露於能量(光)以形成圖案(開口)。具有選擇性化學作用的蝕刻製程(例如反應性離子蝕刻(RIE))將用以通過抗蝕劑的開口在絕緣體材料14中形成一或多個溝槽。接著,可藉由傳統的氧灰化製程或其他已知的剝離劑來移除抗蝕劑。在移除抗蝕劑之後,可藉由任何傳統的沉積製程(例如化學氣相沉積(CVD)製程)來沉積導電材料。絕緣體材料14的表面上的任何殘留材料都可藉由傳統的化學機械拋光(CMP)製程來移除。
仍參考圖1,在形成導電佈線結構12之後,可在導電佈線結構12上方的絕緣材料14的表面上沉積蝕刻停止層或擴散阻擋層16。蝕刻停止層或擴散阻擋層16可例如為氮化物,如SiCN、SiN、AlN等。在蝕刻停止層或擴散阻擋層16中形成開口,以暴露出導電佈線結構12b的表面。
底部電極材料18、開關材料20、頂部電極材料22、和硬式遮罩材料24依序沉積在蝕刻停止層或擴散阻擋層16上方。在具體實施例中,這些材料的沉積可藉由任何傳統的沉積製程來進行(包含例如物理氣相沉積(PVD)、化學氣相沉積(CVD)、電漿增強CVD(PECVD)製程、原子層沉積(ALD)等)。底部電極材料18與導電佈線結構12b直接電接觸。
材料18、20、22可例如為TiN、TaN、WN、Al、Ru、Ir、Pt、Ag、Au、Co、W、Cu、或多層導電膜的組合。頂部電極22上的硬式遮罩材料24可為碳基有機物,例如CxHy、CxHyNz、氧化物(例如SixOy、AlxOy、SiOxCy、高k氧化物)、氮化物(例如SixNy、SiOxNy、AlxNy、AlOxNy)、非晶或多晶矽、或它們的多層堆疊材料。在進一步的具體實施例中,硬式遮罩材料24可為具有與本文所述的任何材料結合的氧化物、氮化物、Si和有機物的單膜層或多層膜。材料18、20、22和24藉由傳統的微影和蝕刻製程來
進行圖案化,以形成具有垂直對準的側壁的垂直柱26。垂直柱26與導電佈線結構12b直接接觸。
仍參考圖1,介電材料28沉積在垂直柱26和蝕刻停止層或擴散阻擋層16上。介電材料28可為氧化物材料,例如SiO2、TEOS、FTEOS、低k或超低SiCOH等、或它們的任何組合。可藉由傳統的CVD、PECVD、或ALD製程、並接著進行平坦化製程來沉積介電材料28。在具體實施例中,平坦化製程可為CMP或回蝕刻製程。替代地,可藉由旋塗和固化/乾燥製程來施加介電材料28。
圖2顯示了後鑲嵌微影和蝕刻圖案化製程,用以製造溝槽Mx+1和通孔Vx。更具體地說,在圖2中,可使用雙鑲嵌或多個單鑲嵌製程來形成溝槽Mx+1和通孔Vx。在具體實施例中,在移除硬式遮罩材料24之前,可在通孔Vx中留下或清除蝕刻停止層或擴散阻擋層16。在具體實施例中,溝槽Mx+1的蝕刻製程可比材料堆疊(例如,垂直柱26)更寬,從而為自對準特徵提供了改善的裕度。通孔Vx將暴露出導電佈線結構12a的表面。
參照圖3,藉由乾式或濕式蝕刻製程來移除硬式遮罩材料24。乾式或濕式蝕刻製程將對硬式遮罩材料24的材料具有選擇性,從而無需任何遮罩步驟。硬式遮罩材料24的移除將產生自對準通孔30,其暴露了頂部電極22。在具體實施例中,可在移除硬式遮罩材料的過程中或之後將蝕刻停止層或擴散阻擋層16移除。在任一情況下,蝕刻停止層或擴散阻擋層16的移除將暴露出導電佈線結構12a的表面。
圖4顯示了根據本發明各態樣的後金屬化結構和相應的製造程序。在具體實施例中,導電材料32沉積在自對準通孔30、溝槽Mx+1和通孔Vx內。自對準通孔30內的導電材料32將為與頂部電極22和上部金屬Mx+1直接電接觸的互連29。無需額外的遮罩步驟即可完成此操作。互連29將具有與垂直柱結構26對準的垂直側壁。金屬化可使用金屬(例如Cu、W、Al、Co、Ru等)與擴散阻擋材料(例如TiN、TaN、WN等)結合,用於互連和
佈線結構。在金屬化(例如沉積金屬和阻擋材料)之後,將使用CMP製程來移除任何多餘的材料。
圖5和圖6顯示根據本發明另一態樣的具有間隙壁材料的替代結構以及相應的製造程序。在圖5所示的結構10a中,在垂直柱26上的硬式遮罩材料24的側壁上提供間隙壁材料24a。在具體實施例中,可在藉由傳統的沉積、微影和蝕刻製程沉積並圖案化硬式遮罩材料24之後,沉積間隙壁材料24a。間隙壁材料24a可為氮化物材料(例如SixNy、SiCxNy、AlxNy、SiOxNy、AlOxNy等),或者氧化物材料(例如SiOx、SiOxCy、TiOx、AlOx等)。
在圖6中,使用雙鑲嵌或多個單鑲嵌製程形成溝槽Mx+1和通孔Vx,如關於圖2所述。藉由乾式或濕式蝕刻製程來移除硬式遮罩材料24,如關於圖3所作的描述。然而,在此過程中,將不移除間隙壁材料24a,藉此定義(環繞的)自對準通孔30。在具體實施例中,導電材料32沉積在自對準通孔30、溝槽Mx+1、及通孔Vx內,如關於圖4所作的詳細描述。在此具體實施例中,互連29將具有階梯狀或比垂直柱結構26的輪廓更窄的橫截面。
圖7和圖8顯示了根據本發明另一態樣的具有襯層材料的替代結構和相應的製造程序。在圖7所示的結構10b中,在整個垂直柱26的側壁上(例如在材料18、20、22、24上)設置襯層材料24b。在具體實施例中,藉由傳統的沉積製程(例如CVD)將襯層材料24b沉積在垂直柱26上至約1nm至約5nm的厚度。襯層材料24b可為氮化物材料(例如SixNy、SiCxNy、AlxNy、SiOxNy、AlOxNy等),或為氧化物材料(例如SiOx、SiOxCy、TiOx、AlOx等)。在沉積襯層材料24b後,進行異向性蝕刻製程以從結構10b的水平表面(例如在硬式遮罩材料24和蝕刻停止層或擴散阻擋層16上方)移除襯層材料24b。
在圖8中,介電材料28沉積在垂直柱26(包含襯層材料24b)和蝕刻停止層或擴散阻擋層16上,如關於圖1所述。溝槽Mx+1和通孔Vx是
使用雙鑲嵌或多個單鑲嵌製程形成的,如關於圖2所述。藉由乾式或濕式蝕刻製程來移除硬式遮罩材料,如關於圖3所述。然而,在此過程中,將不移除襯層材料24b,藉此定義(環繞的)自對準通孔30。在具體實施例中,導電材料32沉積在自對準通孔30、溝槽Mx+1、及通孔Vx內,如關於圖4所作的詳細描述。互連29將具有與垂直柱結構26對準的垂直側壁。
圖9顯示了根據本發明另外態樣的替代結構10c和相應的製造程序。在具體實施例中,替代結構10c包含定義了自對準通孔30的雙間隙壁,亦即間隙壁材料24a和襯層材料24b。如所屬技術領域中具有通常知識者應理解的,用於建構圖9的結構10c的製造程序為圖5到圖8的結構及相應製造程序的組合,因此此處不需進一步的解釋。
上述該(等)方法用於積體電路晶片製造。結果積體電路晶片可由製造廠以原始晶圓形式(也就是具有多個未封裝晶片的單一晶圓)、當成裸晶粒或已封裝形式來散佈。在後者案例中,晶片固定在單晶片封裝內(像是塑膠載體,具有導線黏貼至主機板或其他更高層載體)或固定在多晶片封裝內(像是一或兩表面都具有表面互連或內嵌互連的陶瓷載體)。然後在任何案例中,晶片與其他晶片、離散電路元件以及/或其他信號處理裝置整合成為(a)中間產品,像是主機板,或(b)末端產品。末端產品可為包括積體電路晶片的任何產品,範圍從玩具與其他低階應用到具有顯示器、鍵盤或其它輸入裝置以及中央處理器的進階電腦產品。
許多本發明具體實施例的描述已經為了說明而呈現,但非要將本發明受限在所公布形式中。在不脫離所描述具體實施例之範疇與精神的前提下,本技術之一般技術者將瞭解許多修正例以及變化例。本文內使用的術語係為了能最佳解釋具體實施例的原理、市場上所發現技術的實際應用或技術改進,或可讓精通技術人士能理解本文所揭示的具體實施例。
12:導電佈線結構
12a:導電佈線結構
12b:導電佈線結構
14:絕緣體材料
16:蝕刻停止層或擴散阻擋層
18:底部電極材料
20:開關材料
22:頂部電極材料
26:垂直柱
28:介電材料
29:互連
30:自對準通孔
32:導電材料
Claims (20)
- 一種半導體結構,包含:一下部金屬化特徵;一上部金屬化特徵;一底部電極,與該下部金屬化特徵直接接觸;一或多個開關材料,在該底部電極上方;一頂部電極,直接接觸該一或多個開關材料;一通孔互連,與該頂部電極之一頂面和該上部金屬化特徵之一底面接觸;以及一間隙壁材料,接觸與圍繞該通孔互連的一側壁,且接觸該頂部電極之該頂面和該上部金屬化特徵之該底面;其中該間隙壁材料的一外側壁表面是與該一或多個開關材料、該頂部電極和該底部電極之每一者的一側壁共平面。
- 如申請專利範圍第1項所述的結構,更包含一週邊裝置或邏輯裝置,其包含藉由沒有任何中間材料的一互連結構而連接在一起的該下部金屬化特徵和該上部金屬化特徵。
- 如申請專利範圍第1項所述的結構,其中該通孔互連為一自對準通孔互連,其暴露且對準該頂部電極。
- 如申請專利範圍第3項所述的結構,其中該間隙壁材料定義並圍繞該自對準通孔互連。
- 如申請專利範圍第3項所述的結構,更包含一垂直對準襯層材 料,其定義該自對準通孔互連並直接接觸且圍繞該頂部電極、該一或多個開關材料、該底部電極和該間隙壁材料之該外側壁表面,以及該襯層材料藉由該間隙壁材料而與該自對準通孔互連隔開。
- 如申請專利範圍第5項所述的結構,其中該間隙壁材料在該垂直對準襯層材料的一內側上,其定義並圍繞該自對準通孔互連。
- 如申請專利範圍第1項所述的結構,其中該頂部電極由以下的一或多種導電材料形成:TiN、TaN、WN、Al、Ru、Ir、Pt、Ag、Au、Co、W、Cu或其多層膜的組合。
- 如申請專利範圍第1項所述的結構,其中該底部電極、該一或多個開關材料、該頂部電極和圍繞該通孔互連的該間隙壁材料具有形成一垂直柱結構的多個垂直對準側壁,該等垂直對準側壁更包含接觸該底部電極的一擴散阻擋層。
- 一種半導體結構,包含:一第一金屬化層;一第二金屬化層;以及一垂直柱,其將該第一金屬化層連接至該第二金屬化層,該垂直柱包含一對準通孔互連與圍繞該對準通孔互連的一間隙壁,該對準通孔互連與該間隙壁兩者接觸該垂直柱的一頂部電極和該第二金屬化層;一週邊裝置或邏輯裝置,其包含該第一金屬化層和該第二金屬化層,該第一金屬化層和該第二金屬化層藉由沒有該對準通孔互連和該垂直柱的一互連結構連接在一起;以及一擴散阻擋材料,接觸該該第一金屬化層與該底部電極, 其中該間隙壁的一外側壁表面與該頂部電極的一邊緣具有多個共平面側壁,且一襯層材料在該等共平面側壁之上且接觸該等共平面側壁以形成一垂直柱結構。
- 如申請專利範圍第9項所述的結構,其中該對準通孔互連在一通孔中,其暴露該頂部電極且更包含接觸該間隙壁、該垂直柱之一側壁與該擴散阻擋材料的一側壁結構。
- 如申請專利範圍第10項所述的結構,其中該間隙壁定義該自形成自對準通孔並完全圍繞且直接接觸該自對準通孔互連與一側壁結構,並且該側壁結構接觸該垂直柱之一外表面。
- 如申請專利範圍第11項所述的結構,其中該垂直柱在該自形成自對準通孔處具有比該頂部電極更窄的一橫截面。
- 如申請專利範圍第11項所述的結構,其中該襯層材料定義該自形成自對準通孔並圍繞該垂直柱和該自對準通孔互連。
- 一種半導體結構,包含:一下部金屬化特徵;一上部金屬化特徵;一底部電極,與該下部金屬化特徵直接接觸;一或多個開關材料,在該底部電極上方;一頂部電極,在該一或多個開關材料上方;一通孔互連,與該頂部電極和該上部金屬化特徵接觸;一間隙壁材料,接觸與圍繞該通孔互連的一側壁,且接觸該頂部電極 之一頂面和該上部金屬化特徵之一底面;以及一擴散阻擋材料,直接接觸該下部金屬化特徵與該底部電極;其中該底部電極、該一或多個開關材料,該頂部電極與該間隙壁材料之一外表面的每一者的多個側壁是互相共平面,且與形成一垂直柱結構的該通孔互連共平面。
- 如申請專利範圍第14項所述的結構,其中該通孔互連是一自對準通孔互連,該頂部電極直接接觸該一或多個開關材料。
- 如申請專利範圍第14項所述的結構,更包含一週邊裝置或邏輯裝置,其包含藉由沒有任何中間材料的一互連結構而連接在一起的該下部金屬化特徵和該上部金屬化特徵。
- 如申請專利範圍第1項所述的結構,更包含多個垂直對準側壁,其沿著該通孔互連之一側壁的全部。
- 如申請專利範圍第1項所述的結構,更包含一垂直對準側壁材料,其直接接觸與沿著該底部電極、該一或多個開關材料、該頂部電極與該間隙壁材料之該外側壁表面的一垂直對準側壁的全部,並且該間隙壁材料是在該側壁材料的一內表面與該通孔互連之一外表面之間且接觸該側壁材料的該內表面與該通孔互連之該外表面。
- 如申請專利範圍第1項所述的結構,更包含一垂直對準側壁材料,其直接接觸與沿著該底部電極、該一或多個開關材料與該頂部電極的一垂直對準側壁的全部以及該間隙壁材料之該外側壁表面,該通孔互連在橫截面上是小於該底部電極、該一或多個開關材料與該頂部電極的該垂 直對準側壁,並且該間隙壁材料直接接觸該垂直對準側壁材料而位於該垂直對準側壁材料之下,並且該半導體結構更包含直接接觸該下部金屬化特徵與該間隙壁材料的一擴散阻擋材料。
- 如申請專利範圍第9項所述的結構,其中該垂直柱包含一底部電極,其直接接觸該第一金屬化層與一或多個開關材料,該一或多個開關材料在該底部電極上方直接接觸該頂部電極。
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