CN111179829B - 具有外部补偿和阳极复位的有机发光二极管显示器 - Google Patents

具有外部补偿和阳极复位的有机发光二极管显示器 Download PDF

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Publication number
CN111179829B
CN111179829B CN202010050007.XA CN202010050007A CN111179829B CN 111179829 B CN111179829 B CN 111179829B CN 202010050007 A CN202010050007 A CN 202010050007A CN 111179829 B CN111179829 B CN 111179829B
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transistor
light emitting
display pixel
emitting diode
display
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CN111179829A (zh
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林敬伟
小野晋也
V·古普塔
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Apple Inc
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Apple Inc
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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Abstract

本申请涉及具有外部补偿和阳极复位的有机发光二极管显示器。具体而言，显示器可以包括有机发光二极管显示器像素阵列，其具有通过受到晶体管变化影响的阈值电压来表征的晶体管。补偿电路可用于测量像素的晶体管阈值电压。可以通过控制像素以将阈值电压采样到像素处的电容器上来对阈值电压进行采样。像素可包括至少一个半导体氧化物晶体管、硅晶体管和发光二极管。二极管可以耦接到数据线，该数据线可以用于数据加载和补偿感测操作。可以在数据编程之后并且在发射之前执行复位操作以复位二极管的阳极电压。

Description

具有外部补偿和阳极复位的有机发光二极管显示器
本申请是申请日为2018年3月14日、发明名称为“具有外部补偿和阳极复位的有机发光二极管显示器”的中国专利申请201880014878.7的分案申请。
本专利申请要求2017年11月2日提交的美国专利申请15/802,367以及2017年3月24日提交的临时专利申请62/476,562的优先权，这些专利申请据此全文以引用方式并入本文。
技术领域
本公开整体涉及具有显示器的电子设备，更具体地，涉及用于显示器诸如有机发光二极管显示器的显示驱动器电路。
背景技术
电子设备通常包括显示器。例如，蜂窝电话和便携式计算机包括用于向用户呈现信息的显示器。
显示器(诸如有机发光二极管显示器)具有基于发光二极管的显示器像素阵列。在这种类型的显示器中，每个显示器像素都包括发光二极管和用于控制信号施加到发光二极管以产生光的薄膜晶体管。
有机发光二极管显示器像素包括经由接入薄膜晶体管连接到数据线的驱动薄膜晶体管。接入晶体管可具有栅极端子，其经由对应的扫描线接收扫描信号。可以通过认定扫描信号以导通接入晶体管而将数据线上的图像数据加载到显示器像素中。显示器像素包括电流源晶体管，该电流源晶体管向有机发光二极管提供电流以产生光。
有机发光二极管显示器像素中的晶体管可经受工艺、电压和温度(PVT)变化。由于这种变化，不同显示器像素之间的晶体管阈值电压可以变化。晶体管阈值电压的变化可能导致显示器像素产生与目标图像不匹配的光量。补偿方案有时用于补偿阈值电压的变化。这种补偿方案通常涉及在正常显示操作期间在每个像素内执行的采样操作并且因此增加了显示图像所需的时间。
正是在这种情况下，产生本文的实施方案。
发明内容
电子设备可包括具有显示器像素阵列的显示器。显示器像素可以是有机发光二极管显示器像素。每个显示器像素可具有发光的有机发光二极管。每个显示器像素中的驱动晶体管(即，电流源晶体管)可以向该显示器像素中的有机发光二极管施加电流。驱动晶体管可以通过阈值电压来表征。
阈值电压可能受到晶体管变化的影响。补偿电路可用于测量驱动晶体管的阈值电压。可以通过控制驱动晶体管以将阈值电压采样到在电流源晶体管的栅极和源极端子之间耦接的电容器上来对阈值电压进行采样。补偿电路可以包括感测电路，该感测电路可以与像素组合操作以将电荷从电容器传输到感测电路，使得在感测电路的输出处产生阈值电压。补偿电路可以基于测量的阈值电压生成补偿数据。在显示操作期间，数据电路可以接收数字图像数据并处理数字图像数据以及补偿数据以生成用于像素的模拟数据信号。
可以为每个像素或像素组生成阈值电压补偿数据。补偿数据可以存储在诸如易失性或非易失性存储器的存储器中。补偿数据可以存储为偏移值(例如，相对于参考阈值电压归一化)。在显示操作期间，数据电路可以将偏移值添加到数字图像数据。相加的数字值可以用于生成补偿像素之间的阈值电压变化的模拟像素数据信号。
显示器像素还可以包括发射控制晶体管(例如，与驱动晶体管和发光二极管串联耦接的晶体管)、栅极电压设置晶体管(例如，用于将驱动晶体管的栅极端子设定为预定参考电压水平的晶体管)、数据加载晶体管(例如，用于将数据加载到像素中并且还用于感测驱动晶体管的阈值电压的晶体管)以及阳极复位晶体管(例如，用于复位发光二极管的阳极端子的晶体管)。数据编程操作之后可以进行阳极复位操作。阳极复位操作可以帮助消除低灰度不均匀性问题，消除低刷新率闪烁，并提高可变刷新率指数。
附图说明
图1是根据一个实施方案的具有显示器的例示性电子设备的图示。
图2是根据一个实施方案的具有耦接到补偿电路的有机发光二极管显示器像素阵列的例示性显示器的图示。
图3是根据一个实施方案的由n沟道薄膜晶体管形成的例示性显示器像素的电路图。
图4是示出根据一个实施方案的操作图3中所示的显示器像素的相关波形的时序图。
图5A和图5B是示出根据一个实施方案的阳极复位如何能够有助于消除低灰度等级下的阳极充电不均匀性问题的时序图。
图6A是示出根据一个实施方案的如何能够在相邻行中的像素之间共享至少一些行控制线的图示。
图6B是示出根据一个实施方案的操作具有共享行控制线的显示器像素中的相关波形的时序图。
图7是根据一个实施方案的由n沟道半导体氧化物晶体管和p沟道硅晶体管形成的例示性显示器像素的电路图。
图8是示出根据一个实施方案的操作图7中所示的显示器像素的相关波形的时序图。
图9A是示出根据一个实施方案的如何能够在图7中所示类型的相邻像素之间共享至少一些行控制线的图示。
图9B是示出根据一个实施方案的操作图9A中所示的显示器像素的相关波形的时序图。
图10是根据至少一些实施方案的用于操作结合图2至图9所示类型的显示器像素的例示性步骤的流程图。
具体实施方式
图1中示出了可以装备有机发光二极管(OLED)显示器的类型的例示性电子设备。如图1所示，电子设备10可以具有控制电路16。控制电路16可以包括用于支持设备10的操作的存储和处理电路。存储和处理电路可以包括存储装置，诸如硬盘驱动器存储装置、非易失性存储器(例如，被配置为形成固态驱动器的闪存存储器或其他电可编程只读存储器)、易失性存储器(例如，静态或动态随机存取存储器)等等。控制电路16中的处理电路可以被用于控制设备10的操作。处理电路可基于一个或多个微处理器、微控制器、数字信号处理器、基带处理器、电源管理单元、音频编解码芯片、专用集成电路、可编程集成电路等。
设备10中的输入-输出电路诸如输入-输出设备12可以被用于允许将数据供应给设备10以及允许将数据从设备10提供给外部设备。输入-输出设备12可包括按钮、操纵杆、点击轮、滚轮、触控板、小键盘、键盘、麦克风、扬声器、音频发生器、振动器、摄像机、传感器、发光二极管和其他状态指示器、数据端口等。用户可通过经由输入-输出设备12提供命令来控制设备10的操作并且可使用输入-输出设备12的输出资源从设备10接收状态信息和其他输出。
输入-输出设备12可包括一个或多个显示器，诸如显示器14。显示器14可为包括用于采集来自用户的触摸输入的触摸传感器的触摸屏显示器，或者显示器14可对触摸不敏感。显示器14的触摸传感器可基于电容性触摸传感器电极的阵列、声学触摸传感器结构、电阻性触摸部件、基于力的触摸传感器结构、基于光的触摸传感器，或其他合适的触摸传感器布置。
控制电路16可用于运行设备10上的软件，诸如操作系统代码和应用程序。在设备10的操作期间，运行控制电路16上的软件可以在输入-输出设备中的显示器14上显示图像。
图2示出了显示器14和相关的显示驱动器电路15。显示器14包括形成于诸如基板24的一个或多个层上的结构。诸如基板24的层可由诸如平面玻璃层的材料的平面矩形层形成。显示器14可具有显示器像素22的阵列以用于向用户显示图像。显示器像素22的阵列可由在基板24上的显示器像素结构的行和列形成。这些结构可包括薄膜晶体管，诸如多晶硅薄膜晶体管、半导体氧化物薄膜晶体管等。在显示器像素22的阵列中可以有任意适当数量的行和列(例如，十个或更多个、一百个或更多个、或者一千个或更多个)。
可以利用焊料或导电粘合剂将显示驱动器电路(诸如显示驱动器集成电路15)耦接到导电路径诸如基板24上的金属迹线。如果需要，显示驱动器集成电路15可以通过诸如柔性印刷电路或其他缆线的路径耦接到基板24。显示驱动器集成电路15(有时称为定时控制器芯片)可包括用于通过路径125与系统控制电路16通信的通信电路。路径125可由柔性印刷电路上的迹线或其他缆线形成。控制电路16(参见图1)可位于电子设备(诸如为蜂窝电话、计算机、电视、机顶盒、媒体播放器、便携式电子设备、或正在使用显示器14的其他电子装置)中的主逻辑板上。
在操作期间，控制电路可以为显示驱动器集成电路15提供要在显示器14上显示的图像的信息。为了在显示器像素22上显示图像，显示驱动器集成电路15可以向显示驱动器电路，诸如行驱动器电路18和列驱动器电路20，提供时钟信号和其他控制信号。例如，数据电路17可以接收图像数据并处理图像数据以向显示器14提供像素数据信号。像素数据信号可以由列驱动器电路20解复用，并且像素数据信号D可以通过数据线26路由到每个像素22(例如，路由到每个红色像素、绿色像素或蓝色像素)。行驱动器电路18和/或列驱动器电路20可由一个或多个集成电路和/或一个或多个薄膜晶体管电路形成。
显示驱动器集成电路15可以包括补偿电路17，该补偿电路有助于补偿显示器像素22之间的变化，诸如阈值电压变化。如果需要，补偿电路17还可以帮助补偿晶体管老化。补偿电路17可以经由路径19、切换电路21和路径23耦接到像素22。补偿电路17可以包括感测电路25和偏压电路27。感测电路25可以用于感测(例如，采样)来自像素22的电压。在感测操作期间，切换电路21可被配置为将感测电路25电耦接到一个或多个选定像素22。例如，补偿电路17可以产生控制信号CTL以配置切换电路21。感测电路25可以从路径19、切换电路21和路径23上的像素采样诸如阈值电压或其他期望信号的电压。偏压电路27可以包括用于将参考电压或偏压电压驱动到像素22的节点上的一个或多个驱动器电路。例如，切换电路21可以被配置为将路径19电耦接到一个或多个选定像素22。在这种情况下，偏压电路27可以向选定像素提供参考信号。参考信号可以将在选定像素处的节点偏压在期望电压，用于由感测电路25执行的感测操作。
补偿电路17可以使用偏压电路27和感测电路25对像素22执行补偿操作，以生成存储在存储装置29中的补偿数据。存储装置29例如可以是静态随机存取存储器(SRAM)。在图2的示例中，存储装置29是片上存储装置。如果需要，存储装置29可以是片外存储装置，诸如非易失性存储器(例如，即使在显示器断电时也保持所存储信息的非易失性存储器)。存储在存储装置29中的补偿数据可以在显示操作期间由数据电路13检索。数据电路13可以处理补偿数据以及输入的数字图像数据，以生成用于像素22的补偿数据信号。
数据电路13可以包括γ电路44，该γ电路提供数字图像数据到用于驱动像素22的适当电压水平的模拟数据信号的映射。多路复用器46从γ电路44接收一组可能的模拟数据信号，并由数字图像数据控制，以选择适合于数字图像数据的模拟数据信号。从存储装置29检索的补偿数据可以由加法器电路48添加到数字图像数据(或从数字图像数据中减去)，以帮助补偿不同显示器像素22之间的晶体管变化(例如，阈值电压变化、晶体管老化变化或其他类型的变化)。将补偿数据作为补偿添加到数字输入图像数据的示例仅仅是例示性的。通常，数据电路13可以与图像数据一起处理补偿数据，以产生用于驱动像素22的补偿模拟数据信号。
相比于专注执行像素内阈值取消的技术(诸如通过执行复位阶段，然后进行阈值补偿阶段)，以这种方式使用每个像素22外部的补偿电路17来执行补偿允许更高的刷新率(例如，大于60Hz的刷新率，至少120Hz的刷新率等)并且有时被称为“外部”补偿。外部变化补偿可以在工厂中实时地(例如，在连续图像帧之间的消隐间隔期间)或者当显示器空闲时(作为示例)执行。
行驱动器电路18可以位于显示器14的左边缘和右边缘上，仅在显示器14的单个边缘上，或在显示器14中的别处。在操作期间，行驱动器电路18可在水平线28(有时称为行线、“扫描”线、和/或“发射”线)上提供行控制信号。行驱动器电路可以包括用于驱动扫描线的扫描线驱动器电路和用于驱动发射线的发射驱动器电路。
解复用电路20可用于将来自显示驱动器集成电路(DIC)15的数据信号D提供到多个对应的竖直线26上。解复用电路20有时可以称为列驱动器电路、数据线驱动器电路或源驱动器电路。竖直线26有时称为数据线。在显示操作期间，可以使用线26将显示数据加载到显示器像素22中。
每一数据线26都与相应列的显示器像素22相关联。多组水平信号线28通过显示器14水平延伸。每组水平信号线28都与相应行的显示器像素22相关联。每行中的水平信号线的数量由被水平信号线独立控制的显示器像素22中的晶体管的数量决定。可由不同数量的扫描线来操作不同配置的显示器像素。
行驱动器电路18可以认定诸如显示器14中的行线28上的扫描和发射信号的控制信号。例如，驱动器电路18可从显示驱动器集成电路15接收时钟信号和其他控制信号，并可响应于所接收的信号认定每行显示器像素22中的扫描控制信号和发射控制信号。可以依次处理显示器像素22的行，针对每帧图像数据的处理开始于显示器像素阵列的顶部，并结束于阵列的底部(作为示例)。在认定行中的扫描线时，由DIC15提供给列驱动器电路20的控制信号和数据信号可以指示列驱动器电路20对关联的数据信号D(例如，由数据电路13提供的补偿数据信号)解复用并驱动到数据线26上，从而将利用出现在数据线D上的显示数据来对行中的显示器像素进行编程。然后显示器像素能够显示加载的显示数据。
在有机发光二极管显示器中，每个显示器像素22都包含相应的有机发光二极管。图3中示出了耦接到补偿电路17的例示性有机发光二极管显示器像素22的电路图。如图3所示，显示器像素22可包括发光二极管300、n沟道薄膜晶体管310、312、314、316和318以及存储电容器Cst1。特别地，晶体管312有时被称为“驱动”晶体管。晶体管310和312以及二极管300可以串联耦接在第一电源线302(例如，上面设置有正电源电压VDDEL的正电源线)和第二电源线304(例如，上面设置有接地电压VSSEL的接地电源线)之间。晶体管310具有栅极端子，该栅极端子接收在发射控制线28-4上提供的发射控制信号EM；因此，晶体管310有时被称为发射控制晶体管。存储电容器Cst1可以具有分别耦接到驱动晶体管312的栅极和源极端子的第一端子和第二端子。
晶体管314可以耦接在竖直线23(例如，沿着给定列向每个像素22提供参考电压Vref的共享路径)和驱动晶体管312的栅极(G)之间。晶体管314具有栅极端子，该栅极端子接收扫描控制信号SCAN1并且被选择性地导通以将驱动晶体管312的栅极电压设置为预定电压水平(例如，电压水平Vref)。因此，晶体管314有时被称为栅极电压设置晶体管。
晶体管316可以耦接在竖直线26(例如，耦接到列驱动器电路20的数据线)和二极管300的阳极端子之间。晶体管316具有栅极端子，该栅极端子接收扫描控制信号SCAN2并且被选择性地导通以将数据信号加载到像素22中。因此，晶体管316有时被称为数据加载晶体管。
晶体管318可以耦接在参考电压线23和发光二极管300的阳极端子之间。晶体管318具有栅极端子，该栅极端子接收扫描控制信号SCAN3并且被选择性地导通以将二极管300的阳极复位到参考电压水平Vref。因此，晶体管318有时被称为阳极复位晶体管。
根据一种在本文中有时描述为示例的合适布置，显示器14上的一些薄膜晶体管中的沟道区(有效区域)由硅(例如，硅诸如使用低温工艺沉积的多晶硅，有时称为LTPS或低温多晶硅)形成，并且在显示器14上的其他薄膜晶体管中的沟道区由半导体氧化物材料(例如，非晶态的氧化铟镓锌，有时称为IGZO)形成。如果需要，则其他类型的半导体可用于形成薄膜晶体管诸如非晶硅、除了IGZO之外的半导体氧化物等。在这种类型的混合显示器配置中，硅晶体管(例如，LTPS晶体管)可在期望的属性诸如切换速度和良好驱动电流的情况下使用(例如，对于液晶二极管显示器中的栅极驱动器或者考虑切换速度的有机发光二极管显示器像素的部分)，而氧化物晶体管(例如，IGZO晶体管)可用于需要低漏电流(例如，在液晶二极管显示器像素和显示驱动器电路中)或需要高像素-像素均匀性(例如，在有机发光二极管显示器像素阵列中)的地方。其他注意事项也可被考虑(例如，与功率消耗、占位面积消耗、迟滞等相关的注意事项)。
诸如IGZO薄膜晶体管的氧化物晶体管通常是n沟道器件(即，NMOS晶体管)。硅晶体管可以使用p-沟道或n-沟道设计制成(即，LTPS设备可以是PMOS或NMOS)。这些薄膜晶体管结构的组合可以提供最佳性能。
在图3的示例中，晶体管314可以是半导体氧化物晶体管，而其他晶体管310、312、316和318是硅晶体管(例如，n沟道LTPS晶体管)。由于驱动晶体管312的栅极(G)处的阻抗高，所以将半导体氧化物晶体管314耦接到该节点可能有利于帮助减少泄漏和功耗。
在图3的布置中，不仅使用线26执行数据加载，而且还能够在数据线26上执行电流感测。换句话说，图1中所示的补偿电路17的感测电路25可以与数据编程电路共享相同的数据线26。如果没有在同一数据线26上执行数据编程和电流感测，则有必要为每个像素列包括单独的感测路径(即线23也需要支持电流感测)，这将大大增加阵列路由的复杂性和面积。因此，通过数据线26执行数据编程和电流感测可以帮助显著降低阵列布线复杂性和面积，因为全局参考电压线23可以耦接到每个像素列(例如，参考线23可以在显示器像素阵列中的不同列之间共享)。
图4是示出图3中所示的操作显示器像素22中的相关波形的时序图。在时间t1之前，仅认定信号EM(例如，发射控制信号EM被驱动为高到逻辑“1”)，而所有其他扫描控制信号SCAN1、SCAN2、SCON3对于该行被解除认定(例如，扫描控制信号被驱动为低到逻辑“0”)。信号EM被认定的周期可以被称为发射周期T发射或发射阶段。
在时间t2处，扫描信号SCAN1可被认定以导通晶体管314。激活晶体管314可以允许驱动晶体管312的栅极被设置为参考电压水平Vref。在时间t3处，扫描信号SCAN2可被认定以导通晶体管316。激活晶体管316可以允许沿线26呈现的数据信号被加载到显示器像素中(例如，数据信号可以被加载到发光二极管300的阳极端子上)。在信号SCAN2的下降沿处的数据信号的值(在时间t4处)确定实际加载到显示器像素中的内容。时间t2和t4之间的周期可以称为数据编程周期T数据_编程或数据写入阶段。当前数据信号对于该行应当保持恒定的持续时间表示为一个单位编程时间1H(显示为TPROG)。
在时间t5处，信号SCAN1被解除认定。此时，电容器Cst1上的电压是固定的(例如，存储在Cst1中的电压等于Vref和编程数据值之间的差值)。
在时间t6处，仅扫描信号SCAN3可被认定以导通晶体管318。激活晶体管318可以允许发光二极管300的阳极被复位到参考电压水平Vref。因为晶体管314断开，所以此时电容器Cst1上的电压不能改变。因此，将阳极电压水平复位为Vref将简单地将驱动晶体管312的栅极水平向上(或向下)移位Vref与刚加载到阳极中的数据值之间的差值。驱动晶体管312的栅极-源极电压不应改变。在时间t7处，扫描信号SCAN3被解除认定。时间t6和t7之间的周期可以被称为阳极复位周期T阳极_复位或阳极复位阶段。在该示例中，扫描控制信号SCAN1和SCAN2的认定在时间上重叠，而扫描控制信号SCAN1和SCAN3的认定在时间上不重叠。
在时间t8处，发射控制信号EM可以针对发射阶段认定。在发射阶段期间，电流将流过晶体管310和312以及发光二极管300，其中电流的大小取决于存储在电容器Cst1上的电压。电流量将影响从二极管300发射的光的实际亮度。
图5A和图5B是示出执行阳极复位如何能够有助于消除低灰度等级下的阳极充电不均匀性问题的时序图。图5A绘制了作为时间函数的阳极电压水平。电压水平VON表示OLED导通电压阈值。如果数据信号被设置为第一灰度等级V1，则波形500表示阳极电压水平。如果数据信号被设置为第二灰度等级V2，则波形502表示阳极电压水平。如图5A所示，阳极的电压将充电但在不同时间将达到阈值VON。因此，与波形500相关联的发射周期TE1和与波形502相关联的发射周期TE2将略微不同，从而导致阳极充电不均匀。图5B示出了这将如何对平均亮度水平产生负面影响，因为对于具有不同灰度等级的像素，发射周期将是不同的。低灰度等级会加剧这个问题。
根据一个实施方案，在数据加载之后和发射之前执行阳极复位消除了低灰度不均匀性问题。此外，即使当显示器仅以低刷新率(例如，30Hz或更低)操作时，阳极复位操作也可以帮助模拟高频刷新率(例如，60Hz、120Hz等)，从而消除低刷新率闪烁并改善可变刷新率指数。
图6A是示出如何在相邻行中的像素之间共享至少一些行控制线的图示。如图6A所示，诸如级600的栅极驱动级可以驱动在像素22-1和22-2以及两行中的其他像素之间共享的行控制信号SCAN1、SCAN3和EM，并且还可以驱动仅馈送到像素22-1和第一行中的其他像素的信号SCAN2_ODD以及仅被馈送到像素22-2和第二行中的其他像素的信号SCAN2_EVEN。栅极驱动级600可以表示行驱动器电路18中的级链中的一个级(参见图2)。虽然信号SCAN1、SCAN3和EM可以在多个相邻行之间共享，但是信号SCAN2不能被共享，因为它控制数据加载(例如，不同的像素需要加载不同的数据信号以保持完整的显示分辨率)。
图6B是示出操作具有共享行控制线的显示器像素中的相关波形的时序图，如图6A的配置中所示。在时间t1之前，仅认定信号EM，同时所有其他扫描控制信号SCAN1、SCAN2_ODD、SCAN2_EVEN和SCAN3针对那两行解除认定。
在时间t2处，共享扫描信号SCAN1可被认定以导通像素22-1和22-2两者中的晶体管314(参见图6A)。在时间t3处，扫描信号SCAN2_ODD可被认定以导通像素22-1中的晶体管316(以及沿着该行的其他像素)。在时间t4处，扫描信号SCAN2_EVEN可被认定以导通像素22-2中的晶体管316(以及沿着该行的其他像素)。在时间t5处，信号SCAN2_ODD可以被解除认定以将数据信号“A”锁存到像素22-1中。在时间t6处，信号SCAN2_EVEN可以被解除认定以将数据信号“B”锁存到像素22-2中。在时间t7处，信号SCAN1可以被解除认定。
在时间t8处，共享扫描信号SCAN3可被认定以导通像素22-1和22-2两者中的晶体管318以执行阳极复位操作。在时间t9处，信号SCAN3可以被解除认定。在时间t10处，共享发射控制信号EM可被认定以开始发射阶段。图6B的示例性定时方案仅仅是例示性的并不用于限制本实施方案的范围，其中发射周期是8H持续时间(即，单位数据编程周期的8倍)，SCAN1周期是4H，并且SCAN2和SCAN3周期是1.5H。如果需要，只要正确执行数据编程和阳极复位，这些周期可以延长或缩短并及时向前或向后移位。通常，行控制线的共享可以扩展到任何数量的相邻行(例如，行控制线可以在三行或更多行、四行或更多行、五行或更多行之间共享等)。
图7示出了另一种合适的布置，其中像素22包括n沟道半导体氧化物晶体管和p沟道硅晶体管，其中像素22可以耦接到图2的补偿电路17。如图7所示，显示器像素22可包括发光二极管300、n沟道薄膜晶体管312'和314、310'、p沟道薄膜晶体管316'和318'以及存储电容器Cst1。晶体管312'可以被称为“驱动”晶体管。晶体管310'和312'以及二极管300可以串联耦接在第一电源线302和第二电源线304之间。晶体管310'具有接收发射控制信号EM的栅极端子。存储电容器Cst1可以具有分别耦接到驱动晶体管312'的栅极和源极端子的第一端子和第二端子。
晶体管314可以耦接在参考线23和驱动晶体管312'的栅极(G)端子之间。晶体管314具有栅极端子，该栅极端子接收扫描控制信号SCAN1并且被选择性地导通以将驱动晶体管312'的栅极电压设置为预定电压水平Vref。晶体管316'可以耦接在列线26和二极管300的阳极端子之间。晶体管316'具有栅极端子，该栅极端子接收扫描控制信号SCAN2并且被选择性地导通以将数据信号传送到像素22中。晶体管318'可以耦接在参考电压线23和发光二极管300的阳极端子之间。晶体管318'具有栅极端子，该栅极端子接收扫描控制信号SCAN3并且被选择性地导通以将二极管300的阳极复位到参考电压水平Vref。
在图7的示例中，晶体管314和312'可以是半导体氧化物晶体管，而其他晶体管310'、316'和318'是硅晶体管(例如，p沟道LTPS晶体管)。由于驱动晶体管312'的栅极(G)处的阻抗高，所以将半导体氧化物晶体管314耦接到该节点可能有利于帮助减少泄漏和功耗。驱动晶体管通常是n型，因此将晶体管312'保持为半导体氧化物晶体管以简化制造可能是有利的(例如，将驱动晶体管312'形成为n型LTPS晶体管必然会增加光刻掩模的数量，从而增加制造成本)。在图7的布置中，数据编程和电流感测也都在数据线26上执行，这可以帮助显著降低阵列路由复杂性和面积。
图8是示出图7中所示的操作显示器像素22中的相关波形的时序图。由于晶体管310'、316'和318'现在是p沟道晶体管，对应的控制信号EM、SCAN2和SCAN3是低水平有效信号(即，认定意味着这些信号被驱动到逻辑“0”)。在时间t1之前，仅认定信号EM(例如，发射控制信号EM被驱动为低至逻辑“0”)，而所有其他扫描控制信号SCAN1、SCAN2和SCAN3被解除认定(例如，信号SCAN2和SCAN3被驱动为高至逻辑“1”，并且信号SCAN1被驱动为低至逻辑“0”)。信号EM被认定的周期可以被称为发射周期T发射或发射阶段。
在时间t2处，扫描信号SCAN1可被认定(例如，驱动高)以导通晶体管314。激活晶体管314可以允许驱动晶体管312'的栅极被设置为参考电压水平Vref。在时间t3处，扫描信号SCAN2可被认定(例如，驱动低)以导通晶体管316'。激活晶体管316'可以允许沿线26呈现的数据信号被加载到显示器像素中(例如，数据信号可以被加载到发光二极管300的阳极端子上)。在信号SCAN2的下降沿处的数据信号的值(在时间t4处)确定实际加载到显示器像素中的内容。时间t2和t4之间的周期可以称为数据编程周期T数据_编程或数据写入阶段。当前数据信号对于该行应当保持恒定的持续时间表示为一个单位编程时间1H(显示为TPROG)。
在时间t5处，信号SCAN1被解除认定。此时，电容器Cst1上的电压是固定的(例如，存储在Cst1中的电压等于Vref和编程数据值之间的差值)。
在时间t6处，仅扫描信号SCAN3可被认定(例如，驱动低)以导通晶体管318'。激活晶体管318'可以允许发光二极管300的阳极被复位到参考电压水平Vref。因为晶体管314断开，所以此时电容器Cst1上的电压不能改变。因此，将阳极电压水平复位为Vref将简单地将驱动晶体管312'的栅极水平向上(或向下)移位Vref与刚加载到阳极中的数据值之间的差值。驱动晶体管312'的栅极-源极电压不应改变。在时间t7处，扫描信号SCAN3被解除认定。时间t6和t7之间的周期可以被称为阳极复位周期T阳极_复位或阳极复位阶段。在该示例中，扫描控制信号SCAN1和SCAN2的认定在时间上重叠，而扫描控制信号SCAN1和SCAN3的认定在时间上不重叠。
在时间t8处，发射控制信号EM可以针对发射阶段认定。在发射阶段期间，电流将流过晶体管310'和312'以及发光二极管300，其中电流的大小取决于存储在电容器Cst1上的电压。电流量将影响从二极管300发射的光的实际亮度。
通过以这种方式配置，能够在数据加载之后和发射之前执行阳极复位的图7的像素22消除了低灰度不均匀性问题。此外，即使当显示器仅以低刷新率(例如，30Hz或更低)操作时，阳极复位操作也可以帮助模拟高频刷新率(例如，60Hz、120Hz等)，从而消除低刷新率闪烁并改善可变刷新率指数。
图9A是示出如何在相邻行中的像素之间共享至少一些行控制线的图示。如图9A所示，诸如级900的栅极驱动级可以驱动在像素22-1和22-2与两行中的其他像素之间共享的行控制信号SCAN1、SCAN3和EM，并且还可以驱动仅馈送到像素22-1(和第一行中的其他像素)的信号SCAN2_ODD以及仅被馈送到像素22-2(和第二行中的其他像素)的信号SCAN2_EVEN。栅极驱动级900可以表示行驱动器电路18中的级链中的一个级(参见图2)。虽然信号SCAN1、SCAN3和EM可以在多个相邻行之间共享，但是信号SCAN2不能被共享，因为它控制数据加载(例如，不同的像素需要加载不同的数据信号以保持完整的显示分辨率)。
图9B是示出操作具有共享行控制线的显示器像素中的相关波形的时序图，如图9A的配置中所示。在时间t1之前，仅认定信号EM(例如，被驱动低至逻辑“1”)，而对于这两行，所有其他扫描控制信号SCAN1、SCAN2_ODD、SCAN2_EVEN和SCAN3被解除认定(例如，高水平有效信号SCAN1被驱动为低至逻辑“0”，而低水平有效信号SCAN2_ODD、SCAN2_EVEN和SCAN3被驱动为高至逻辑“1”)。
在时间t2处，共享扫描信号SCAN1可被认定以导通像素22-1和22-2两者中的晶体管314(参见图9A)。在时间t3处，扫描信号SCAN2_ODD可被认定以导通像素22-1中的晶体管316'(以及沿着该行的其他像素)。在时间t4处，扫描信号SCAN2_EVEN可被认定以导通像素22-2中的晶体管316'(以及沿着该行的其他像素)。在时间t5处，信号SCAN2_ODD可以被解除认定以将数据信号“X”锁存到像素22-1中。在时间t6处，信号SCAN2_EVEN可以被解除认定以将数据信号“Y”锁存到像素22-2中。在时间t7处，信号SCAN1可以被解除认定。
在时间t8处，共享扫描信号SCAN3可被认定以导通两个像素22-1和22-2两者中的晶体管318以执行阳极复位操作。在时间t9处，信号SCAN3可以被解除认定。在时间t10处，共享发射控制信号EM可被认定以开始发射阶段。图9B的示例性定时方案仅仅是例示性的并不用于限制本实施方案的范围，其中发射周期是8H持续时间(即，单位数据编程周期的8倍)，SCAN1周期是4H，并且SCAN2和SCAN3周期是1.5H。如果需要，只要正确执行数据编程和阳极复位，这些周期可以延长或缩短并及时向前或向后移位。通常，行控制线的共享可以扩展到任何数量的相邻行(例如，行控制线可以在三行或更多行、四行或更多行、五行或更多行之间共享等)。
图10是根据至少一些实施方案的用于操作结合图2至图9所示类型的显示器像素的例示性步骤的流程图。在步骤1000处，可以在发射阶段操作显示器像素22(例如，通过认定发射控制信号EM以允许电流流过驱动晶体管到OLED，同时使扫描控制信号SCAN1、SCAN2和SCAN3解除认定)。
在步骤1002处，可以暂时停止发射阶段(例如，通过暂时使发射控制信号EM解除认定以防止电流流过驱动晶体管到OLED)。
在步骤1004处，可以在数据编程阶段操作像素22以将补偿的图像数据加载到阳极端子中(例如，通过脉冲信号SCAN1和SCAN2来设置驱动晶体管的栅极端子处的电压水平并分别将补偿数据值加载到阳极端子)。
在步骤1006处，像素22可以在阳极复位阶段操作，使得OLED的阳极被偏压到预定的复位/参考电压水平(例如，通过脉冲扫描信号SCAN3)。以这种方式执行阳极复位帮助消除低灰度不均匀性问题，消除低刷新率闪烁，并提高可变刷新率指数。对于显示器像素阵列中的连续行，处理可以循环回到步骤1000，如路径1008所示。
图3和图7中所示的包括五个晶体管、一个电容器、一个发射控制线和三个扫描控制线的示例性像素架构仅仅是例示性的。如果需要，可以将本文描述的技术扩展或应用于包括任何数量的氧化物或硅晶体管、任何数量的电容器、多于一条发射线、少于三条扫描控制线或多于三条扫描控制线以及其他合适的显示器像素架构的像素架构。
根据一个实施方案，提供一种显示器，该显示器包括发光二极管、与发光二极管串联耦接的驱动晶体管、用于将数据加载到发光二极管上的第一晶体管以及用于复位发光二极管的第二晶体管。
根据另一个实施方案，第一晶体管直接连接到发光二极管。
根据另一个实施方案，第二晶体管直接连接到发光二极管。
根据另一个实施方案，显示器包括通过第一晶体管耦接到发光二极管的数据线以及包括感测电路的像素补偿电路，该感测电路耦接到数据线。
根据另一个实施方案，显示器包括用于将参考电压加载到驱动晶体管的栅极端子上的第三晶体管和耦接到第二晶体管和第三晶体管的全局参考电压线。
根据另一个实施方案，第三晶体管是半导体氧化物晶体管，并且驱动晶体管是硅晶体管。
根据另一个实施方案，第三晶体管和驱动晶体管是n沟道晶体管。
根据另一个实施方案，第一晶体管和第二晶体管也是n沟道晶体管。
根据另一个实施方案，第一晶体管和第二晶体管是p沟道晶体管。
根据另一个实施方案，显示器包括耦接在第二晶体管和第三晶体管之间的存储电容器。
根据另一个实施方案，显示器包括：用于向第一晶体管提供第一扫描信号的第一扫描线；用于向第二晶体管提供第二扫描信号的第二扫描线，第二扫描线与第一扫描线不同；以及用于向第三晶体管提供第三扫描信号的第三扫描线，第三扫描线与第一扫描线和第二扫描线不同。
根据一个实施方案，一种用于操作显示器像素的方法，显示器像素包括发光二极管、驱动晶体管、数据加载晶体管，并且提供阳极复位晶体管，该阳极复位晶体管包括：数据加载晶体管，将数据加载到发光二极管上；阳极复位晶体管，使发光二极管复位；以及驱动晶体管，驱动电流通过发光二极管。
根据另一个实施方案，复位发光二极管包括在将数据加载到发光二极管上之后复位发光二极管。
根据另一个实施方案，该方法包括利用补偿电路通过数据加载晶体管在显示器像素上执行感测。
根据另一个实施方案，显示器像素包括发射控制晶体管和栅极电压设置晶体管，该方法包括：利用发射控制晶体管接收发射控制信号，利用栅极电压设置晶体管接收第一扫描控制信号，利用数据加载晶体管接收与第一扫描控制信号不同的第二扫描控制信号，并且利用阳极复位晶体管接收与第一扫描控制信号和第二扫描控制信号不同的第三扫描控制信号。
根据另一个实施方案，第一扫描控制信号和第二扫描控制信号的认定在时间上重叠，并且第一扫描控制信号和第三扫描控制信号的认定在时间上不重叠。
根据一个实施方案，提供了一种电子设备，该电子设备包括第一行中的第一显示器像素、第二行中的第二显示器像素以及栅极驱动级，该栅极驱动级将第一扫描信号输出到第一显示器像素和第二显示器像素，将第二奇数扫描信号输出到第一显示器像素而不是第二显示器像素，并且将第二偶数扫描信号到第二显示器像素而不是第一显示器像素。
根据另一个实施方案，栅极驱动级还被配置为将第三扫描信号和发射控制信号输出到第一显示器像素和第二显示器像素。
根据另一个实施方案，第一行和第二行是阵列中的相邻行。
根据另一个实施方案，第一显示器像素包括：接收发射控制信号的发射晶体管；与发射晶体管串联耦接的驱动晶体管；具有栅极端子的驱动晶体管；与发光晶体管和驱动晶体管串联耦接的发光二极管；具有阳极端子的发光二极管；参考电压线；耦接在参考电压线与驱动晶体管的栅极端之间的栅极电压设置晶体管，栅极电压设置晶体管接收第一扫描信号；数据线；耦接在数据线和发光二极管的阳极端子之间的数据加载晶体管，数据加载晶体管接收第二奇数扫描信号；以及耦接在参考电压线和发光二极管的阳极端之间的阳极复位晶体管，阳极复位晶体管接收第三扫描信号。
前述仅为例示性的，并且在不脱离所述实施方案的范围和实质的情况下，本领域的技术人员可作出各种修改。前述实施方案可独立实施或可以任意组合实施。

Claims (15)

1.一种显示像素，包括：
发光二极管；
驱动晶体管，所述驱动晶体管与发光二极管串联耦接；
数据加载晶体管，所述数据加载晶体管用于将数据加载到所述显示像素中；
电压线；
阳极复位晶体管，所述阳极复位晶体管连接在电压线和发光二极管之间；和
半导体氧化物晶体管，所述半导体氧化物晶体管连接在所述电压线和所述驱动晶体管的栅极端子之间，其中所述阳极复位晶体管是硅晶体管，其中所述半导体氧化物晶体管是在第一时间段激活的，并且其中所述阳极复位晶体管是在所述第一时间段之后的第二时间段激活的。
2.根据权利要求1所述的显示像素，其中所述数据加载晶体管是硅晶体管。
3.根据权利要求1所述的显示像素，其中所述阳极复位晶体管直接连接至所述发光二极管。
4.根据权利要求1所述的显示像素，其中所述显示像素仅包括两个半导体氧化物晶体管。
5.根据权利要求1所述的显示像素，其中所述数据加载晶体管和所述阳极复位晶体管是p型硅晶体管。
6.根据权利要求1所述的显示像素，其中所述显示像素还包括：
发射晶体管，所述发射晶体管与所述驱动晶体管和所述发光二极管串联耦接，其中所述发射晶体管和所述驱动晶体管是硅晶体管。
7.根据权利要求6所述的显示像素，其中所述显示像素仅包括选自由以下各项组成的组中的晶体管：半导体氧化物晶体管和p型硅晶体管。
8.根据权利要求1所述的显示像素，其中所述数据加载晶体管是直接连接至所述驱动晶体管的p型硅晶体管。
9.根据权利要求5所述的显示像素，还包括：
存储电容器，所述存储电容器耦接到所述驱动晶体管的栅极端子。
10.根据权利要求5所述的显示像素，还包括：
第一控制线，所述第一控制线被配置为向所述半导体氧化物晶体管提供第一控制信号；
第二控制线，所述第二控制线不同于第一控制线并且被配置为向所述数据加载晶体管提供第二控制信号；和
第三控制线，所述第三控制线不同于所述第一控制线和所述第二控制线，并且被配置为向所述阳极复位晶体管提供第三控制信号。
11.一种用于操作显示像素的方法，所述显示像素包括发光二极管、驱动晶体管、栅极电压设置晶体管、数据加载晶体管和阳极复位晶体管，所述方法包括：
利用所述数据加载晶体管将数据加载到所述发光二极管上；
利用所述栅极电压设置晶体管接收在第一时间段期间认定的第一扫描控制信号；
利用所述阳极复位晶体管接收在所述第一时间段之后的第二时间段期间认定的第二扫描控制信号以对所述发光二极管进行复位；和
利用所述驱动晶体管驱动电流通过所述发光二极管，其中所述栅极电压设定晶体管和所述阳极复位晶体管连接到同一电压线。
12.根据权利要求11所述的方法，其中所述栅极电压设置晶体管是半导体氧化物晶体管。
13.根据权利要求11所述的方法，其中所述显示像素仅包括两个半导体氧化物晶体管。
14.根据权利要求11所述的方法，其中所述显示像素还包括发射控制晶体管，所述方法还包括：
利用所述发射控制晶体管接收发射控制信号；和
利用所述数据加载晶体管接收与所述第一扫描控制信号和所述第二扫描控制信号不同的第三扫描控制信号。
15.根据权利要求14所述的方法，其中所述第一扫描控制信号和所述第三扫描控制信号的认定在时间上是重叠的，并且其中所述第一扫描控制信号和所述第二扫描控制信号的认定在时间上是不重叠的。
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