CN111095565B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN111095565B
CN111095565B CN201880050073.8A CN201880050073A CN111095565B CN 111095565 B CN111095565 B CN 111095565B CN 201880050073 A CN201880050073 A CN 201880050073A CN 111095565 B CN111095565 B CN 111095565B
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insulating film
interlayer insulating
semiconductor substrate
contact opening
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CN111095565A (zh
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田村隆博
小野泽勇一
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Fuji Electric Co Ltd
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Abstract

本发明提供半导体装置，缓和接触开口的端部处的电流集中。半导体装置具备：阳极区；阴极区；设置于阴极区的上方的埋入区；层间绝缘膜，配置于半导体基板的上表面的上方，并且设置有使阳极区的一部分露出的接触开口；以及在接触开口中与阳极区接触的上表面侧电极，埋入区包含端部埋入区，所述端部埋入区在垂直于半导体基板的上表面的截面中，从接触开口的下方的区域，通过接触开口的端部的下方，连续地设置到层间绝缘膜的下方的区域，在与半导体基板的上表面平行的第1方向上，设置于层间绝缘膜的下方的端部埋入区比设置于接触开口的下方的端部埋入区短。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
以往，已知有在半导体基板上的绝缘膜设置接触用的开口而将半导体基板与阳电极连接的半导体装置(例如，参照专利文献1)。
专利文献1：国际公开2014/156849号
发明内容
技术问题
因为在接触开口的端部容易集中电流，所以优选缓和电流集中。
技术方案
(项目1)
为了解决上述课题，在本发明的一个方式中，提供具备设置有第一导电型的漂移区的半导体基板的半导体装置。半导体装置可以具备设置在半导体基板的上表面与漂移区之间的第二导电型的阳极区。半导体装置可以具备设置在半导体基板的下表面与漂移区之间并且掺杂浓度高于漂移区的掺杂浓度的第一导电型的阴极区。半导体装置可以具备设置于阴极区的上方的第二导电型的埋入区。半导体装置可以具备配置于半导体基板的上表面的上方且设置有使阳极区的一部分露出的接触开口的层间绝缘膜。半导体装置可以具备在接触开口中与阳极区接触的上表面侧电极。埋入区可以包含端部埋入区，所述端部埋入区在垂直于半导体基板的上表面的截面中，从接触开口的下方的区域，通过接触开口的端部的下方，连续地设置到层间绝缘膜的下方的区域。在与半导体基板的上表面平行的第1方向上，设置于层间绝缘膜的下方的端部埋入区可以比设置于接触开口的下方的端部埋入区短。
(项目2)
设置于层间绝缘膜的下方的端部埋入区在第1方向上的长度可以为20μm以上。
(项目3)
埋入区可以以预先设定的狭缝宽度的间隔在第1方向上分离地设置。设置于层间绝缘膜的下方的端部埋入区的第1方向上的长度可以大于狭缝宽度。
(项目4)
在垂直于半导体基板的上表面的截面中，阳极区可以从接触开口的下方的区域，通过接触开口的端部的下方，设置到层间绝缘膜的下方的区域。在第1方向上，设置于层间绝缘膜的下方的端部埋入区可以比设置于层间绝缘膜的下方的阳极区短。
(项目5)
在垂直于半导体基板的上表面的截面中，阴极区可以从接触开口的下方的区域，通过接触开口的端部的下方，设置到层间绝缘膜的下方的区域。在第1方向上，设置于层间绝缘膜的下方的端部埋入区可以比设置于层间绝缘膜的下方的阴极区短。
(项目6)
在第1方向上，设置于层间绝缘膜的下方的端部埋入区可以比设置于层间绝缘膜的下方的阴极区短10μm以上。
(项目7)
在垂直于半导体基板的上表面的截面中，阳极区及阴极区可以从接触开口的下方的区域，通过接触开口的端部的下方，设置到层间绝缘膜的下方的区域。在第1方向上，设置于层间绝缘膜的下方的阴极区可以比设置于层间绝缘膜的下方的阳极区短。
(项目8)
在第1方向上，设置于层间绝缘膜的下方的阴极区的长度可以为设置于层间绝缘膜的下方的阳极区的长度的一半以上。
(项目9)
第1方向上的阴极区的端部与阳极区的端部之间的距离可以大于阳极区的垂直于半导体基板的上表面的第2方向上的厚度。
(项目10)
第1方向上的阴极区的端部与阳极区的端部之间的距离可以大于层间绝缘膜的垂直于半导体基板的上表面的第2方向上的厚度。
(项目11)
在垂直于半导体基板的上表面的截面中，阳极区可以在端部具有弯曲部。阴极区可以不设置在弯曲部的下方。
(项目12)
在第1方向上，设置于接触开口的下方的端部埋入区的长度可以为半导体基板的厚度以上。
应予说明，上述发明内容没有列举出本发明的全部必要特征。另外，这些特征组的子组合还可以成为发明。
附图说明
图1是表示本发明的一个实施方式的半导体装置100的上表面的结构的图。
图2是表示图1所示的A-A截面的一例的图。
图3是放大阳极区16的端部15附近而得的截面图。
图4是表示半导体装置100的另一例中的YZ截面的图。
图5是表示图4中的B-B截面的掺杂浓度分布例的图。
图6是表示比较例的半导体装置200的结构例的图。
图7是表示半导体装置100和半导体装置200的正向电压-正向电流特性的一例的图。
符号说明
10…半导体基板、11…上表面、12…阳电极、13…下表面、14…阴电极、15…端部、16…阳极区、17…弯曲部、18…漂移区、20…缓冲区、22…埋入区、23…端部、24…阴极区、25…端部、26…层间绝缘膜、27…端部、28…保护环、30…端部、35…部分、37…部分、40…寿命控制部、42…峰、56…接触开口、90…边缘终端结构部、100…半导体装置、120…有源部、140…外周端、200…半导体装置
具体实施方式
以下，通过发明的实施方式来说明本发明，但是以下实施方式不限定权利要求所记载的发明。另外，实施方式中所说明的特征的全部组合并非是发明的解决手段所必须的。
在本说明书中，将与半导体基板的深度方向平行的方向上的一侧称为“上”，将另一侧称为“下”。将基板、层或其他部件的2个主面中的一个面称为上表面，将另一个面称为下表面。“上”、“下”的方向并不限于重力方向、或者在安装半导体装置时向基板等安装的方向。
在本说明书中，有可能利用X轴、Y轴及Z轴的直角坐标轴来说明技术事项。在本说明书中，将与半导体基板的上表面平行的面设为XY面，将与半导体基板的上表面垂直的深度方向设为Z轴。
在各实施例中，示出以第一导电型为n型并以第二导电型为p型的例子，但是也可以以第一导电型为p型并以第二导电型为n型。在该情况下，各实施例中的基板、层、区等的导电型为彼此相反的极性。另外，在本说明书中，在记载为p+型(或n+型)的情况下，意味着掺杂浓度比p型(或n型)高，在记载为p-型(或n-型)的情况下，意味着掺杂浓度比p型(或n型)低。
在本说明书中，掺杂浓度是指，施主或受主化了的杂质的浓度。在本说明书中，有时将施主和受主的浓度差作为掺杂浓度(也称为净掺杂浓度或载流子浓度)。另外，有时将掺杂区中的掺杂浓度分布的峰值作为该掺杂区中的掺杂浓度。
图1是表示本发明的一个实施方式的半导体装置100的上表面的结构的图。半导体装置100具备半导体基板10。半导体基板10可以是硅基板，也可以是碳化硅基板，还可以是氮化镓等氮化物半导体基板等。本例的半导体基板10是硅基板。在本说明书中，将俯视下的半导体基板10的外周的端部作为外周端140。俯视是指，从半导体基板10的上表面侧平行于Z轴地观察的情况。
半导体装置100具备有源部120和边缘终端结构部90。有源部120是在将半导体装置100控制为导通状态的情况下在半导体基板10的上表面与下表面之间流通有主电流的区域。也就是说，是电流在半导体基板10的内部沿深度方向从半导体基板10的上表面向下表面、或者从下表面向上表面流通的区域。有源部120还可以被设为在俯视半导体基板10时设置有阳电极等供主电流流通的上表面侧电极的区域。另外，在俯视半导体基板10时上表面侧电极分离的情况下，被夹在2个设置有上表面侧电极的区域之间的区域也可以包含在有源部120中。上表面侧电极可以在整个有源部120中与半导体基板10的上表面接触，也可以局部地与半导体基板10的上表面接触。
在有源部120设置有包含续流二极管(FWD)等二极管元件的二极管部。在有源部120还可以设置有包含绝缘栅双极型晶体管(IGBT)等晶体管元件的晶体管部。二极管部的p型的阳极区与晶体管部的n型的发射区可以连接于共同的上表面侧电极，并且二极管部的n型的阴极区与晶体管部的p型的集电区可以连接于共同的下表面侧电极。二极管部和晶体管部可以在XY面上设置为沿Y轴方向具有长度的条状。二极管部和晶体管部可以在XY面上沿X轴方向交替地配置。
边缘终端结构部90在半导体基板10的上表面，设置在有源部120与半导体基板10的外周端140之间。边缘终端结构部90可以在半导体基板10的上表面以包围有源部120的方式配置为环状。本例的边缘终端结构部90沿半导体基板10的外周端140配置。边缘终端结构部90缓和半导体基板10的上表面侧的电场集中。边缘终端结构部90具有例如保护环、场板、降低表面电场及将它们组合而成的结构。
另外，在有源部120设置有晶体管部的情况下，在半导体基板10的上表面，在边缘终端结构部90与有源部120之间可以设置栅极金属层。在俯视半导体基板10时，栅极金属层可以被设置为包围有源部120。栅极金属层与晶体管部电连接，向晶体管部供给栅极电压。
图2是表示图1所示的A-A截面的一例的图。A-A截面是包含有源部120和边缘终端结构部90的YZ面。图2中的Y轴方向是第1方向的一例，Z轴方向是第2方向的一例。本例的半导体装置100在该截面中具有半导体基板10、层间绝缘膜26、阳电极12及阴电极14。阳电极12是上表面侧电极的一例，阴电极14是下表面侧电极的一例。
层间绝缘膜26覆盖半导体基板10的上表面的一部分而设置。层间绝缘膜26可以是PSG、BPSG等硅酸盐玻璃，也可以是氧化膜或氮化膜等。本例的层间绝缘膜26覆盖整个边缘终端结构部90。另外，在层间绝缘膜26，在有源部120的至少一部分的区域，设置有使半导体基板10的上表面11露出的接触开口56。在有源部120设置有二极管部且不设置晶体管部的情况下，接触开口56可以设置于整个有源部120。在本例中，沿半导体基板10的外周端140，将被平行于外周端140地配置的层间绝缘膜26覆盖的区域设为边缘终端结构部90，并将没有被该层间绝缘膜26覆盖的区域设为有源部120。
阳电极12设置在半导体基板10的上表面11的上方，利用接触开口56而与半导体基板10的上表面11接触。本例的阳电极12与在半导体基板10的上表面11露出地设置的阳极区16接触。阳电极12也可以局部地设置在层间绝缘膜26上。
阴电极14设置在半导体基板10的下表面13。阴电极14可以与半导体基板10的整个下表面13接触。阳电极12和阴电极14由金属等导电材料形成。在本说明书中，将连结阳电极12与阴电极14的方向称为深度方向(Z轴方向)。
在半导体基板10设置有n-型的漂移区18。在漂移区18与半导体基板10的上表面11之间设置有p型的阳极区16。阳极区16设置在包含半导体基板10的上表面11的区域。半导体基板10的上表面11处的阳极区16的至少一部分从接触开口56露出而与阳电极12接触。阳极区16的一部分可以被层间绝缘膜26覆盖。在本例中，在与半导体基板10的上表面11垂直的YZ截面中，阳极区16从接触开口56的下方的区域，通过接触开口56的端部30的下方，连续地设置到层间绝缘膜26的下方的区域。
其中，在该截面中，在边缘终端结构部90的至少一部分的区域不设置阳极区16。在本例中，阳极区16的Y轴方向上的端部15配置在边缘终端结构部90的内部。端部15可以配置在设置于边缘终端结构部90的保护环28中的最靠近有源部120的保护环28与接触开口56的端部30之间。阳极区16的端部15可以是半导体基板10的上表面11处的阳极区16与n型区域之间的边界。阳极区16可以设置于整个有源部120，也可以设置于有源部120的一部分。
在半导体基板10的下表面13与漂移区18之间设置有掺杂浓度高于漂移区18的掺杂浓度的n+型的阴极区24。阴极区24设置在包含半导体基板10的下表面13的区域。阴极区24与阴电极14接触。阴极区24的至少一部分设置于接触开口56的下方。阴极区24可以设置于XY面中的整个有源部120，也可以局部地设置。阴极区24的一部分设置于层间绝缘膜26的下方。在本例中，在与半导体基板10的上表面11垂直的YZ截面中，阴极区24从接触开口56的下方的区域，通过接触开口56的端部30的下方，连续地设置到层间绝缘膜26的下方的区域。
但是，在该截面中，在边缘终端结构部90的至少一部分的区域不设置阴极区24。在不设置阴极区24的区域，在半导体基板10的下表面13可以露出漂移区18，也可以露出后述的缓冲区20。在本例中，在Y轴方向上，阴极区24的端部27配置在边缘终端结构部90的内部。端部27可以在Y轴方向上，配置在设置于边缘终端结构部90的保护环28中的最靠近有源部120的保护环28与接触开口56的端部30之间。阴极区24的端部27可以是在半导体基板10的下表面13，相对于阴极区24中的掺杂浓度的峰值为一半的掺杂浓度的部分。
在半导体基板10的内部，在阴极区24的上方设置有p型的埋入区22。埋入区22可以与阴极区24相接地设置。本例的埋入区22在Z轴方向上，夹在阴极区24与缓冲区20(在未设置缓冲区20的情况下为漂移区18)之间地配置。
埋入区22的至少一部分设置于接触开口56的下方。埋入区22局部设置在XY面中的有源部120。本例的埋入区22在有源部120的Y轴方向上隔开预定的狭缝宽度Ys的间隔而配置。另外，在X轴方向上也可以隔开预定的狭缝宽度的间隔而配置多个埋入区22。X轴方向和Y轴方向上的狭缝宽度可以相同，也可以不同。
将多个埋入区22中的、在垂直于半导体基板10的上表面11的截面中从接触开口56的下方的区域通过接触开口的端部30的下方连续地设置到层间绝缘膜26的下方的区域的埋入区22设为端部埋入区22-e。端部埋入区22-e可以是Y轴方向上离半导体基板10的外周端140最近的埋入区22。
应予说明，埋入区22不与阴电极14接触。本例的埋入区22整体设置在阴极区24上。端部埋入区22-e的Y轴方向上的端部中的、外周端140侧的端部23配置在边缘终端结构部90的内部。端部23可以在Y轴方向上配置在设置于边缘终端结构部90的保护环28中的、最靠近有源部120的保护环28与接触开口56的端部30之间。端部埋入区22-e的Y轴方向上的端部中的、与端部23相反侧的端部25配置在有源部120的内部。
本例的半导体装置100在漂移区18与半导体基板10的下表面13之间具有n型的缓冲区20。本例的阴极区24配置在缓冲区20与半导体基板10的下表面13之间。本例的埋入区22配置在缓冲区20与阴极区24之间。
在没有设置阴极区24的区域，缓冲区20(在未设置缓冲区的情况下为漂移区18)在半导体基板10的下表面13露出。缓冲区20的掺杂浓度高于漂移区18的掺杂浓度。缓冲区20可以作为防止从阳极区16的下表面侧扩散的耗尽层到达阴极区24的场截止层而起作用。
本例的边缘终端结构部90具有1个以上保护环28。各保护环28以包围有源部120的方式在XY面中设置为环状。各保护环28在XY面中可以设置为同心状。本例的保护环28是从半导体基板10的上表面11设置到预定的深度位置的p型的区域。通过设置保护环28，能够使从阳极区16与漂移区18之间扩散的耗尽层延伸到半导体基板10的外周端140的附近。由此，能够缓和有源部120的端部处的电场集中。
如图2所示，通过在接触开口56的端部30的下方设置覆盖阴极区24的端部埋入区22-e，从而能够抑制从端部30的下方的阴极区24注入电子。虽然存在于边缘终端结构部90的漂移区18等的载流子容易集中在接触开口56的端部30，但是通过抑制从端部30的下方注入电子，能够缓和载流子向端部30集中。
应予说明，在Y轴方向上，设置于层间绝缘膜26的下方的端部埋入区22-e的长度Ye1短于设置于接触开口56的下方的端部埋入区22-e的长度Ye2。也就是说，端部埋入区22-e以端部30为基准，向Y轴方向上的有源部120侧突出的部分比向Y轴方向上的边缘终端结构部90侧突出的部分长。由此，在有源部120中未被埋入区22覆盖而露出的阴极区24的部分37距接触开口56的端部30的距离比在边缘终端结构部90中未被埋入区22覆盖而露出的阴极区24的部分35距接触开口56的端部30的距离大。
在向半导体装置100流通正向电压的情况下，未被埋入区22覆盖而露出的阴极区24的部分中的、面对阳电极12的部分37更容易注入电子。通过将部分37相比于部分35更远离接触开口56的端部30而配置，从而能够缓和针对端部30的载流子集中。另外，通过减小端部埋入区22-e的边缘终端结构部90中的长度Ye1，从而容易减小半导体装置100的Y轴方向上的尺寸。
端部埋入区22-e的有源部120中的长度Ye2可以是边缘终端结构部90中的长度Ye1的2倍以上，也可以是5倍以上，还可以是10倍以上，甚至可以是40倍以上。长度Ye2可以是长度Ye1的100倍以下，也可以是50倍以下，还可以是10倍以下。另外，长度Ye2可以是半导体基板10的Z轴方向上的厚度Zs以上。长度Ye2可以是厚度Zs的2倍以上，也可以是5倍以上。
另外，设置于层间绝缘膜26的下方的端部埋入区22-e的Y轴方向上的长度Ye1可以是20μm以上。通过使长度Ye1为预定以上，能够使阴极区24的部分35与接触开口56的端部30分离。由此，能够更加缓和载流子向端部30集中。长度Ye1可以是30μm以上，也可以是40μm以上。通过增大长度Ye1，在形成形成埋入区22时所使用的掩模的光刻工序中产生制造偏差的情况下，也能够抑制对特性造成的影响。
另外，设置于层间绝缘膜26的下方的端部埋入区22-e的Y轴方向上的长度Ye1可以大于埋入区22的Y轴方向上的狭缝宽度Ys。由此，能够将阴极区24的部分35远离端部30地配置。长度Ye1可以是狭缝宽度Ys的1.5倍以上，也可以是2倍以上，还可以是3倍以上。
在将设置于层间绝缘膜26的下方的阳极区16的Y轴方向上的长度设为Ya的情况下，长度Ye1可以短于长度Ya。也就是说，在边缘终端结构部90中，端部埋入区22-e设置在与阳极区16重叠的范围内。长度Ye1可以为长度Ya的20％以上，也可以是30％以上，还可以是40％以上。长度Ye1可以是长度Ya的60％以下，也可以是50％以下。
在将设置于层间绝缘膜26的下方的阴极区24的Y轴方向上的长度设为Yk的情况下，长度Ye1可以短于长度Yk。也就是说，在边缘终端结构部90中，端部埋入区22-e设置在与阴极区24重叠的范围内。由此，即使产生制造偏差等，也防止端部埋入区22-e与阴电极14接触。
长度Ye1可以为长度Yk的20％以上，也可以为30％以上，还可以为40％以上。长度Ye1可以为长度Yk的80％以下，也可以为70％以下。另外，长度Ye1可以比长度Yk短10μm以上。长度Ye1可以比长度Yk短15μm以上，也可以比长度Yk短20μm以上。
另外，在层间绝缘膜26的下方，阴极区24的长度Yk可以短于阳极区16的长度Ya。也就是说，在边缘终端结构部90中，阴极区24设置在与阳极区16重叠的范围内。长度Yk可以为长度Ya的一半以上，也可以为长度Ya的60％以上。长度Yk可以为长度Ya的80％以下，也可以为长度Ya的70％以下。通过将阴极区24的端部27配置在比阳极区16的端部15更靠近接触开口56的端部30侧，能够缓和向阳极区16的端部15集中载流子。
另外，Y轴方向上的阴极区24的端部27与阳极区16的端部15之间的距离(Ya-Yk)可以大于阳极区16的Z轴方向上的厚度Za。由此，能够抑制从阴极区24注入的载流子到达阳极区16的端部15，并且缓和端部15处的载流子集中。距离(Ya-Yk)可以为厚度Za的1.2倍以上，也可以为1.5倍以上，还可以为2倍以上。应予说明，阳极区16的厚度Za可以使用接触开口56的端部30的正下方处的阳极区16的厚度。
另外，Y轴方向上的阴极区24的端部27与阳极区16的端部15之间的距离(Ya-Yk)可以大于层间绝缘膜26的Z轴方向上的厚度Zi。距离(Ya-Yk)可以为厚度Zi的1.2倍以上，也可以为1.5倍以上，还可以为2倍以上。应予说明，层间绝缘膜26的厚度Zi可以使用阳极区16的端部15的正上方处的层间绝缘膜26的厚度。
图3是放大阳极区16的端部15附近而得的截面图。阳极区16在YZ截面中，在端部15具有弯曲部17。弯曲部17是使阳极区16与漂移区18之间的边界在YZ截面中向下凸出地弯曲而得的区域。
在本例中，阴极区24不设置在弯曲部17的下方。也就是说，阴极区24设置在阳极区16中的YZ截面中的下端成为与半导体基板10的上表面11平行的直线的区域的下方。通过这样的结构，能够抑制从阴极区24注入的载流子到达弯曲部17，并且能够缓和弯曲部17处的载流子集中。
图4是表示半导体装置100的另一例的YZ截面的图。本例的半导体装置100除了图1至图3中说明的半导体装置100的结构以外，还具有寿命控制部40。寿命控制部40是通过将氦等局部地注入到半导体基板10的预定的区域，从而使晶体缺陷的密度高于其他区域的区域。通过设置寿命控制部40，能够促进因晶体缺陷而引起的载流子的复合，并且能够调整载流子的寿命。
本例的寿命控制部40在Z轴方向上设置在缓冲区20的内部，并且在XY面内设置在有源部120的内部。寿命控制部40也可以在XY面内还设置在边缘终端结构部90的至少一部分。
图5是表示图4中的B-B截面的掺杂浓度分布例的图。在图5中，除了掺杂浓度以外，还示出了寿命控制部40中的晶体缺陷的浓度的峰。本例的缓冲区20的Z轴方向上的掺杂浓度分布具有多个峰42。寿命控制部40中的晶体缺陷的浓度的峰优选被配置为，在Z轴方向上，不与缓冲区20中的任一峰值42重叠。由此，能够抑制寿命控制部40中的晶体缺陷因注入到缓冲区20的质子等而过度恢复。
应予说明，浓度的峰不重叠是指，峰间的距离X为预定值以上。作为一例，距离X可以为寿命控制部40的晶体缺陷浓度分布的半值半宽Y/2以上，也可以为半值全宽Y以上，还可以为半值全宽Y的2倍以上。
同样地，寿命控制部40的浓度峰优选不与埋入区22的掺杂浓度的峰重叠。由此，利用寿命控制部40，能够抑制埋入区22中的载流子消失。
图6是表示比较例的半导体装置200的结构例的图。在半导体装置200中，阴极区24和埋入区22设置在接触开口56的下方，未设置在接触开口56的端部30和层间绝缘膜26的下方。在这样的结构的情况下，有载流子集中于接触开口56的端部30的情况。另外，端部埋入区22-e的端部23和阴极区24的端部27设置在大致相同的位置，端部埋入区22-e与阴电极14容易电连接。如果端部埋入区22-e与阴电极14处于短路状态，则妨碍从阴极区24注入电子，并且如果施加高的正向电压，则不会流通正向电流。
图7是表示半导体装置100和半导体装置200的正向电压-正向电流特性的一例的图。在图7中，以实线来表示半导体装置100的特性，并以虚线来表示半导体装置200的特性。
如图7所示，半导体装置100的特性与半导体装置200的特性相比，电流在较低的电压下上升。即，通过将端部埋入区22-e的端部23配置在比阴极区24的端部27更靠有源部120侧，从而能够增大端部埋入区22-e与阴电极14之间的电阻，并且能够有效地从阴极区24注入电子。
以上，利用实施方式对本发明进行说明，但本发明的技术范围不限于上述实施方式所记载的范围。本领域技术人员可知，能够对上述实施方式追加多种变更或改良。从权利要求的记载可知，追加了这样的变更或改良的方式也能够包含在本发明的技术范围内。

Claims (12)

1.一种半导体装置，其特征在于，具备设置有第一导电型的漂移区的半导体基板，所述半导体装置具备：
第二导电型的阳极区，其设置在所述半导体基板的上表面与所述漂移区之间；
第一导电型的阴极区，其设置在所述半导体基板的下表面与所述漂移区之间，并且掺杂浓度高于所述漂移区的掺杂浓度；
第二导电型的埋入区，其设置于所述阴极区的上方；
层间绝缘膜，其配置于所述半导体基板的上表面的上方，并且设置有使所述阳极区的一部分露出的接触开口；以及
上表面侧电极，其在所述接触开口中与所述阳极区接触，
所述埋入区包含端部埋入区，所述端部埋入区在与所述半导体基板的上表面垂直的截面中，从所述接触开口的下方的区域起，通过所述接触开口的端部的下方，而连续地设置到所述层间绝缘膜的下方的区域，
在与所述半导体基板的上表面平行的第1方向上，设置于所述层间绝缘膜的下方的所述端部埋入区比设置于所述接触开口的下方的所述端部埋入区短。
2.如权利要求1所述的半导体装置，其特征在于，
设置于所述层间绝缘膜的下方的所述端部埋入区在所述第1方向上的长度为20μm以上。
3.如权利要求1或2所述的半导体装置，其特征在于，
所述埋入区以预先设定的狭缝宽度的间隔在第1方向上分离地设置，
设置于所述层间绝缘膜的下方的所述端部埋入区在所述第1方向上的长度大于所述狭缝宽度。
4.如权利要求1至3中任一项所述的半导体装置，其特征在于，
在与所述半导体基板的上表面垂直的截面中，所述阳极区从所述接触开口的下方的区域起，通过所述接触开口的端部的下方，而设置到所述层间绝缘膜的下方的区域，
在所述第1方向上，设置于所述层间绝缘膜的下方的所述端部埋入区比设置于所述层间绝缘膜的下方的所述阳极区短。
5.如权利要求1至4中任一项所述的半导体装置，其特征在于，
在与所述半导体基板的上表面垂直的截面中，所述阴极区从所述接触开口的下方的区域起，通过所述接触开口的端部的下方，而设置到所述层间绝缘膜的下方的区域，
在所述第1方向上，设置于所述层间绝缘膜的下方的所述端部埋入区比设置于所述层间绝缘膜的下方的所述阴极区短。
6.如权利要求5所述的半导体装置，其特征在于，
在所述第1方向上，设置于所述层间绝缘膜的下方的所述端部埋入区比设置于所述层间绝缘膜的下方的所述阴极区短10μm以上。
7.如权利要求1至6中任一项所述的半导体装置，其特征在于，
在与所述半导体基板的上表面垂直的截面中，所述阳极区和所述阴极区从所述接触开口的下方的区域起，通过所述接触开口的端部的下方，而设置到所述层间绝缘膜的下方的区域，
在所述第1方向上，设置于所述层间绝缘膜的下方的所述阴极区比设置于所述层间绝缘膜的下方的所述阳极区短。
8.如权利要求7所述的半导体装置，其特征在于，
在所述第1方向上，设置于所述层间绝缘膜的下方的所述阴极区的长度为设置于所述层间绝缘膜的下方的所述阳极区的长度的一半以上。
9.如权利要求7或8所述的半导体装置，其特征在于，
所述第1方向上的所述阴极区的端部与所述阳极区的端部之间的距离大于所述阳极区的垂直于所述半导体基板的上表面的第2方向上的厚度。
10.如权利要求7至9中任一项所述的半导体装置，其特征在于，
所述第1方向上的所述阴极区的端部与所述阳极区的端部之间的距离大于所述层间绝缘膜的垂直于所述半导体基板的上表面的第2方向上的厚度。
11.如权利要求7或8所述的半导体装置，其特征在于，
在垂直于所述半导体基板的上表面的截面中，所述阳极区在端部具有弯曲部，
所述阴极区未设置在所述弯曲部的下方。
12.如权利要求1至11中任一项所述的半导体装置，其特征在于，
在所述第1方向上，设置于所述接触开口的下方的所述端部埋入区的长度为所述半导体基板的厚度以上。
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