CN111052378A - 形成包括包含氧化物半导体的薄膜晶体管的半导体结构的方法 - Google Patents

形成包括包含氧化物半导体的薄膜晶体管的半导体结构的方法 Download PDF

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CN111052378A
CN111052378A CN201880056034.9A CN201880056034A CN111052378A CN 111052378 A CN111052378 A CN 111052378A CN 201880056034 A CN201880056034 A CN 201880056034A CN 111052378 A CN111052378 A CN 111052378A
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凯文·J·特雷克
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Micron Technology Inc
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Micron Technology Inc
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Abstract

一种形成半导体结构的方法包括形成竖直薄膜晶体管阵列。形成所述竖直薄膜晶体管阵列包括：形成源极区域；在所述源极区域上方形成包括氧化物半导体材料的沟道材料；将所述沟道材料暴露于包括溴化氢的干蚀刻剂中以将所述沟道材料图案化为相邻的竖直薄膜晶体管结构的沟道区域；在所述沟道区域的侧壁上形成栅极介电材料；形成与所述栅极介电材料相邻的栅极电极材料；以及在所述沟道区域上方形成漏极区域。还揭示了形成半导体结构和存储器单元阵列的相关方法。

Description

形成包括包含氧化物半导体的薄膜晶体管的半导体结构的 方法
优先权要求
本申请要求于2018年8月28日提交的标题为“形成包括包含氧化物半导体的薄膜晶体管的半导体结构的方法”的美国专利申请序列号16/114,614的申请日的权益，其要求于2017年8月30日提交的标题为“形成包括包含氧化物半导体的薄膜晶体管的半导体结构的方法”的美国临时专利申请第62/522,159号的权益。
技术领域
本文中所揭示的实施例涉及形成包含包括氧化物半导体的竖直薄膜晶体管的半导体结构的方法以及相关半导体结构。更具体地，本公开的实施例涉及形成半导体结构的方法，所述半导体结构包括具有沟道区域的竖直薄膜晶体管阵列，所述沟道区域在一些实施例中可以包括氧化物；图案化竖直薄膜晶体管的方法以及相关半导体结构。
背景技术
常规易失性存储器单元(例如，动态随机存取存储器(DRAM)单元)可以包含存储元件和晶体管。存储元件可以例如包含电容器(例如，有时被称为“单元电容器”或“存储电容器”)，其被配置成存储由电容器中的存储电荷定义的逻辑状态(例如，“0”或“1”的二进制值)。所述晶体管在本领域中可以被称成“存取晶体管”。所述晶体管通常包含在一对源极/漏极区域之间的沟道区域，并且进一步包含被配置成通过沟道区域将源极/漏极区域彼此电连接的栅极。沟道区域通常包含半导体材料，例如硅。
为了对电容器充电、放电、读取或再充电，可以将晶体管选择性地转换到“接通”状态，其中电流穿过晶体管的沟道区域在源极和漏极区域之间流动。晶体管可以选择性地转换到“截止”状态，其中电流基本上停止流动。在截止状态下，期望电容器保持电荷不变。然而，常规易失性存储器单元的电容器可能随着时间的推移表现出电流放电，从而导致所存储的电荷的损失。因此，即使在存储器单元未被选择时处于“截止”状态，电流也可能从电容器流出。所述截止状态泄露电流在本领域中被称为亚阈值泄露电流。
由于亚阈值泄露电流，常规易失性存储器单元经常被刷新。亚阈值泄露电流还可能影响存储器装置内的存储器单元阵列的制造和配置。在设计、制造和使用易失性存储器单元以及合并存储器装置中的单元阵列时，存储器单元的亚阈值泄露电流速率、刷新速率、单元大小和热预算通常是重要的考虑因素。
形成沟道区域的方法通常包含利用例如草酸的湿蚀刻剂蚀刻此结构的沟道区域。然而，使用此蚀刻剂通常在此结构上形成残余物。由此蚀刻剂留下的残留物会改变沟道区域的材料特性。另外，湿蚀刻剂通常无法实现所图案化的结构的理想的高填充密度。
发明内容
本文中所揭示的实施例涉及形成包含包括氧化物半导体的竖直薄膜晶体管的半导体装置的方法以及相关半导体装置。例如，根据一些实施例，形成半导体结构的方法包括形成竖直薄膜晶体管阵列。形成薄膜晶体管阵列包括：形成源极区域：在源极区域上方形成包括氧化物半导体材料的沟道材料：将沟道材料暴露于包括溴化氢的干蚀刻剂以将沟道材料图案化为相邻的竖直薄膜晶体管结构的沟道区域：在沟道区域的侧壁上形成栅极介电材料：形成与栅极介电材料相邻的栅极电极材料，以及在沟道区域上方形成漏极区域。
在另外的实施例中，形成半导体结构的方法包括：形成导电源极区域：在导电源极区域上方图案化包括氧化物半导体材料的沟道材料以形成在第一方向上延伸的沟道材料的行，其中图案化沟道材料包括将沟道材料暴露于包括含溴化氢的气体的干蚀刻剂；在沟道材料的行的侧壁上形成栅极氧化物；形成与栅极氧化物相邻的栅极电极，以及图案化沟道材料的行以形成包括竖直薄膜晶体管的隔离的沟道区域。
在另外的实施例中，形成存储器单元阵列的方法包括形成竖直薄膜晶体管阵列。形成竖直薄膜晶体管阵列包括：在导电源极材料上方将包括氧化物半导体材料的沟道材料暴露于包括溴化氢的干蚀刻剂以形成沟道材料的行：在沟道材料的行的侧壁上形成栅极氧化物；形成与栅极氧化物相邻的栅极电极；将沟道材料的行暴露于干蚀刻剂以形成隔离的竖直薄膜晶体管结构，以及在隔离的竖直薄膜晶体管中的每一者的沟道材料上方形成漏极区域。所述方法进一步包括在隔离的竖直薄膜晶体管中的每一者的漏极区域上方形成与其接触的电容器结构。
附图说明
图1A是根据本公开的一些实施例的半导体结构的简化横截面图；
图2A是根据本公开的一些实施例的竖直薄膜晶体管阵列的简化横截面图；
图2B是沿图2A的剖面线B-B截取的图2A的竖直薄膜晶体管阵列的简化横截面图；以及
图3A至图3K示出了根据本公开的一些实施例形成竖直薄膜晶体管阵列的方法。
具体实施方式
本文中所包含的图示并不意味着是任何特定系统或半导体结构的实际视图，而仅仅是用于描述本文中的实施例的理想化表示。在图之间共同的元件和特征可以保持相同的数字标号，但是为了便于以下描述，在大多数情况下，附图标记从引入或最充分描述元件的附图编号开始。
以下描述提供特定细节，例如材料类型、材料厚度和处理条件，以便提供本文中所述的实施例的全面描述。然而，本领域的普通技术人员将了解，可以在不使用这些特定细节的情况下实践本文中所揭示的实施例。实际上，可以结合半导体工业中所采用的常规制造技术来实践所述的实施例。另外，本文中所提供的描述并不形成包含包括氧化物半导体的竖直薄膜晶体管的半导体结构的完整描述，或者用于制造此半导体结构的工艺流程的完整描述。以下所述的结构没有形成完整的竖直薄膜晶体管或半导体结构。以下仅详细描述理解本文中所述的实施例所必需的那些过程动作和结构。可以通过常规技术执行形成包含本文中所述的氧化物半导体的完整半导体结构或竖直薄膜晶体管的附加动作。
根据本文中所揭示的实施例，半导体结构包含存储器单元阵列和竖直薄膜晶体管。竖直薄膜晶体管可以包含在源极区域和漏极区域之间形成的沟道区域。在一些实施例中，沟道区域可以包含氧化物半导体材料。包含氧化物半导体材料的此沟道区域可以表现出减少的截止状态泄露量，并且可以表现出比常规材料更低的截止状态电流。可以通过利用干蚀刻剂(例如反应离子蚀刻(RIE)中使用的)蚀刻沟道区域的材料来形成竖直薄膜晶体管。干蚀刻剂可以包含溴化氢和载气。在一些实施例中，干蚀刻剂进一步包含烷烃(例如，甲烷)、氢气、三氟化氮和氧气中的一或多种。此干蚀刻剂促进了包括氧化物半导体材料的竖直薄膜晶体管的形成，所述氧化物半导体材料的填充密度大于用其它蚀刻方法可获得的填充密度。例如，可以形成薄膜晶体管阵列，其在第一方向上的间距在约10nm至约40nm之间，在基本上垂直于第一方向的第二方向上的间距在约20nm至约50nm之间。因此，根据本公开的实施例形成的竖直薄膜晶体管可以用于超大规模集成或高密度存储器电路中。竖直薄膜晶体管的沟道区域可以具有基本上垂直的侧壁(即，相对于半导体结构的主表面以约90°角定向的侧壁)。根据此方法形成的竖直薄膜晶体管可以基本上不存在蚀刻沟道区域期间形成的任何残留材料，并且沟道区域材料的材料特性可以基本上不受用于蚀刻此材料的蚀刻剂的影响。蚀刻沟道材料的方法促进形成沟道区域的平滑线和清洁表面，并且促进形成具有窄间距和间隔的竖直薄膜晶体管阵列。
图1是根据本公开的一些实施例的半导体装置100的简化横截面图。半导体装置100可以包含逻辑电路区域102、通过例如导电互连件106连接到逻辑电路区域102的晶体管区域104、与晶体管区域104连通的电容器区域108以及在电容器区域108上方的互连区域110。电容器区域108可以包含与存储器单元相关联的存储电容器，并且可以被配置成存储与其相关联的存储器单元的逻辑值。互连区域110可以包含互连电路，其用于将半导体结构及其组件电耦合到半导体装置100的一或多个其它组件。互连区域110可以包含一或多种导电材料。
逻辑电路区域102可以形成在衬底101上或在衬底101中。衬底101可以是基底材料或在其上形成附加材料的构造。衬底101可以是半导体衬底、支撑结构上的基底半导体层、金属电极或其上形成有一或多个层、结构或区域的半导体衬底。衬底101可以是常规硅衬底或包括半导体材料层的其它体衬底。如本文中所使用，术语“体衬底”不仅意味且包含着硅晶片，而且还意味且包含着绝缘体上硅(“SOI”)衬底(例如蓝宝石上硅(“SOS”)衬底及玻璃上硅(“SOG”)衬底)、基底半导体基础上的硅外延层以及其它半导体或光电子材料，例如硅锗、锗、砷化镓、氮化镓和磷化铟。衬底102可以是掺杂的或未掺杂的。
逻辑电路区域102可以包含衬底层的互补金属氧化物半导体(CMOS)电路。作为非限制性实例，平面晶体管结构112(例如，NMOS晶体管结构、PMOS晶体管结构等)布置在衬底101上。平面晶体管结构112可以包含在源极/漏极区域116之间延伸的一或多个栅极介电材料114。栅极电极材料118可以覆盖在栅极介电材料114，并且可以被配置成与半导体装置100的一或多个组件电连通。栅极电极材料118可以包含导电材料，例如氮化钛(TiN)、铜、钨、氮化钨(WN)、钼、多晶硅、其它导电材料或其组合。罩盖材料120可以覆盖栅极电极材料118。罩盖材料120可以包含绝缘材料，例如二氧化硅、氮化硅或其组合。侧壁间隔物122可以在平面晶体管结构112的侧壁上。侧壁间隔物122可以包含绝缘材料，例如二氧化硅、氮化硅或其组合。
导电互连件124可以将至少一些平面晶体管结构112的源极/漏极区域116中的一者电耦合到导电互连件106，导电互连件106又可以耦合到晶体管区域104。导电互连件124可以通过例如导电线126与导电互连件106电连通。
电容器区域108可以包含电容器结构130，每个电容器结构130包含与晶体管区域104接触的第一电极132、与第一电极132接触的介电材料134以及与介电材料134接触的第二电极136。因此，介电材料134可以设置在第一电极132和第二电极136之间。第二电极136可以通过一或多个导电互连件(例如，导电互连件138)与互连区域110电连通。
第一电极132和第二电极136可以包含导电材料，例如金属、金属合金、导电金属氧化物、导电金属氮化物、导电金属硅化物、导电掺杂的半导体材料或其组合。第一电极132和第二电极136可以独立地包括例如W、WN、Ni、Ta、TaN、TaSi、Pt、Cu、Ag、Au、Al、Mo、Ti、TiN、TiSi、TiSiN、TiAlN、MoN、Ir、IrOx、Ru、RuOx以及导电掺杂的硅中的至少一者。
介电材料134可以包含用于保持电容器电荷的合适的介电材料。在一些实施例中，介电材料134包括铁电材料，例如铁电氧化铪、铁电氧化锆、锆钛酸铅(PZT)、钛酸锶钡、高k介电材料或其组合。在一些实施例中，介电材料134可以包含掺杂剂，例如硅、铝、镧、钇、铒、钙、镁、锶、稀土元素或其组合中的一或多种。介电材料134可以被配置成存储与和电容器结构130相关联的存储器单元的逻辑状态相关联的电荷或其它特性。因此，电容器结构130可以被称为“单元电容器”或“存储电容器”。
尽管图1示出了包括沟槽电容器的电容器结构130，但是本公开不限于此。在其它实施例中，电容器结构130可以包括除沟槽电容器以外的电容器。作为非限制性实例，电容器结构130可以包括堆叠的电容器。
导电互连件138可以将电容器结构130电连接到互连区域110。互连区域110可以包含导电接触170、174、178和导电线172、176，其用于将电容器结构130电连接到外部电路或半导体结构100的其它组件。导电接触170、174、178和导电线172、176可以包含导电材料，例如氮化钛、铜、钨、氮化钨、钼、多晶硅、其它导电材料或其组合。
参考图1和图2A，晶体管区域104可以包含竖直薄膜晶体管140，其细节在图2A中示出。竖直薄膜晶体管140可以布置在阵列200中。每个竖直薄膜晶体管140可以包含与导电互连件106电连通的源极区域(例如，源极线)142，用于在竖直薄膜晶体管140和逻辑电路区域102之间形成电连接。
源极区域142可以包含金属、金属的组合或不同金属的区域。例如但不限于，源极区域142可以包含氮化钛、铜、钨、氮化钨、钼、多晶硅、其它导电材料或其组合。在一些实施例中，源极区域142包括钨。
沟道材料144可以覆盖源极区域142并且与其直接接触。沟道材料144可以包含氧化物半导体材料。作为非限制性实例，氧化物半导体材料可以包含铟镓锌氧化物、非晶氧化物半导体材料、ZnOx、InOx、In2O3、SnO2、TiOx、ZnxOyNz、InxZnyOz、InxGayZnzOa、ZrxInyZnzOa、HfxInyZnzOa、SnxInyZnzOa、AlxSnyInzZnaOd、SixInyZnzOa、ZnxSnyOz、AlxZnySnzOa、GaxZnySnzOa、ZrxZnySnzOa、InGaSiO及其组合，其中x、y、z、a和d中的每一者独立地为约1至约10之间的实数。换句话说，x、y、z、a和d中的每一者可以等于约1至约10之间的任何值，并且可以与x、y、z、a和d中的另一者不同。
在一些实施例中，沟道材料144包括铟镓锌氧化物。铟镓锌氧化物可以包含铟(In)、镓(Ga)、锌(Zn)和氧(O)的任何组合物。例如，在没有限制的情况下，铟镓锌氧化物可以具有1:1:1:4的In:Ga:Zn:O的比率，可以具有2:2:1的In2O3:Ga2O3:ZnO的比率，或者可以由分子式InGaO3(ZnO)5表示。在一些实施例中，基于半导体材料114的其它金属原子，铟可以占半导体材料114的约20原子百分比至约60原子百分比，例如约20原子百分比至约40原子百分比。基于半导体材料114的其它金属原子(即，不包含氧原子)，镓可以占半导体材料114的约20原子百分比至约60原子百分比，例如约35原子百分比至约55原子百分比。基于半导体材料114的其它金属原子，锌可以占半导体材料114的约20原子百分比至约60原子百分比，例如约20原子百分比至约40原子百分比。在沟道材料144包括铟镓锌氧化物的实施例中，沟道材料144可以表现出“接通”状态电流与“截止”状态泄露电流的高比率。例如，沟道材料144可以表现出仅约1×10-24A的截止状态泄露电流以及约1,000,000,000至1的接通至截止电流比率。低截止状态泄露电流可以有助于使用存储器单元中的沟道材料144，其不需要每小时刷新约一次以上(例如，每十小时一次、每二十四小时一次等)。
漏极区域(例如，漏极线)146可以覆盖并且直接接触沟道材料144。漏极区域146可以包含任何适当的导电材料，所述导电材料被设计和配置成便于电流穿过沟道材料144在漏极区域146和源极区域142之间流动。漏极区域146可以包含金属、金属的组合或不同金属的区域。例如但不限于，漏极区域146可以包含氮化钛、铜、钨、氮化钨、钼、多晶硅、其它导电材料或其组合。在一些实施例中，漏极区域146包括与源极区域142相同的材料。在一些实施例中，漏极区域146包括钨。
漏极区域146可以与电容器区域108的电容器结构130的第一电极132电连通。因此，竖直薄膜晶体管140可以被配置成提供对存储电容器结构130的存储器材料(例如，介电材料134)的存取。
栅极介电材料148(图2A)可以在沟道材料144的侧壁上。栅极电极150(图2A)可以在栅极介电材料148的侧壁上，并且可以与栅极介电材料148相邻。栅极介电材料148可以包含栅极绝缘体材料，例如氧化物(例如，二氧化硅(SiO2))。在其它实施例中，栅极介电材料148可以包含磷硅酸盐玻璃、硼硅酸盐玻璃、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃、二氧化钛、二氧化锆、二氧化铪、氧化钽、氧化镁、氧化铝或其组合、氮化物材料(例如，氮化硅(Si3N4))、氮氧化物(例如，氮氧化硅)或其组合。
栅极电极150可以包含导电材料，例如金属、金属合金、导电金属氧化物、导电金属氮化物、导电金属硅化物、导电掺杂的半导体材料或其组合。作为非限制性实例，栅极电极150可以包含多晶硅、导电掺杂的硅、钨、氮化钨、镍、钽、氮化钽、硅化钽、铂、铜、银、金、铝、钼、钛、氮化钛、硅化钛、氮化钛铝、氮化钼、铱、氧化铱、钌、氧化钌及其组合。在一些实施例中，栅极电极包括氮化钛。
栅极电极150可以与导电线(例如，导电字线160)电连通。导电字线160可以按行延伸并且将竖直存取晶体管的行的每个竖直存取晶体管140彼此电连接。
导电字线160可以包含导电材料，例如多晶硅、导电掺杂的硅、钨、氮化钨、镍、钽、氮化钽、硅化钽、铂、铜、银、金、铝、钼、钛、氮化钛、硅化钛、氮化钛铝、氮化钼、铱、氧化铱、钌、氧化钌及其组合。在一些实施例中，导电字线160包含氮化钛。
在使用和操作中，可以通过与竖直存取晶体管140相关联的行(经由导电字线160)施加电压，并且施加与竖直存取晶体管140的列(例如，经由与例如源极区域142相关联的源极线)相关联的电压，来存取个别竖直存取晶体管140。为了存取特定竖直存取晶体管140，可以将电压(和电流)提供到与竖直存取晶体管140相关联的栅极电极150。响应于足够的电压(例如，幅度大于阈值电压的电压)，电流可以通过竖直薄膜晶体管140在源极区域142和漏极区域146之间的沟道区域144中流动。因此，可以通过响应于栅极电极150暴露于阈值电压的竖直薄膜晶体管140访问电容器区域108中的存储器材料。
相邻的竖直薄膜晶体管140之间的间距P可以在约10nm至约40nm之间，例如在约10nm至约15nm之间、在约15nm至约20nm之间、在约20nm至约25nm之间、在约25nm至约30nm之间，或者在约30nm至约40nm之间。间距P可以定义为从竖直薄膜晶体管140的一个特征到相邻的竖直薄膜晶体管140的类似特征的距离。在一些实施例中，间距P约等于24nm。
沟道区域144的高度H可以在约40nm至约100nm之间，例如在约40nm至约60nm之间、在约60nm至约80nm之间或在约80nm至约100nm之间。在一些实施例中，高度H约等于80nm。
图2B是通过图2A的剖面线B-B截取的竖直薄膜晶体管140的横截面图。相邻的竖直薄膜晶体管140可以通过绝缘材料154彼此隔离。绝缘材料154可以包括介电材料，例如二氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、硼磷硅酸盐玻璃、氟硅酸盐玻璃、二氧化钛、二氧化锆、二氧化铪、氧化钽、氧化镁、氧化铝、氮化硅、氮氧化硅、无定形碳或其组合。在一些实施例中，绝缘材料154包括二氧化硅。
竖直薄膜晶体管140的宽度W可以在约5nm至约40nm之间，例如在约5nm至约10nm之间、在约10nm至约15nm之间、在约15nm至约20nm之间、在约20nm至约30nm之间或在约30nm至约40nm之间。在一些实施例中，宽度W可以约等于12nm。在其它实施例中，宽度W可以约等于26nm。
图2B的横截面中的相邻的竖直薄膜晶体管140之间的距离D可以在约20nm至约100nm之间，例如在约20nm至约30nm之间、在约30nm至约40nm之间、在约40nm至约50nm之间、在约50nm至约75nm之间或在约75nm至约100nm之间。在一些实施例中，距离D可以约等于36nm。在其它实施例中，距离D可以在约70nm至约80nm之间，例如约73nm。
在一些实施例中，沟道材料144的侧壁152可以相对于衬底101(图1)的主表面以约90°角定向。换句话说，侧壁152可以基本上垂直于衬底101的主表面定向，并且可以不表现出显著的倾斜。在一些实施例中，侧壁152相对于衬底101的主表面的角度可以大于约88°、大于约89°或可以基本上与其垂直。所述角度可以在约80°至约90°之间，例如在约80°至约85°之间或在约85°至约90°之间。所述角度可以在约88°至约89°之间或在约89°至约90°之间。在一些实施例中，所述角度大于约82.8°。
如将参考图3A至图3K所述，竖直薄膜晶体管140可以形成在具有比常规半导体装置更大的填充密度(例如，每单位面积的竖直薄膜晶体管140的数量)的阵列中，并且可以通过使用包括溴化氢的干蚀刻工艺形成沟道材料144来实现侧壁152和衬底101的主表面之间的角度。
图3A至图3K示出了形成竖直薄膜晶体管140(图2A、图2B)的方法。参考图3A，可以在衬底302上方形成源极材料304。衬底302可以包含例如上文参考图1所述的逻辑电路区域102的组件。作为非限制性实例，衬底302可以包含导电互连件106(图1)，其可以被设置和配置成与源极材料304接触。
源极材料304可以包含上文参考源极区域142(图2A、图2B)所述的任何材料。作为非限制性实例，源极材料304可以包含金属、金属的组合或不同金属的区域。例如但不限于，源极材料304可以包含氮化钛、铜、钨、氮化钨、钼、多晶硅、其它导电材料或其组合。
参考图3B，可以图案化源极材料304以形成源极材料304(图3A)的源极区域(例如，源极线)306。源极区域306可以布置在例如衬底302上方在第一方向上(例如，y方向，其垂直于x方向，并且在图3B所示的横截面中的进入和离开页面)延伸的行中。可以通过例如在源极材料304上方形成掩模(图3A)、在掩模中形成图案(例如，通过光刻)以及通过掩模去除源极材料304的部分来图案化源极区域306。在形成源极材料的源极区域306之后，可以在源极区域306上方以及在源极区域306之间的区域中形成介电材料308。可以例如通过化学机械抛光(CMP)从源极区域306上方的部分去除介电材料308。介电材料308可以包含二氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、硼磷硅酸盐玻璃、氟硅酸盐玻璃、二氧化钛、二氧化锆、二氧化铪、氧化钽、氧化镁、氧化铝、氮化硅、氮氧化硅、无定形碳或其组合。
参考图3C，可以在介电材料308和源极区域306上方形成沟道材料310。沟道材料310可以包含上文参考图2A的沟道材料144所述的相同材料。可以通过例如原子层沉积(ALD)、化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、等离子体增强化学气相沉积(PECVD)、物理气相沉积(PVD)、脉冲激光沉积(PLD)、另一种沉积工艺或其组合来形成沟道材料310。
参考图3D，可以图案化沟道材料310以在源极区域306上方形成沟道材料310的隔离线。在一些实施例中，可以图案化沟道材料310以在源极区域306上方直接形成与其接触的沟道区域312。可以图案化沟道区域312，使得沟道区域312的相邻的部分彼此分开的距离在约10nm至约40nm之间，例如在约10nm至约15nm之间、在约15nm至约20nm之间、在约20nm至约25nm之间、在约25nm至约30nm之间或在约30nm至约40nm之间。在一些实施例中，沟道区域512的相邻的部分可以彼此分开约24nm的距离。
可以通过干蚀刻沟道材料310以去除沟道材料310的部分并形成具有期望的间距、宽度和间隔的沟道区域312来图案化沟道材料310。在一些实施例中，在沟道材料310上方以期望的图案形成包括例如碳材料(例如，无定形碳)的掩模。可以通过掩模用各向异性蚀刻(例如，各向异性干蚀刻)去除沟道材料310的部分。作为非限制性实例，可以通过反应离子蚀刻(RIE)、等离子体蚀刻、另一种干蚀刻方法等图案化沟道区域312。
合适的蚀刻剂气体可以包含溴化氢(HBr)、一或多种烷烃或烯烃(例如，CH4、C2H6等)、基于卤素的蚀刻剂、Cl2、CF4和CH2O2、四氟甲烷(CF4)、八氟丙烷(C3F8)、八氟环丁烷(C4F8)、六氟丁二烯(C4F6)、八氟环戊烯(C5F8)、三氟甲烷(CHF3)、二氟甲烷(CH2F2)、六氟化硫(SF6)、三氟化氮(NF3)、三氟化氯(ClF3)、氯气(Cl2)、三氯化硼(BCl3)和三氟碘甲烷(CF3I)、CF4、C3F8、C4F8、C4F6、CHF3、CH2F2、SF6、NF3、ClF3、HBr、Cl2、BCl3以及CF3I。蚀刻剂气体可以进一步包含至少一种载体，例如氮气、氩气、氦气、氧气或其组合。
在一些实施例中，蚀刻剂气体包括含溴化氢的气体。含溴化氢的气体可以包含溴化氢、载气、以及甲烷(CH4)、氢气(H2)、氧气(O2)和三氟化氮中的一或多种。在一些实施例中，蚀刻剂气体包括溴化氢、氩气、甲烷和氢气。在一些此实施例中，蚀刻剂气体可以包括约每1.0份溴化氢的在约0.1份至约5.0份之间的甲烷，例如在约0.1份至约0.5份之间、在约0.5份至约1.0份之间、在约1.0份至约2.0份之间，或者约每1.0份溴化氢的在约2.0份至约5.0份之间的甲烷。在一些实施例中，蚀刻剂气体包括约每1.0份甲烷的约1.0份溴化氢。在其它实施例中，蚀刻剂气体包括约每2.0份甲烷的约1.0份溴化氢。在另外其它实施例中，蚀刻剂气体包括约每0.30份甲烷的约1.0份溴化氢。
蚀刻剂气体中可以包括约每1.0份溴化氢的在约0.1份至约5.0份之间的氢气，例如在约0.1份至约0.5份之间、在约0.5份至约1.0份之间、在约1.0份至约2.0份之间，或者约每1.0份溴化氢的在约2.0份至约5.0份之间的氢气。在一些实施例中，蚀刻剂气体包括约每1.0份溴化氢的约1.0份氢气。
对于，蚀刻剂气体可以包括约每1.0份溴化氢的在约0.1份至约5.0份之间的载气(例如，氩气)，例如在约0.1份至约0.5份之间、在约0.5份至约1.0份之间、在约1.0份至约2.0份之间，或者约每1.0份溴化氢的在约2.0份至约5.0份之间的载气。在一些实施例中，蚀刻剂气体中包括约每0.5份载气的约1.0份溴化氢。在其它实施例中，蚀刻剂气体中包括约每1.0份载气的约4.0份溴化氢，例如其中载气包括氦气。
蚀刻剂气体中可以包括约每1.0份氧气的在约0.1份至约10.0份之间的溴化氢，例如在约0.1份至约0.5份之间、在约0.5份至约1.0份之间、在约1.0份至约2.0份之间、约2.0份至约5.0份之间，或者约每1.0份氧气的在约5.0份至约10.0份之间的溴化氢。在一些实施例中，蚀刻剂气体中包括约每5.0份溴化氢的约1.0份氧气。
在一些实施例中，蚀刻剂气体包括溴化氢或基本上由其组成。在其它实施例中，蚀刻剂气体包括溴化氢和载气(例如，氮气、氩气、氦气、氧气或其组合)或基本上由其组成。在一些实施例中，蚀刻剂气体包括溴化氢和氩气或基本上由其组成。
在另外其它实施例中，蚀刻剂气体包括溴化氢、烷烃(例如，甲烷)和载气或基本上由其组成。在一些实施例中，蚀刻剂气体包括溴化氢、甲烷、氢气和氩气。在一些此实施例中，蚀刻剂气体可以包含约60:60:60:32的溴化氢:甲烷:氢气:氩气的比率。
在一些实施例中，蚀刻剂气体包括溴化氢、甲烷、氦气和氧气。在一些实施例中，蚀刻剂气体包括约50:100:12:10的溴化氢:甲烷:氦气:氧气的比率。
在其它实施例中，蚀刻剂气体包括溴化氢、氩气、氢气、甲烷和三氟化氮。在一些此实施例中，蚀刻剂气体包括约200:200:200:60:20的溴化氢:氩气:氢气:甲烷:三氟化氮的比率。
可以在图案化工艺期间施加偏置电压。在一些实施例中，偏置电压在约200V至约2,500V之间，例如在约200V至约400V之间、在约400V至约600V之间、在约600V至约800V之间、在约800V至约1,000V之间、在约1,000V至约1,250V之间、在约1,250V至约1,500V之间、在约1,500V至约2,000V之间或在约2,000V至约2,500V之间。在一些实施例中，偏置电压可以被脉冲。在一些实施例中，偏置电压可以大于约500V、大于约1,000V、大于约1,500V或大于约2,000V。
在图案化工艺期间，源极射频(RF)功率可以在约150W至约1,500W之间，例如在约150W至约250W之间、在约250W至约500W之间、在约500W至约1,000W之间或在约1,000W至约1,500W之间。
在图案化工艺期间，蚀刻室的压力可以在约1.0毫托至约10.0毫托之间，例如在约1.0毫托至约2.0毫托之间、在约2.0毫托至约5.0毫托之间、在约5.0毫托至约8.0毫托之间或在约8.0毫托至约10.0毫托之间。
在图案化工艺期间，蚀刻室的温度可以大于蚀刻副产物(例如，Zn(CH3)2)的挥发温度。在一些此实施例中，温度可以大于约46℃，例如大于约50℃。温度可以在约20℃至约250℃之间，例如在约20℃至约50℃之间、在约50℃至约100℃之间、在约100℃至约150℃之间、在约150℃至约200℃之间或在约200℃至约250℃之间。
在一些实施例中，可以通过在所谓的“一步”蚀刻中将沟道材料310暴露于蚀刻剂气体的混合物中来图案化沟道区域312。在其它实施例中，沟道材料310可以暴露于蚀刻剂气体的不同组合物中。举例来说，沟道材料310可以暴露于交替的蚀刻组合物中，所述蚀刻组合物包含包括溴化氢和载气的第一组合物和包含一或多种被配置成减少或防止聚合物形成的气体的第二组合物。在一些此实施例中，包括溴化氢、甲烷和载气的第一组合物可以被循环以去除沟道材料310。在将沟道材料310暴露于第一组合物之后，可以将沟道材料310暴露于第二气体组合物，所述第二气体组合物包括载气以及氢气、氧气和三氟化氮中的一或多种。在一些实施例中，当将沟道材料310暴露于第二气体组合物时，可以不施加偏置电压。图案化沟道材料310可以包含执行暴露于第一气体组合物的多个循环，随后执行暴露于第二气体组合物的多个循环。
不希望受任何特定理论的束缚，据信，甲烷、溴化氢、氢气和三氟化氮的组合促进沟道材料310的图案化，并且维持沟道区域312的临界尺寸。据信，甲烷蚀刻沟道材料310，并且保留掩模材料(例如，碳)。氢气还可以蚀刻沟道材料310，并且可以减少或基本上防止可能由甲烷蚀刻剂形成的聚合物的量。另外，三氟化氮减少了可能由甲烷形成的聚合物的量。据信，施加具有脉冲的高偏置电压(例如，大于约400V的偏置电压)可以促进形成基本上竖直的侧壁，并且可以基本上减少或消除形成通常伴随基于烷烃的蚀刻剂的聚合物副产物。
用含溴化氢的蚀刻剂图案化沟道区域312可以促进形成具有比常规半导体装置中形成的填充密度更高的填充密度的沟道区域312。令人惊讶的是，用含溴化氢的气体图案化沟道区域312形成具有基本上竖直的侧壁(例如，侧壁相对于衬底302的主表面具有在例如约80°和约90°之间的角度)的沟道区域312。由于沟道区域312用含溴化氢的蚀刻剂形成有基本上竖直的侧壁，所以可以增加沟道区域312的填充密度。沟道区域312的侧壁可以表现出光滑和清洁的表面。作为比较，用其它蚀刻剂(例如，三氯化硼(BCl3))蚀刻的氧化物半导体通常表现出相对较高的表面粗糙度，并且蚀刻剂在一些半导体结构中不能达到期望的填充密度。主要由烷烃形成的蚀刻化学物质可以在沟道区域312的表面上留下残余物。在一些实施例中，此蚀刻剂可能不期望地改变沟道区域312的化学和电特性。令人惊讶的是，用包含烷烃的含溴化氢气体图案化沟道区域312不会在沟道区域312的表面上形成残留物。
参考图3E，可以在半导体结构300上方共形地形成栅极介电材料314，例如在沟道区域312上方和在沟道区域312之间的空间中。栅极介电材料314可以包含上文参考图2A和图2B所述的任何栅极介电材料148。在一些实施例中，栅极介电材料314包括氧化物材料。栅极介电材料314可以由ALD、CVD、LPCVD、PECVD、PVD、另一种方法或其组合形成。
在形成栅极介电材料314之后，栅极电极材料316可以与栅极介电材料314相邻(例如，在上方)形成。栅极电极材料316可以形成在栅极介电材料314上方。栅极电极材料316可以包含上文参考图2A和图2B所述的栅极电极150的任何材料。在一些实施例中，栅极电极材料316包括氮化钛。栅极电极材料316可以由ALD、CVD、LPCVD、PECVD、PVD、另一种方法或其组合形成。
参考图3F，在形成栅极介电材料314和栅极电极材料316之后，可以图案化栅极介电材料314和栅极电极材料316。在一些实施例中，可以从横向延伸的表面(例如，基本上平行于衬底302的主表面延伸的表面)去除栅极电极材料316。可以通过例如干蚀刻、湿蚀刻或其组合的方法去除栅极电极材料316。在一些实施例中，通过将栅极电极材料316暴露于干蚀刻(例如，通过反应离子蚀刻)去除栅极电极材料316。栅极电极材料316可以保留在沟道区域312的侧壁上的栅极介电材料314上。在一些实施例中，栅极电极材料316可以延伸至介电材料308的表面，并且可以与源极区域306电隔离。
在图案化栅极电极材料316之后，可以图案化栅极介电材料314。可以去除栅极介电材料314的部分以形成从沟道材料312的侧壁上的介电材料308延伸至沟道材料312的上表面的栅极介电材料314。栅极介电材料314可以将沟道区域312与栅极电极材料316电隔离。沟道材料312的一部分可以通过栅极介电材料312保持暴露。
参考图3G，可以形成与栅极电极316电连通的导电线318。在一些实施例中，导电线318包括导电字线，并且与上文参考图2A所述的导电字线160基本上相同。导电线318可以包含导电材料，例如多晶硅、导电掺杂的硅、钨、氮化钨、镍、钽、氮化钽、硅化钽、铂、铜、银、金、铝、钼、钛、氮化钛、硅化钛、氮化钛铝、氮化钼、铱、氧化铱、钌、氧化钌及其组合。在一些实施例中，导电线318包含氮化钛。
图3H是沿图3H的剖面线H-H截取的半导体结构300的横截面图。半导体结构300可以包含源极区域306与沟道材料310的堆叠。参考图3I，可以在第二方向上去除沟道区域312的部分以在第二方向(例如，在y方向上)上图案化沟道区域312。沟道区域312可以如上文参考图3D所述的那样被图案化。作为非限制性实例，沟道材料310可以暴露于包括含溴化氢的气体的干蚀刻剂。
参考图3J，可以在半导体结构300上方形成并且图案化绝缘材料320。可以图案化绝缘材料320以填充相邻的沟道区域312之间的空间。绝缘材料320可以包含二氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、硼磷硅酸盐玻璃、氟硅酸盐玻璃、二氧化钛、二氧化锆、二氧化铪、氧化钽、氧化镁、氧化铝、氮化硅、氮氧化硅、无定形碳或其组合。
参考图3K，可以在半导体结构300上方形成漏极材料，以在沟道区域312上方形成并且与其直接接触的漏极区域322，并且形成竖直薄膜晶体管324。可以图案化漏极材料以形成如上文参考图2A和图2B所述的竖直薄膜晶体管。
可以通过在半导体结构300上方(例如，在沟道区域312上方以及在相邻的沟道区域312之间的区域中)形成导电材料来形成漏极区域322。可以在沟道区域312上方图案化漏极区域322。可以通过例如湿蚀刻、干蚀刻或其组合来图案化漏极区域320。作为非限制性实例，要去除的漏极区域322的部分可以通过掩模暴露于蚀刻溶液以去除其暴露的部分。在其它实施例中，要去除的漏极区域322的部分可以暴露于反应离子蚀刻工艺以去除此些部分。参考图3K和图1，漏极区域322可以被配置成与例如电容器结构130的第一电极132电连通。因此，竖直薄膜晶体管324可以通过漏极区域322与电容器区域108电连通。
在形成漏极区域322之后，可以执行附加的处理以形成完整的半导体结构，例如上文参考图1所述的半导体结构100。作为非限制性实例，可以在漏极区域322上方形成电容器结构130(图1)以将每个竖直薄膜晶体管324与电容器结构130电连接。互连区域110(图1)可以通过本领域普通技术人员理解的方法形成。
所得半导体结构可以包含竖直薄膜晶体管阵列，其包含氧化物半导体沟道材料。根据本公开的实施例的竖直薄膜晶体管阵列可以比在常规半导体结构中更紧密地填充，可以具有基本上竖直的侧壁，并且可以基本上不存在常规半导体结构中常见的蚀刻残留物。
因此，在一些实施例中，形成半导体结构的方法包括形成竖直薄膜晶体管阵列。形成竖直薄膜晶体管阵列包括：形成源极区域；在源极区域上方形成包括氧化物半导体材料的沟道材料；将沟道材料暴露于包括溴化氢的干蚀刻剂以将沟道材料图案化为相邻的竖直薄膜晶体管结构的沟道区域；在沟道区域的侧壁上形成栅极介电材料；在栅极介电材料上方形成栅极电极材料，以及在沟道区域上方形成漏极区域。
因此，在一些实施例中，形成半导体结构的方法包括：形成导电源线；在导电源线上方图案化包括氧化物半导体材料的沟道材料以形成在第一方向上延伸的沟道材料的行，其中图案化沟道材料包括将沟道材料暴露于包括含溴化氢的气体的干蚀刻剂；在沟道材料的行的侧壁上形成栅极氧化物；在栅极氧化物上方形成栅极电极，以及图案化沟道材料的行以形成包括竖直薄膜晶体管的隔离的沟道区域。
因此，在其它实施例中，形成存储器单元阵列的方法包括形成竖直薄膜晶体管阵列。形成竖直薄膜晶体管阵列包括：在导电源极材料上方将包括氧化物半导体材料的沟道材料暴露于包括溴化氢的干蚀刻剂以形成沟道材料的行；在沟道材料的行的侧壁上形成栅极氧化物；在栅极氧化物上方形成栅极电极；将沟道材料的行暴露于干蚀刻剂以形成隔离的竖直薄膜晶体管结构，以及在隔离的竖直薄膜晶体管中的每一者的沟道材料上方形成漏极区域。所述方法进一步包括在隔离的竖直薄膜晶体管中的每一者的漏极区域上方形成与其接触的电容器结构。
尽管已经结合附图描述了某些说明性实施例，但本领域的技术人员将认识并了解，本公开所涵盖的实施例不限于本文中明确展示和所述的那些实施例。相反，在不脱离本公开所涵盖的实施例的范围的情况下，可以对本文中所述的实施例进行许多添加、删除和修改，例如下文要求保护的那些，包含法定等同物。另外，来自一个所揭示的实施例的特征可以与另一个所揭示的实施例的特征组合，同时仍然涵盖在本公开的范围内。

Claims (24)

1.一种形成半导体结构的方法，所述方法包括：
形成竖直薄膜晶体管阵列，形成所述竖直薄膜晶体管阵列包括：
形成源极区域；
在所述源极区域上方形成包括氧化物半导体材料的沟道材料；
将所述沟道材料暴露于包括溴化氢的干蚀刻剂以将所述沟道材料图案化为相邻的竖直薄膜晶体管结构的沟道区域；
在所述沟道区域的侧壁上形成栅极介电材料；
形成与所述栅极介质材料相邻的栅极电极材料；以及
在所述沟道区域上方形成漏极区域。
2.根据权利要求1所述的方法，其中形成包括所述氧化物半导体材料的沟道材料包括形成包括1:1:1:4的In:Ga:Zn:O的比率、2:2:1的In2O3:Ga2O3:ZnO的比率或InGaO3(ZnO)5的沟道材料。
3.根据权利要求1所述的方法，其中将所述沟道材料暴露于包括溴化氢的干蚀刻剂包括将所述沟道材料暴露于包括溴化氢和至少一种烷烃的干蚀刻剂。
4.根据权利要求3所述的方法，其中将所述沟道材料暴露于包括溴化氢和至少一种烷烃的干蚀刻剂包括将所述沟道材料暴露于包括溴化氢和甲烷的干蚀刻。
5.根据权利要求4所述的方法，其中将所述沟道材料暴露于包括溴化氢和甲烷的干蚀刻剂包括，对于约每1.0份溴化氢，将所述沟道材料暴露于在约0.1份至约5.0份之间的甲烷。
6.根据权利要求1所述的方法，其中图案化所述沟道材料包括形成每个沟道区域，使得每个沟道区域在第一方向上与相邻的沟道区域相隔约10nm至约40nm且在第二方向上与相邻的沟道区域相隔约20nm至约50nm。
7.根据权利要求1所述的方法，其中将所述沟道材料暴露于包括溴化氢的干蚀刻剂包括将所述沟道材料暴露于包括溴化氢、甲烷、氢气和三氟化氮的干蚀刻剂。
8.根据权利要求1所述的方法，其中将所述沟道材料暴露于包括溴化氢的干蚀刻剂包括：
将所述通道材料暴露于包括溴化氢的第一组合物；以及
在将所述沟道材料暴露于所述第一组合物之后，将所述沟道材料暴露于包括氢气和三氟化氮中的至少一种的第二组合物。
9.根据权利要求1所述的方法，其中将所述沟道材料暴露于干蚀刻剂包括在大于约50℃的温度下将所述沟道材料暴露于所述干蚀刻剂。
10.根据权利要求1所述的方法，其进一步包括施加大于约2,000V的偏置电压，同时将所述沟道材料暴露于所述干蚀刻剂。
11.根据权利要求1所述的方法，其中形成与所述栅极介电材料相邻的栅极电极材料包括形成包括与所述栅极介电材料相邻的氮化钛的栅极电极材料。
12.根据权利要求1所述的方法，其中将所述沟道材料暴露于包括溴化氢的干蚀刻剂以将所述沟道材料图案化为相邻竖直薄膜晶体管结构的沟道区域包括：
将所述沟道材料暴露于所述干蚀刻剂以在第一方向上形成所述沟道材料的线；以及
将所述沟道材料的所述线的部分暴露于所述干蚀刻剂以形成相邻的竖直薄膜晶体管的所述沟道区域。
13.一种形成半导体结构的方法，所述方法包括：
形成导电源极区域；
在所述导电源极区域上方图案化包括氧化物半导体材料的沟道材料以形成在第一方向上延伸的所述沟道材料的行，其中图案化所述沟道材料包括将所述沟道材料暴露于包括含溴化氢的气体的干蚀刻剂；
在所述沟道材料的所述行的侧壁上形成栅极氧化物；
形成与所述栅极氧化物相邻的栅极电极；以及
图案化所述沟道材料的所述行以形成包括竖直薄膜晶体管的隔离的沟道区域。
14.根据权利要求13所述的方法，其中图案化包括所述氧化物半导体材料的沟道材料包括将沟道材料图案化为具有在约40nm至约100nm之间的高度。
15.根据权利要求13所述的方法，其中图案化包括氧化物半导体材料的沟道材料以形成所述沟道材料的行包括将所述沟道材料的所述行形成为具有在约10nm至约40nm之间的间距。
16.根据权利要求13所述的方法，其中图案化所述沟道材料的所述行以形成隔离的沟道区域包括将所述隔离的沟道区域形成为具有约5nm和约40nm之间的宽度。
17.根据权利要求13所述的方法，其中图案化包括氧化物半导体材料的沟道材料包括将所述沟道材料暴露于进一步包括氢气的干蚀刻剂。
18.根据权利要求13所述的方法，其中将所述沟道材料暴露于干蚀刻剂包括将所述沟道材料暴露于包括三氟化氮的干蚀刻剂。
19.根据权利要求18所述的方法，其中将所述沟道材料暴露于干蚀刻剂包括将所述沟道材料暴露于包括甲烷的干蚀刻剂。
20.根据权利要求13所述的方法，其中图案化沟道材料包括将所述沟道材料的所述行形成为具有侧壁，所述侧壁相对于衬底的主表面具有在约80°与约90°之间的角度。
21.根据权利要求13所述的方法，其中形成所述导电源极区域包括将所述导电源极区域形成为包括钨。
22.根据权利要求13所述的方法，其进一步包括在每个薄膜晶体管上方形成与其接触的电容器结构。
23.根据权利要求13所述的方法，其进一步包括在所述竖直薄膜晶体管中的每一者的所述沟道材料上方形成漏极区域。
24.根据权利要求20所述的方法，其中将所述沟道材料暴露于所述干蚀刻剂包括将所述沟道材料暴露于甲烷、氢气和三氟化氮。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113380898A (zh) * 2020-05-29 2021-09-10 台湾积体电路制造股份有限公司 半导体晶体管及其形成方法、及半导体器件

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10714400B2 (en) * 2017-08-30 2020-07-14 Micron Technology, Inc. Methods of forming semiconductor structures comprising thin film transistors including oxide semiconductors
US20230197896A1 (en) * 2019-10-30 2023-06-22 The Regents Of The University Of California Method to improve the performance of gallium-containing light-emitting devices
US11476248B2 (en) 2019-12-26 2022-10-18 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuit and fabrication thereof
US11581366B2 (en) * 2020-06-22 2023-02-14 Taiwan Semiconductor Manufacturing Company Limited Memory cell device with thin-film transistor selector and methods for forming the same
US11515313B2 (en) 2020-06-22 2022-11-29 Taiwan Semiconductor Manufacturing Company Limited Gated ferroelectric memory cells for memory cell array and methods of forming the same
KR20220007393A (ko) 2020-07-10 2022-01-18 삼성전자주식회사 반도체 메모리 소자
US11908932B2 (en) 2020-07-23 2024-02-20 Micron Technology, Inc. Apparatuses comprising vertical transistors having gate electrodes at least partially recessed within channel regions, and related methods and systems
KR20220043981A (ko) 2020-09-28 2022-04-06 삼성전자주식회사 반도체 메모리 장치
KR20220089875A (ko) 2020-12-22 2022-06-29 삼성전자주식회사 반도체 메모리 장치 및 그 제조 방법
KR20220102242A (ko) 2021-01-13 2022-07-20 삼성전자주식회사 반도체 메모리 장치 및 그 제조 방법
US12040409B2 (en) 2021-02-09 2024-07-16 Taiwan Semiconductor Manufacturing Company Limited Thin film transistor including a dielectric diffusion barrier and methods for forming the same
KR20240002609A (ko) * 2022-06-29 2024-01-05 삼성전자주식회사 반도체 소자

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060175609A1 (en) * 2004-05-20 2006-08-10 Chan Isaac W T Vertical thin film transistor with short-channel effect suppression
KR20090017046A (ko) * 2007-08-13 2009-02-18 성균관대학교산학협력단 더미 드레인층을 이용한 수직 실린더형 트랜지스터의제조방법 및 이에 의해 제조된 수직 실린더형 트랜지스터
US20110108706A1 (en) * 2009-11-06 2011-05-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and operating method thereof
US20130230955A1 (en) * 2012-03-01 2013-09-05 Meng-Hsien Chen Method for fabricating a vertical transistor
US20150249143A1 (en) * 2014-02-28 2015-09-03 Sandisk 3D Llc Method For Forming Oxide Below Control Gate In Vertical Channel Thin Film Transistor
US20170221559A1 (en) * 2016-01-29 2017-08-03 Sandisk Technologies Llc Vacancy-modulated conductive oxide resistive ram device including an interfacial oxygen source layer

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11162941A (ja) * 1997-11-28 1999-06-18 Nec Corp ドライエッチング方法
US6424001B1 (en) 2001-02-09 2002-07-23 Micron Technology, Inc. Flash memory with ultra thin vertical body transistors
US7138685B2 (en) 2002-12-11 2006-11-21 International Business Machines Corporation Vertical MOSFET SRAM cell
JP4999400B2 (ja) 2006-08-09 2012-08-15 キヤノン株式会社 酸化物半導体膜のドライエッチング方法
KR101788521B1 (ko) 2009-10-30 2017-10-19 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
CN103151266B (zh) * 2009-11-20 2016-08-03 株式会社半导体能源研究所 用于制造半导体器件的方法
WO2012121265A1 (en) * 2011-03-10 2012-09-13 Semiconductor Energy Laboratory Co., Ltd. Memory device and method for manufacturing the same
US9111795B2 (en) 2011-04-29 2015-08-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with capacitor connected to memory element through oxide semiconductor film
KR20130103942A (ko) 2012-03-12 2013-09-25 에스케이하이닉스 주식회사 무접합 수직 게이트 트랜지스터를 갖는 반도체 소자 및 그 제조 방법
US8952470B2 (en) 2012-09-10 2015-02-10 James John Lupino Low cost high density nonvolatile memory array device employing thin film transistors and back to back Schottky diodes
US9105468B2 (en) * 2013-09-06 2015-08-11 Sandisk 3D Llc Vertical bit line wide band gap TFT decoder
US9379246B2 (en) * 2014-03-05 2016-06-28 Sandisk Technologies Inc. Vertical thin film transistor selection devices and methods of fabrication
US9263577B2 (en) 2014-04-24 2016-02-16 Micron Technology, Inc. Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors
US10037397B2 (en) * 2014-06-23 2018-07-31 Synopsys, Inc. Memory cell including vertical transistors and horizontal nanowire bit lines
US9397145B1 (en) 2015-05-14 2016-07-19 Micron Technology, Inc. Memory structures and related cross-point memory arrays, electronic systems, and methods of forming memory structures
US10304959B2 (en) * 2017-07-17 2019-05-28 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd Array substrate, display device, and method of manufacturing the same
US10714400B2 (en) * 2017-08-30 2020-07-14 Micron Technology, Inc. Methods of forming semiconductor structures comprising thin film transistors including oxide semiconductors
CN111052395A (zh) * 2017-08-31 2020-04-21 美光科技公司 半导体装置、晶体管以及用于接触金属氧化物半导体装置的相关方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060175609A1 (en) * 2004-05-20 2006-08-10 Chan Isaac W T Vertical thin film transistor with short-channel effect suppression
KR20090017046A (ko) * 2007-08-13 2009-02-18 성균관대학교산학협력단 더미 드레인층을 이용한 수직 실린더형 트랜지스터의제조방법 및 이에 의해 제조된 수직 실린더형 트랜지스터
US20110108706A1 (en) * 2009-11-06 2011-05-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and operating method thereof
US20130230955A1 (en) * 2012-03-01 2013-09-05 Meng-Hsien Chen Method for fabricating a vertical transistor
US20150249143A1 (en) * 2014-02-28 2015-09-03 Sandisk 3D Llc Method For Forming Oxide Below Control Gate In Vertical Channel Thin Film Transistor
US20170221559A1 (en) * 2016-01-29 2017-08-03 Sandisk Technologies Llc Vacancy-modulated conductive oxide resistive ram device including an interfacial oxygen source layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113380898A (zh) * 2020-05-29 2021-09-10 台湾积体电路制造股份有限公司 半导体晶体管及其形成方法、及半导体器件
CN113380898B (zh) * 2020-05-29 2024-02-02 台湾积体电路制造股份有限公司 半导体晶体管及其形成方法、及半导体器件

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