CN1109357C - 半导体器件生产方法 - Google Patents

半导体器件生产方法 Download PDF

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CN1109357C
CN1109357C CN98125646A CN98125646A CN1109357C CN 1109357 C CN1109357 C CN 1109357C CN 98125646 A CN98125646 A CN 98125646A CN 98125646 A CN98125646 A CN 98125646A CN 1109357 C CN1109357 C CN 1109357C
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antireflection coating
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齐藤和美
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Renesas Electronics Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers
    • H01L21/31133Etching organic layers by chemical means
    • H01L21/31138Etching organic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • H01L21/0276Photolithographic processes using an anti-reflective coating

Abstract

半导体器件生产方法,包含如下步骤:在半导体基片上形成绝缘膜,在绝缘膜上形成由导电材料构成的导电薄膜,在导电薄膜上形成由有机材料构成的防反射敷层,在防反射敷层上形成光敏光刻胶膜,通过暴光在光刻胶膜上显影预定的光图像,以形成光刻胶图形,用包含氧气,反应气及惰性气体的混合气的等离子体的干蚀选择的去除防反射敷层,从而形成防反射敷层图形,并用光刻胶图形作为掩膜蚀刻导电薄膜,从而形成电极。

Description

半导体器件生产方法
技术领域
本发明涉及一种半导体器件的生产方法,其用于多级互连结构中形成互连图形。
背景技术
LSI(大规模集成电路)是通过重复如下步骤进行的,即半导体基片上形成由各种材料形成的薄膜,然后通过光刻和蚀刻部分去除薄膜。光刻的作用是在预定的位置形成具有预定尺寸的图形。蚀刻的作用是通过用光刻形成的图形做掩膜从表面部分去除薄膜,从而形成具有所需尺寸的薄膜材料构成的互连。
下面对构成LSI的金属氧化物半导体晶体管的栅电极互连进行描述。
如图2A所示,在硅基片201上形成栅绝缘膜202,导电膜(例如多晶硅膜)203形成在栅绝缘膜202上。如图2B中所示,在导电膜203上形成防反射敷层(ARC)204。
如图2C中所示,通过公知的光刻技术在防反射敷层204上形成光刻胶图形205。在此光刻技术中,由于防反射敷层204形成在光刻胶图形205下面,可防止形成妨碍形成高精度图形的驻波效应。
如图2D所示,用光刻胶图形205作为掩膜蚀刻防反射敷层204,从而形成图形204a。使用混合气体的干蚀进行此种蚀刻,其中的混合气体是通过将氯气或溴化氢气体加入氧气中所获得的。
由于防反射敷层204为有机膜,其可通过用氧气的干蚀进行蚀刻。如果只使用氧气,会产生降低尺寸精度的侧蚀。通常的,在干蚀的反应过程中,反应物会在等离子体中分解,再次到达加工材料的表面,并会沉积到等离子体中的加工材料的表面上,或会在加工材料的表面上产生聚合反应。当通过氧等离子体对有机膜进行干蚀时,所获得的反应物主要是二氧化碳和水,其不会容易的造成重新覆盖或沉积。
与此相对比,如果用氧气和加入其中的氯气进行干蚀,在加工材料的表面会产生由等离子体聚合造成的沉积。当在光刻胶图形205的侧面或在通过蚀刻已经露出的防反射敷层204的图形204a的侧面产生沉积时,可抑制侧蚀。更具体的,在作为有机膜的防反射敷层204的干蚀中,当使用将氯气加入氧气所获得的蚀刻气体时,可提高尺寸精度。
如图2E所示,通过用光刻胶图形205和204a作为掩膜,蚀刻导电膜203以形成栅电极203a。
对于传统的方法,在图2D的形成图形204a的步骤中,由于在图形204a和导电膜当203间的界面导电膜203被部分过蚀刻,如图3A所示,会形成相对较大的亚槽301。在这些亚槽存在时,当蚀刻导电膜203形成栅电极203a时,由于对应于亚槽301的导电膜的厚度比其他地方的小,从而在该处所蚀刻的导电膜消失的比其他地方的快。
因此,当完全去除不包括栅电极203a的部分的导电膜203时,在基片301下面的部分也被大大的过蚀。相应的,对栅绝缘膜202及部分硅基片201的蚀刻会形成如图3B中所示的基片损伤。
在防反射敷层204的蚀刻中通过降低氯气的含量可抑制这些不足。更具体的,当反应气体的量(如氯气)降低时,基片301的尺寸也降低。
然而当氯气的含量降低时,会发生侧蚀,引起尺寸精度的降低,这会导致产量的降低。
发明内容
本发明的目的是提供一种半导体器件的生产方法,其中,通过抑制缺陷而增加半导体器件的产量。
为了实现上述目的,根据本发明,所提供的半导体器件的生产方法包含如下步骤:在半导体基片上形成绝缘膜,在绝缘膜上形成由导电材料构成的导电薄膜,在导电薄膜上形成由有机材料构成的防反射敷层,在防反射敷层上形成光敏光刻胶膜,通过暴光在光刻胶膜上显影预定的光图像,以形成光刻胶图形,用包含氧气,反应气及惰性气体的混合气的等离子体的干蚀选择的去除防反射敷层,从而形成防反射敷层图形,并用光刻胶图形作为掩膜蚀刻导电薄膜,从而形成电极。
如上所述,根据本发明,用氧气,反应气及惰性气体等的混合气体的等离子体进行干蚀,同时用保护膜图形作为掩膜。通过与反应气体反应产生的等离子体反应物被作为侧壁保护膜沉积到保护图形的侧壁及形成在保护图形下面的图形上,并选择去除防反射敷层从而形成图形。因此,可抑制在蚀刻防反射敷层过程中有时发生的不同蚀刻速率的问题。
其结果,可抑制在蚀刻防反射敷层中由于部分异常所引起的缺陷,从而可提高半导体器件的产量。
附图说明
图1A到1E为根据本发明实施例的半导体器件生产方法的个步骤的截面示意图;
图2A到2E为传统半导体器件生产方法的各步骤的截面示意图;
图3A到3B为用于解释亚槽形成原因的截面示意图。
具体实施方式
下面将参考相应附图对本发明进行详细描述。
图1A到1E为根据本发明实施例的半导体器件生产方法的示意图。将针对构成LSI的MOS晶体管的栅电极互连进行描述,与图2A到图2E的情况相同。
首先,如图1A中所示,在硅基片101上形成上绝缘膜102,此后,在栅绝缘膜102上形成诸如多晶硅的导电膜103。如图1B中所示,在导电膜103上形成200纳米厚的防反射敷层104,在防反射敷层104上形成大约700纳米厚的具有正光敏性的光刻胶膜105。
例如,如果波长为248纳米的紫外光被用做暴光光源,SWK-EX1-D55(有机防反射膜;商标名,由TOKYO OHKA公司生产)可被用做防反射敷层104。例如,通过旋涂形成有导电膜103的硅基片提供SKY-EX1-D55溶液。所形成的结构被加热到大约170度到220度,从而,形成防反射敷层104。
通过旋涂向形成有防反射敷层104硅基片提供光刻胶材料,通过加热到90度到100度的蒸发从覆膜去除溶剂,从而形成光刻胶膜105。
接着,通过用还原投影暴光在光刻胶膜105上投影和暴光所需的图像,由此形成潜像。此后,用碱性显影液显影潜影,并去除投影光图像的区域,从而形成如图1C所示的保护膜图像105a。最好将此保护膜图像加热到110度到120度以便提高干蚀阻力。
在此暴光工艺中,由底层反射的光同样被辐射到在其上将要转换图形的光刻胶膜105上,并相应的如射光和反射光彼此交叉造成驻波效应。驻波效应大大的影响通过光刻技术形成的保护膜图形的尺寸精度。因此,上述的防反射敷层104形成在底层上以抑制暴光的反射,从而防止驻波效应。
如图1D所示,用保护膜图形105a作为掩膜蚀刻防反射敷层104,从而形成图形104a。这是通过干蚀进行的,其中的干蚀所示用的混合气是通过将作为惰性气体的氩气加入作为反应气的氯气或溴化氢与氧气的混合气中。更具体的,通过将氯气∶氧气∶氩气的比率设定为3∶2∶8,压力为3.999帕(Pa),等离子体功率为350瓦,并将基片温度控制到35度。
如上所述,在用于形成作为有机膜的防反射敷层104的干蚀中,不仅加入氧气而且加入氯气的蚀刻气体被用来提高尺寸精度。然而,由于加入了氯气,会产生亚槽的问题。
通过用氧气和溴化氢气体的混合气及氧气和四氟化碳(CF4)的混合气体而不用氧气和氯气的混合气可在抑制侧蚀的情况下蚀刻防反射敷层104。然而当在将反应气加入氧气的情况下进行干蚀的情况下,仍然会发生亚槽的问题。
为此,如上所述,在此实施例中,除了使用氧气和反应气体外还使用了诸如氩气的惰性气体进行防反射敷层104的干蚀。其结果,在此实施例中,可最大的抑制亚槽的尺寸。
在上述的实施例中,氯气∶氧气∶氩气=3∶2∶8。然而,本发明并不限于此,例如,如果诸如氩气的惰性气体与所引入用于蚀刻的蚀刻气体的总量的比率设定位20%到90%,可最大的抑制所形成的亚槽的尺寸。
所形成的为数很少的几个亚槽假设是形成在用保护图形105a作掩膜的蚀刻防反射敷层104的初级阶段。更具体的,在蚀刻防反射敷层104的过程中,保护膜图形105a的边缘部分被蚀刻的比其他部分快,亚槽形成在防反射敷层104蚀刻过程中的初级阶段。
相应的,在干蚀防反射敷层104的开始必须加入氩气。当在此情况下加入氩气时,由于氩气为正性气体,可抑制作为有机基片的保护膜105a中的充电,还可抑制光刻胶膜105边缘部分的反应离子的浓度。
在形成图形104a后,用光刻胶膜105和图形104a作为掩膜蚀刻导电膜103,从而形成如图1E中所示的栅电极103a。
其结果,根据本发明,可抑制在栅绝缘膜102与栅电极103a间的边缘部分产生过蚀等缺陷,由此可形成在栅绝缘膜102无异常现象的栅电极。
如上所述,根据本发明,用氧气,反应气及惰性气体等的混合气体的等离子体进行干蚀,同时用保护膜图形作为掩膜。通过与反应气体反应产生的等离子体反应物被作为侧壁保护膜沉积到保护图形的侧壁及形成在保护图形下面的图形上,并选择去除防反射敷层从而形成图形。因此,可抑制在蚀刻防反射敷层过程中有时发生的不同蚀刻速率的问题。
其结果,可抑制在蚀刻防反射敷层中由于部分异常所引起的缺陷,从而可提高半导体器件的产量。

Claims (8)

1.一种半导体器件的生产方法,其特征在于包含如下步骤:
在半导体基片上形成绝缘膜(102);
在所述绝缘膜上形成由导电材料构成的导电薄膜(103);
在所述导电薄膜上形成由有机材料构成的防反射敷层(104);
在所述防反射敷层上形成光敏光刻胶膜(105);
通过暴光在所述光刻胶膜上显影预定的光图像,以形成光刻胶图形(105a);
用包含氧气,反应气及惰性气体的混合气的等离子体的干蚀选择的去除所述防反射敷层,用所述保护图形作为掩膜,从而形成防反射敷层图形(104a);及
并用所述保护膜图形作为掩膜蚀刻所述导电薄膜,从而形成电极(103a)
2.根据权利要求1所述的方法,其特征在于形成所述防反射敷层图形的步骤包含在所述保护膜图形及防反射敷层图形的侧壁上沉积作为侧壁保护膜的通过与所述反应气反应所产生的等离子体产物。
3.根据权利要求1所述的方法,其特征在于反应气为氯气。
4.根据权利要求1所述的方法,其特征在于反应气为溴化氢气体。
5.根据权利要求1所述的方法,其特征在于反应气为四氟化碳气体。
6.根据权利要求1所述的方法,其特征在于惰性气体为氩气。
7.根据权利要求1所述的方法,其特征在于所述惰性气体与混合气体总量的比率落在20%到90%的范围内。
8.根据权利要求7所述的方法,其特征在于反应气,氧气和惰性气体的流速比为3∶2∶8。
CN98125646A 1997-12-24 1998-12-23 半导体器件生产方法 Expired - Fee Related CN1109357C (zh)

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GB9828081D0 (en) 1999-02-17
CN1221214A (zh) 1999-06-30
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JPH11186235A (ja) 1999-07-09
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