CN110931443A - 半导体装置和包括其的半导体封装件 - Google Patents

半导体装置和包括其的半导体封装件 Download PDF

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CN110931443A
CN110931443A CN201910835996.0A CN201910835996A CN110931443A CN 110931443 A CN110931443 A CN 110931443A CN 201910835996 A CN201910835996 A CN 201910835996A CN 110931443 A CN110931443 A CN 110931443A
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pad
dielectric layer
layer
semiconductor
buffer
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崔朱逸
姜泌圭
金会哲
罗勋奏
朴宰亨
孙成旻
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本公开提供了半导体装置和包括其的半导体封装件。半导体装置包括第一电介质层上的第一缓冲电介质层；按次序布置在第一缓冲电介质层上的第二电介质层和第二缓冲电介质层，第二缓冲电介质层与第一缓冲电介质层接触；以及焊盘互连结构，其穿过第一缓冲电介质层和第二缓冲电介质层，其中焊盘互连结构包括铜和锡。

Description

半导体装置和包括其的半导体封装件
相关申请的交叉引用
于2018年9月20日在韩国知识产权局提交的标题为“半导体装置和包括其的半导体封装件”的韩国专利申请No.10-2018-0113157以引用方式全文并入本文中。
技术领域
实施例涉及一种半导体装置和包括其的半导体封装件。
背景技术
半导体装置因为它们的小尺寸、多功能性和/或低制造成本而广泛用于电子工业中。半导体装置可包含用于存储数据的存储器装置、用于处理数据的逻辑装置和用于同时操作各种功能的混合装置。
随着电子工业的先进发展，半导体装置具有高集成度。随着电子工业的先进发展，半导体装置还具有高速度。为了满足半导体装置的高集成度和/或高速度的要求，已经进行了各种研究。
发明内容
可通过提供一种半导体装置来实现实施例，所述半导体装置包括：第一电介质层上的第一缓冲电介质层；按次序布置在第一缓冲电介质层上的第二电介质层和第二缓冲电介质层，第二缓冲电介质层与第一缓冲电介质层接触；以及焊盘互连结构，其穿过第一缓冲电介质层和第二缓冲电介质层，其中焊盘互连结构包括铜和锡。
可通过提供一种半导体装置来实现实施例，所述半导体装置包括：第一电介质层；第一电介质层上的第二电介质层；以及第一电介质层与第二电介质层之间的焊盘连接器，其中焊盘连接器包括中心部分和包围中心部分的外部，并且其中焊盘连接器的粒度在从外部向中心部分的方向上增加。
可通过提供一种半导体封装件来实现实施例，所述半导体封装件包括：封装件衬底；封装件衬底上的第一半导体芯片，第一半导体芯片包括第一半导体层和堆叠在第一半导体层的第一表面上的第一缓冲电介质层；第一半导体芯片上的第二半导体芯片，第二半导体芯片包括第二半导体层和堆叠在第二半导体层的第一表面上的第二缓冲电介质层，第二缓冲电介质层与第一缓冲电介质层接触；以及第一焊盘互连结构，其穿过第一缓冲电介质层和第二缓冲电介质层，其中第一焊盘互连结构包括铜和锡。
附图说明
通过参照附图详细描述示例性实施例，特征将对于本领域技术人员变得清楚，其中：
图1示出了根据一些示例实施例的半导体装置的剖视图；
图2示出了显示图1的焊盘连接器的放大图；
图3示出了显示图2的部分A的放大图；
图4示出了显示根据一些示例实施例的半导体装置的剖视图；
图5示出了显示图4的焊盘连接器的放大图；
图6示出了显示根据一些示例实施例的半导体封装件的剖视图；
图7示出了显示图6的部分B的放大图；
图8示出了显示图6的部分C的放大图；
图9A至图9E示出了根据一些示例实施例的半导体装置的制造方法中的各阶段的剖视图；
图10A至图10C示出了根据一些示例实施例的半导体封装件的制造方法中的各阶段的剖视图。
具体实施方式
图1示出了根据一些示例实施例的半导体装置的剖视图。图2示出了显示图1的焊盘连接器的放大图。图3示出了显示图2的部分A的放大图。
参照图1，第一焊盘120可在第一电介质层110中的第一沟槽T1中。第一焊盘120可包括第一金属焊盘121和第一金属势垒层123。第一金属焊盘121可在第一沟槽T1中，并且在第一沟槽T1中，第一金属势垒层123可在第一金属焊盘121与第一电介质层110之间。第一金属焊盘121可具有彼此面对的(例如，彼此相对的)第一表面121a和第二表面121b。第一金属焊盘121的第一表面121a可在第一电介质层110暴露出来，并且第一金属焊盘121的第二表面121b和侧壁可在第一电介质层110中(例如，可面对第一电介质层110)。第一金属焊盘121的第一表面121a可与第一电介质层110的一个表面110a共面。第一金属势垒层123可包围第一金属焊盘121的侧壁和第二表面121b。第一金属势垒层123可暴露出第一金属焊盘121的第一表面121a和第一电介质层110的一个表面110a。例如，第一电介质层110可包括PETOS层或氧化硅层。例如，第一金属焊盘121可包括铜(Cu)、铝(Al)、镍(Ni)或钨(W)。例如，第一金属势垒层123可包括钛或钽。
第二电介质层130可在第一电介质层110上。第二焊盘140可在第二电介质层130中的第二沟槽T2中。第二焊盘140可包括第二金属焊盘141和第二金属势垒层145。第二金属焊盘141可在第二沟槽T2中，并且在第二沟槽T2中，第二金属势垒层145可在第二金属焊盘141与第二电介质层130之间。第二金属焊盘141可具有彼此面对的第一表面141a和第二表面141b。第二金属焊盘141的第一表面141a可在第二电介质层130暴露出来，并且第二金属焊盘141的第二表面141b和侧壁可在第二电介质层130中或者可面对第二电介质层130。第二金属焊盘141的第一表面141a可与第二电介质层130的一个表面130a共面。第二金属势垒层145可包围第二金属焊盘141的侧壁和第二表面141b。第二金属势垒层145可暴露出第二金属焊盘141的第一表面141a和第二电介质层130的一个表面130a。例如，第二电介质层130可包括PETOS层或者氧化硅层。例如，第二金属焊盘141可包括铜(Cu)、铝(Al)、镍(Ni)或钨(W)。例如，第二金属势垒层145可包括钛或钽。
第一缓冲电介质层150、第三电介质层160和第二缓冲电介质层170可按次序布置在第一电介质层110的一个表面110a上。第一缓冲电介质层150可覆盖第一金属焊盘121的第一表面121a(例如，的一部分)，其中第一表面121a通过第一电介质层110暴露。例如，第一缓冲电介质层150可包括氮化硅层或碳氮化硅层。第三电介质层160可在第一缓冲电介质层150上。第三电介质层160可覆盖第一缓冲电介质层150的一个表面。例如，第三电介质层160可包括PETOS层或氧化硅层。第二缓冲电介质层170可在第三电介质层160上。例如，第二缓冲电介质层170可包括氮化硅层或碳氮化硅层。
第三缓冲电介质层180、第四电介质层190和第四缓冲电介质层200可(例如，在图1中向下)按次序布置在第二电介质层130的一个表面130a上。第三缓冲电介质层180可覆盖第二金属焊盘141的第一表面141a(例如，的一部分)，其中第一表面141a通过第二电介质层130暴露出来。例如，第三缓冲电介质层180可包括氮化硅层或碳氮化硅层。第四电介质层190可在第三缓冲电介质层180上。第四电介质层190可覆盖第三缓冲电介质层180的一个表面。例如，第四电介质层190可包括PETOS层或氧化硅层。第四缓冲电介质层200可在第四电介质层190上。第四缓冲电介质层200和第二缓冲电介质层170可彼此接触。例如，第四缓冲电介质层200可包括氮化硅层或碳氮化硅层。
互连结构ICS可在第一电介质层110与第二电介质层130之间。例如，互连结构ICS可在第一电介质层110中的第一焊盘120与第二电介质层130中的第二焊盘140之间。互连结构ICS可穿过第一缓冲电介质层150、第三电介质层160、第二缓冲电介质层170、第三缓冲电介质层180、第四电介质层190和第四缓冲电介质层200。互连结构ICS可接触第一金属焊盘121的第一表面121a和第二金属焊盘141的第一表面141a。第一焊盘120和第二焊盘140可通过互连结构ICS彼此电连接。例如，互连结构ICS(的截面)可具有规则六边形或者矩形。
互连结构ICS可包括焊盘连接器210和连接金属势垒层220。连接金属势垒层220可包围焊盘连接器210。连接金属势垒层220可接触第一金属焊盘121和第二金属焊盘141。例如，连接金属势垒层220可包括钛或钽。连接金属势垒层220可用作扩散阻断层。参照图1和图2，焊盘连接器210可包括第一区段P1和第二区段P2。第一区段P1可穿过第三电介质层160和第二缓冲电介质层170，第二区段P2可穿过第四电介质层190和第四缓冲电介质层200。例如，第一区段P1和第二区段P2可相对于对称线L线性对称。例如，焊盘连接器210可包括铜(Cu)和/或锡(Sn)。例如，焊盘连接器210可具有其中FCC(面心立方体)和四方向结构彼此混合的点阵结构。在实施中，焊盘连接器210可具有其中FCC(面心立方体)和钻石立方结构彼此混合的点阵结构。
焊盘连接器210可包括中心部分CP、包围中心部分CP的第一中间部分IP1、包围第一中间部分IP1的第二中间部分IP2以及包围第二中间部分IP2的外部OP。外部OP可由连接金属势垒层220包围。在实施中，焊盘连接器210中的铜的量(例如，铜含量)可随着从外部OP到(或接近、或朝着)中心部分CP增大，或者可在从外部OP到(或接近、或朝着)中心部分CP的方向上增大，并且焊盘连接器210中的锡的量(例如，锡含量)可随着从外部OP到(或接近、或朝着)中心部分CP减小，或者可在从外部OP到(或接近、或朝着)中心部分CP的方向上减小。例如，焊盘连接器210的外部OP可包括铜，并且焊盘连接器210的中心部分CP可包括锡。在实施中，中心部分CP中的铜含量可大于中心部分CP中的锡含量。第一中间部分IP1中的铜含量可大于第一中间部分IP1中的锡含量但小于中心部分CP中的铜含量，并且第一中间部分IP1中的锡含量可大于中心部分CP中的锡含量。例如，第一中间部分IP1可为或包括Cu3Sn。第二中间部分IP2中的锡含量可大于第二中间部分IP2中的铜含量，并且第二中间部分IP2中的铜含量可小于第一中间部分IP1中的铜含量，并且第二中间部分IP2中的锡含量可大于第一中间部分IP1中的锡含量。例如，第二中间部分IP2可为或包括Cu6Sn5。外部OP中的锡含量可大于外部OP中的铜含量，并且外部OP中的铜含量可小于第二中间部分IP2中的铜含量，并且外部OP中的锡含量可大于第二中间部分IP2中的锡含量。
在实施中，如图3所示，焊盘连接器210的粒度可随着从外部OP接近中心部分CP增大，或者可在从外部OP接近中心部分CP的方向上增大。例如，中心部分CP的粒度GS1可大于第一中间部分IP1的粒度GS2(GS1＞GS2)，并且第一中间部分IP1的粒度GS2可大于第二中间部分IP2的粒度GS3(GS2＞GS3)。第二中间部分IP2的粒度GS3可大于外部OP的粒度GS4(GS3＞GS4)。例如，外部OP的粒度GS4可小于中心部分CP、第一中间部分IP1和第二中间部分IP2的所有其它粒度GS1、GS2和GS3。中心部分CP的粒度GS1可大于第一中间部分IP1、第二中间部分IP2和外部OP的所有其它粒度GS2、GS3和GS4。
图4示出了显示根据一些示例实施例的半导体装置的剖视图。图5示出了显示图4的焊盘连接器的放大图。为了简单描述，为与上述半导体装置的组件基本相同的组件分配相同标号，并且可省略对其的重复详细解释。
参照图4和图5，焊盘连接器210的第一区段P1和第二区段P2可相对于彼此在反方向上移位。例如，第一区段P1可在第一方向X上移位，并且第二区段P2可在(与第一方向X相反的)第二方向Y上移位。例如，第一区段P1的中心点C1可在第一方向X上从焊盘连接器210的中心点CO移动特定距离，并且第二区段P2的中心点C2可在第二方向Y上从焊盘连接器210的中心点CO移动特定距离，中心点C1和C2位于焊盘连接器210的对称线L上。焊盘连接器210的中心点CO可位于第一区段P1的中心点C1与第二区段P2的中心点C2之间的中心点。例如，在焊盘连接器210的第一区段P1和第二区段P2接触之前，焊盘连接器210的第一区段P1可相对于焊盘连接器210的第二区段P2偏移布置。
第一连接金属势垒层220a可包围第一区段P1的一个表面S1和侧壁。第一连接金属势垒层220a的一端可具有与第二缓冲电介质层170的一个表面共面的一个表面ES1，并且其另一端也可具有与第二缓冲电介质层170的一个表面共面的另一表面ES2，其中一个表面ES1可接触第二区段P2，并且另一表面ES2可接触第四缓冲电介质层200。第二连接金属势垒层220b可包围第二区段P2的一个表面S2和侧壁。第二连接金属势垒层220b的一端可具有与第四缓冲电介质层200的一个表面共面的一个表面ES3，并且其另一端也可具有与第四缓冲电介质层200的一个表面共面的另一表面ES4，其中一个表面ES3可接触第二缓冲电介质层170，并且另一表面ES4可接触第一区段P1。
图6示出了显示根据一些示例实施例的半导体封装件的剖视图。图7示出了显示图6的部分B的放大图。图8示出了显示图6的部分C的放大图。
参照图6，第一半导体芯片600可在封装件衬底500上。封装件衬底500可包括第一键合焊盘510和凸块520。第一键合焊盘510可在封装件衬底500的顶表面上。例如，第一键合焊盘510可包括导电材料。凸块520可在封装件衬底500的底表面上，其中底表面面对封装件衬底500的顶表面。凸块520可电连接至第一键合焊盘510。例如，凸块520可包括焊料球或柱。
第一半导体芯片600可通过粘合剂层601附着于封装件衬底500的顶表面。粘合剂层601可在第一半导体芯片600与封装件衬底500之间。例如，粘合剂层601可包括电介质聚合物。例如，第一半导体芯片600可为存储器芯片，诸如DRAM、SRAM、MRAM或闪速存储器。第一半导体芯片600可包括第一半导体层611和第一连接线结构620。第一半导体层611可包括半导体材料。第一半导体层611可在其第一表面611a上设有晶体管的一些部分(例如，栅电极)和/或无源装置。
第一连接线结构620可在第一半导体层611的第一表面611a上。一起参照图6和图7，第一连接线结构620可包括第一缓冲电介质层621、第一层间电介质层622、第二缓冲电介质层623、第二层间电介质层624、第三缓冲电介质层625和第一焊盘626。第一缓冲电介质层621可在第一半导体层611的第一表面611a上。例如，第一缓冲电介质层621可包括氮化硅层或碳氮化硅层。第一层间电介质层622可在第一缓冲电介质层621的顶表面上。例如，第一层间电介质层622可包括PETOS层或氧化硅层。第二缓冲电介质层623可在第一层间电介质层622的顶表面上。例如，第二缓冲电介质层623可包括氮化硅层或碳氮化硅层。第二层间电介质层624可在第二缓冲电介质层623的顶表面上。例如，第二层间电介质层624可包括PETOS层或氧化硅层。第三缓冲电介质层625可在第二层间电介质层624的顶表面上。例如，第三缓冲电介质层625可包括氮化硅层或碳氮化硅层。
第一焊盘626可在第一缓冲电介质层621和第一层间电介质层622中。例如，第一焊盘626中的每一个可在穿过第一缓冲电介质层621和第一层间电介质层622的第一沟槽TH1中。第一焊盘626可包括第一金属焊盘627和第一金属势垒层629。第一金属势垒层629可在第一沟槽TH1的底表面和侧壁上。第一金属势垒层629可接触第一半导体层611的第一表面611a。第一金属焊盘627可在第一沟槽TH1中。第一金属焊盘627可具有与第一层间电介质层622的顶表面共面的第一表面627a。第一金属势垒层629可包围第一金属焊盘627的侧壁和第二表面，第二表面面对第一表面627a。例如，第一金属势垒层629可包括钛(Ti)或钽(Ta)。例如，第一金属焊盘627可包括铜(Cu)、铝(Al)、镍(Ni)或钨(W)。
第二半导体芯片710可在第一连接线结构620上。第二半导体芯片710可包括第二半导体层711、第二连接线结构715和第三连接线结构810。第二半导体芯片710可为逻辑芯片。第二连接线结构715可在第二半导体层711与第一连接线结构620之间。例如，第二半导体层711可包括半导体材料。第二连接线结构715可在第二半导体层711的第一表面711a上。第二连接线结构715可包括第二焊盘721、第三焊盘722、第四焊盘723、第四层间电介质层724、第三缓冲电介质层726、第五层间电介质层727、第四缓冲电介质层728、第六层间电介质层729、第五缓冲电介质层730、第七层间电介质层731、第六缓冲电介质层732、第一过孔733和第二过孔734。第二半导体层711可在其第一表面711a上按次序设置第四层间电介质层724、第三缓冲电介质层726、第五层间电介质层727、第四缓冲电介质层728、第六层间电介质层729、第五缓冲电介质层730、第七层间电介质层731和第六缓冲电介质层732。第六缓冲电介质层732可接触第三缓冲电介质层625。例如，第三缓冲电介质层726、第四缓冲电介质层728、第五缓冲电介质层730和第六缓冲电介质层732可包括氮化硅层或碳氮化硅层。例如，第四层间电介质层724、第五层间电介质层727、第六层间电介质层729和第七层间电介质层731可包括氧化硅层或PETEOS层。
第二焊盘721可在第二半导体层711的第一表面711a上。第二焊盘721可由第四层间电介质层724覆盖。例如，第二焊盘721可包括铜(Cu)、铝(Al)、镍(Ni)、钨(W)、钛(Ti)或钽(Ta)。第一过孔733可在第四层间电介质层724中。第一过孔733可接触第二焊盘721。例如，第一过孔733可包括铜(Cu)、铝(Al)、镍(Ni)、钨(W)、钛(Ti)或钽(Ta)。第三焊盘722可在第五层间电介质层727中。第三焊盘722可接触第一过孔733。例如，第三焊盘722可包括铜(Cu)、铝(Al)、镍(Ni)、钨(W)、钛(Ti)或钽(Ta)。第二过孔734可在第五层间电介质层727中。第二过孔734可接触第三焊盘722。例如，第二过孔734可包括铜(Cu)、铝(Al)、镍(Ni)、钨(W)、钛(Ti)或钽(Ta)。
第四焊盘723可在第四缓冲电介质层728和第六层间电介质层729中。例如，第四焊盘723中的每一个可在穿过第四缓冲电介质层728和第六层间电介质层729的第二沟槽TH2中。第四焊盘723可包括第二金属势垒层723a和第二金属焊盘723b。第二金属势垒层723a可在第二沟槽TH2的底表面(向上或者如图7所示的顶表面)和侧壁上。第二金属势垒层723a可接触第二过孔734。第二金属焊盘723b可覆盖第二金属势垒层723a的顶表面或内表面，并且可位于第二沟槽TH2中。第二金属焊盘723b可具有与第六层间电介质层729的一个表面共面的第一表面723c。第二金属势垒层723a可包围第二金属焊盘723b的侧壁和第二表面，其中第二表面面对第一表面723c。例如，第二金属势垒层723a可包括钛(Ti)或钽(Ta)。例如，第二金属焊盘723b可包括铜(Cu)、铝(Al)、镍(Ni)或钨(W)。
第一互连结构ICS1可在第一连接线结构620和第二连接线结构715中。例如，第一互连结构ICS1中的每一个可在第一焊盘626与第四焊盘723之间。第一互连结构ICS1可接触第一金属焊盘627的第一表面627a和第二金属焊盘723b的第一表面723c。第一互连结构ICS1可穿过第五缓冲电介质层730、第七层间电介质层731、第六缓冲电介质层732、第二缓冲电介质层623、第二层间电介质层624和第三缓冲电介质层625。第一互连结构ICS1可包括第一焊盘连接器740和第一连接金属势垒层750。第一连接金属势垒层750可包围第一焊盘连接器740。第一焊盘连接器740可对应于图1和图2所示的焊盘连接器210，并且第一连接金属势垒层750可对应于图1和图2所示的连接金属势垒层220。例如，第一焊盘连接器740可包括铜(Cu)和锡(Sn)。例如，第一连接金属势垒层750可包括钛或钽。
模制层650可在封装件衬底500上。模制层650可覆盖第一半导体层611的侧壁、粘合剂层601的侧壁和第一连接线结构620的侧壁。模制层650可接触第二连接线结构715的一个表面。例如，模制层650可接触第二连接线结构715的第六缓冲电介质层732。模制层650可包括诸如环氧模塑料的电介质聚合物。
一起参照图6、图7和图8，第三连接线结构810可在第二半导体层711的第二表面711b上。第二半导体层711的第二表面711b可面对第二半导体层711的第一表面711a。集成装置可在第二半导体层711的第二表面711b上。例如，晶体管的栅电极可在第二半导体层711的第二表面711b上。晶体管的栅电极可由第三连接线结构810覆盖。
第三连接线结构810可包括第八至第十一层间电介质层821、823、825和827、第七至第十缓冲电介质层822、824、826和828、第一穿通过孔829、第三过孔831以及第五焊盘830和第六焊盘840。第二半导体层711可在其第二表面711b上按次序设置第八层间电介质层821、第七缓冲电介质层822、第九层间电介质层823、第八缓冲电介质层824、第十层间电介质层825、第九缓冲电介质层826、第十一层间电介质层827以及第十缓冲电介质层828。例如，第八至第十一层间电介质层821、823、825和827可包括氧化硅层或PETOS层。例如，第七至第十缓冲电介质层822、824、826和828可包括氮化硅层或碳氮化硅层。
第一穿通过孔829可穿过第八层间电介质层821和第二半导体层711。第一穿通过孔829可将第五焊盘830和第二焊盘721彼此连接。例如，第一穿通过孔829可包括导电材料。第五焊盘830可在第九层间电介质层823中。第五焊盘830可穿过第七缓冲电介质层822，并且连接第一穿通过孔829。例如，第五焊盘830可包括铜(Cu)、铝(Al)、镍(Ni)、钨(W)、钛(Ti)或钽(Ta)。第三过孔831可在第九层间电介质层823中。第三过孔831可接触第五焊盘830。例如，第三过孔831可包括铜(Cu)、铝(Al)、镍(Ni)、钨(W)、钛(Ti)或钽(Ta)。
第六焊盘840可在第八缓冲电介质层824和第十层间电介质层825中。例如，第六焊盘840中的每一个可在穿过第八缓冲电介质层824和第十层间电介质层825的第三沟槽TH3中。第六焊盘840可包括第三金属焊盘843和第三金属势垒层845。第三金属势垒层845可在第三沟槽TH3的底表面和侧壁上。第三金属势垒层845可接触第三过孔831。第三金属焊盘843可覆盖第三金属势垒层845的顶表面，并且可位于第三沟槽TH3中。第三金属焊盘843可具有与第十层间电介质层825的一个表面共面的第一表面843a。第三金属势垒层845可包围第三金属焊盘843的侧壁和第二表面，其中第二表面面对第一表面843a。例如，第三金属势垒层845可包括钛(Ti)或钽(Ta)。例如，第三金属焊盘843可包括铜(Cu)、铝(Al)、镍(Ni)或钨(W)。
第三半导体芯片900可在第二半导体芯片710上。第三半导体芯片900可包括第四连接线结构910和第三半导体层930。例如，第三半导体芯片900可为图像传感器芯片。第四连接线结构910可在第三半导体层930与第三连接线结构810之间。第四连接线结构910可在第三半导体层930的第一表面930a上。第四连接线结构910可包括第十二至第十五层间电介质层911、913、915和917、第十一至第十四缓冲电介质层912、914、916和918、第四过孔920以及第七焊盘919和第八焊盘938。第三半导体层930可在其第一表面930a上按次序设置第十二层间电介质层911、第十一缓冲电介质层912、第十三层间电介质层913、第十二缓冲电介质层914、第十四层间电介质层915、第十三缓冲电介质层916、第十五层间电介质层917和第十四缓冲电介质层918。第十四缓冲电介质层918和第十缓冲电介质层828可彼此接触。例如，第十二至第十五层间电介质层911、913、915和917可包括氧化硅层或PETOS层。例如，第十一至第十四缓冲电介质层912、914、916和918可包括氮化硅层或碳氮化硅层。
第七焊盘919可在第十三层间电介质层913中。第七焊盘919可穿过第十一缓冲电介质层912，并且与第四过孔920连接。例如，第七焊盘919可包括铜(Cu)、铝(Al)、镍(Ni)、钨(W)、钛(Ti)或钽(Ta)。第四过孔920可布置在第十三层间电介质层913中。例如，第四过孔920可包括铜(Cu)、铝(Al)、镍(Ni)、钨(W)、钛(Ti)或钽(Ta)。第八焊盘938可在第十二缓冲电介质层914和第十四层间电介质层915中。例如，第八焊盘938中的每一个可在穿过第十二缓冲电介质层914和第十四层间电介质层915的第四沟槽TH4中。第八焊盘938可包括第四金属焊盘933和第四金属势垒层935。第四金属势垒层935可在第四沟槽TH4的底表面(例如，向上或者图8中的顶表面)和侧壁上。第四金属势垒层935可接触第四过孔920。第四金属焊盘933可覆盖第四金属势垒层935的顶表面，并且可位于第四沟槽TH4中。第四金属焊盘933可具有与第十四层间电介质层915的一个表面共面的第一表面933a。第四金属势垒层935可包围第四金属焊盘933的侧壁和第二表面，其中第二表面面对第一表面933a。第四金属势垒层935可包括钛(Ti)或钽(Ta)。例如，第四金属焊盘933可包括铜(Cu)、铝(Al)、镍(Ni)或钨(W)。
第二互连结构ICS2可在第三连接线结构810和第四连接线结构910中。例如，第二互连结构ICS2中的每一个可在第六焊盘840与第八焊盘938之间。第二互连结构ICS2可接触第三金属焊盘843的第一表面843a以及第四金属焊盘933的第一表面933a。第二互连结构ICS2可穿过第十三缓冲电介质层916、第十五层间电介质层917、第十四缓冲电介质层918、第十缓冲电介质层828、第十一层间电介质层827和第九缓冲电介质层826。第二互连结构ICS2可包括第二焊盘连接器940和第二连接金属势垒层950。第二连接金属势垒层950可包围第二焊盘连接器940。第二焊盘连接器940可对应于图1和图2所示的焊盘连接器210，第二连接金属势垒层950可对应于图1和图2所示的连接金属势垒层220。例如，第二焊盘连接器940可包括铜(Cu)和锡(Sn)。例如，第二连接金属势垒层950可包括钛或钽。
可在第三半导体层930的第一表面930a上设有晶体管的多个部分。例如，晶体管的栅电极可在第三半导体层930的第一表面930a上。光电转换装置PD可在第三半导体层930中。光电转换装置PD可具有与第三半导体层930的导电类型不同的导电类型。第三半导体层930可包括半导体材料。第二穿通过孔941可在第三半导体层930中。第二穿通过孔941可穿过第三半导体层930并且可与第七焊盘919连接。例如，第二穿通过孔941可包括导电材料。滤色器CF可在第三半导体层930的第二表面930b上，第二表面930b面对第一表面930a。滤色器CF可对应于光电转换装置PD。微透镜MR可在滤色器CF上。微透镜MR可对应于滤色器CF。第二键合焊盘942可在第三半导体层930的第二表面930b上。第二键合焊盘942可在第三半导体层930周围间隔开特定间距。键合线943可在第一键合焊盘510与第二键合焊盘942之间。键合线943可将第三半导体芯片900与封装件衬底500彼此电连接。
可在封装件衬底500上设有支承透镜982的支架980。支架980可包括工程塑料。透镜982可在支架980上，面对第三半导体芯片900。透镜982可包括诸如玻璃的透明材料，以允许光通过。
图9A至图9E示出了根据一些示例实施例的半导体装置的制造方法中的各阶段的剖视图。
参照图9A，第一焊盘120可形成在第一电介质层110中。第一焊盘120的形成可包括：在第一电介质层10中形成第一沟槽T1；形成第一势垒层以覆盖第一电介质层110的顶表面以及覆盖第一沟槽T的底表面和侧壁；形成第一金属层以覆盖第一势垒层，并且填充第一沟槽T；以及执行平坦化工艺以研磨第一金属层和第一势垒层，以暴露出第一电介质层110的顶表面。第一焊盘120可包括第一金属势垒层123和第一金属焊盘121。第一金属势垒层123可保形地覆盖第一沟槽T1的底表面和侧壁(例如，内表面)。第一金属焊盘121可完全填充第一沟槽T1(例如，第一沟槽T1的其余部分)。
第一缓冲电介质层150、第三电介质层160和第二缓冲电介质层170可按次序形成在第一电介质层110上。第一缓冲电介质层150可覆盖第一电介质层110的顶表面和第一焊盘120的顶表面。第三电介质层160可覆盖第一缓冲电介质层150的顶表面，并且第二缓冲电介质层170可覆盖第三电介质层160的顶表面。
参照图9B，第三沟槽T3可形成在第一缓冲电介质层150、第三电介质层160和第二缓冲电介质层170中。可通过图案化第二缓冲电介质层170、第三电介质层160和第一缓冲电介质层150形成第三沟槽T3，以暴露出第一焊盘120的顶表面。第三沟槽T3的宽度可小于第一沟槽T1的宽度。
第二势垒层301、第二金属层303和第三金属层305可形成在第三沟槽T3中。第二势垒层301可保形地覆盖第二缓冲电介质层170的顶表面，并且还保形地覆盖第三沟槽T3的底表面和侧壁。第二金属层303可保形地覆盖第二势垒层301的顶表面。第三金属层305可覆盖第二金属层303，并且可填充第三沟槽T3。可执行电镀工艺以形成第二金属层303和第三金属层305。例如，第二势垒层301可包括钛或钽。例如，第二金属层303可包括锡(Sn)。例如，第三金属层305可包括铜(Cu)、铝(Al)、镍(Ni)或钨(W)。
参照图9C，可蚀刻第三金属层305以形成第一键合金属焊盘311。可通过在第三金属层305上执行的平坦化工艺形成第一键合金属焊盘311，在平坦化工艺中，将第三金属层305蚀刻以暴露出第二金属层303的顶表面。第二金属层303可用作蚀刻停止层。平坦化工艺可包括化学机械抛光工艺或湿蚀刻工艺。当执行湿蚀刻工艺作为平坦化工艺时，可使用氢氟酸(HF)。
可研磨第二金属层303以形成第二键合金属焊盘312。可通过研磨第二金属层303以暴露出第二势垒层301的顶表面形成第二键合金属焊盘312。当使用研磨剂来研磨第二金属层303时，研磨剂可相对于第一键合金属焊盘311具有蚀刻选择性。第一键合金属焊盘311的邻近于第二键合金属焊盘312的边缘顶表面可被蚀刻，并且其远离第二键合金属焊盘312的中心顶表面可不被蚀刻。因此，第一键合金属焊盘311可具有凸曲面。例如，可执行化学机械抛光工艺以研磨第二金属层303。
可研磨第二势垒层301以形成第一连接势垒层313。可通过研磨第二势垒层301以暴露出第二缓冲电介质层170的顶表面形成第一连接势垒层313。当使用研磨剂来研磨第二势垒层301时，研磨剂可相对于第一键合金属焊盘311和第二键合金属焊盘312具有蚀刻选择性。例如，可执行化学机械抛光工艺以研磨第二势垒层301。第一连接势垒层313可接触第一金属焊盘121的顶表面。第一连接势垒层313的形成可获得第一焊盘结构1000。
参照图9D，可执行与上面讨论的相同的工艺，以形成第二焊盘结构2000。第二沟槽T2可形成在第二电介质层130中，并且第二金属势垒层145和第二金属焊盘141可形成在第二沟槽T2中。第二金属势垒层145可保形地覆盖第二沟槽T2的底表面和侧壁。第二金属焊盘141可覆盖第二金属势垒层145，并且可填充第二沟槽T2。第三缓冲电介质层180、第四电介质层190和第四缓冲电介质层200可按次序形成在第二电介质层130的顶表面上。可通过图案化第四缓冲电介质层200、第四电介质层190和第三缓冲电介质层180形成第四沟槽T4。第四沟槽T4可暴露出第二金属焊盘141的顶表面。第四沟槽T4可形成为宽度小于第二沟槽T2的宽度。
第一连接势垒层316、第四键合金属焊盘315和第三键合金属焊盘314可按次序形成在第四沟槽T4中。第一连接势垒层316可保形地覆盖第四沟槽T4的底表面和侧壁。第一连接势垒层316可接触第二金属焊盘141的顶表面。第一连接势垒层316可暴露出第四缓冲电介质层200的顶表面。例如，第一连接势垒层316可包括钛或钽。第四键合金属焊盘315可保形地覆盖第一连接势垒层316的顶表面。第四键合金属焊盘315可暴露出第四缓冲电介质层200的顶表面。例如，第四键合金属焊盘315可包括锡(Sn)。第三键合金属焊盘314可覆盖第四键合金属焊盘315的顶表面，并且可填充第四沟槽T4。第三键合金属焊盘314可暴露出第四缓冲电介质层200的顶表面。第三键合金属焊盘314可具有凸弯曲顶表面。例如，第三键合金属焊盘314可包括铜(Cu)、铝(Al)、镍(Ni)或钨(W)。
参照图9E，第二焊盘结构2000可堆叠在第一焊盘结构1000上。例如，第二焊盘结构2000的第一连接势垒层316和第三键合金属焊盘314和第四键合金属焊盘315可在第一焊盘结构1000的第一连接势垒层313和第一键合金属焊盘311和第二键合金属焊盘312上。第一连接势垒层313和第一连接势垒层316可彼此对称布置，并且第二键合金属焊盘312和第四键合金属焊盘315可彼此对称布置。第一键合金属焊盘311和第三键合金属焊盘314可彼此对称布置。因为第一键合金属焊盘311和第三键合金属焊盘314中的每一个具有凸弯曲顶表面，所以当第一键合金属焊盘311和第三键合金属焊盘314彼此接触时，可在第二缓冲电介质层170与第四缓冲电介质层200之间产生间隙G。因此，第二缓冲电介质层170和第四缓冲电介质层200可彼此间隔开。
可对图9E中堆叠在彼此顶部的第一焊盘结构1000和第二焊盘结构2000执行退火工艺。退火工艺可允许第一连接势垒层313和第一连接势垒层316彼此组合以形成连接金属势垒层220。退火工艺可允许第一键合金属焊盘311、第二键合金属焊盘312、第三键合金属焊盘314和第四键合金属焊盘315彼此组合，以形成焊盘连接器210。可在约250℃至约350℃执行退火工艺。连接金属势垒层220可包围焊盘连接器210。焊盘连接器210可为当第一键合金属焊盘至第四键合金属焊盘311、312、314和315彼此结合时形成的金属间化合物(IMC)。当第一键合金属焊盘311和第三键合金属焊盘314包括铜时，铜可具有面心立方体(FCC)点阵结构。当第二键合金属焊盘312和第四键合金属焊盘315包括锡时，锡可具有四方向点阵结构或钻石立方点阵结构。退火工艺可将铜原子引入锡点阵结构中，并且还将锡原子引入铜点阵结构中，因此，铜和锡点阵结构可稳定地再排列。因此，其中铜和锡彼此结合的焊盘连接器210的体积可小于还未经历退火工艺的第一键合金属焊盘311、第二键合金属焊盘312、第三键合金属焊盘314和第四键合金属焊盘315的体积之和。焊盘连接器210的体积的减小可消除第二缓冲电介质层170与第四缓冲电介质层200之间的间隙G，结果第二缓冲电介质层170和第四缓冲电介质层200可彼此接触，如图1和图2所示。
在实施中，退火工艺可导致包括铜锡化合物的焊盘连接器210的体积减小，并且可消除第二缓冲电介质层170与第四缓冲电介质层200之间的间隙G，以增加它们之间的粘合力，其可导致半导体装置的产量提高。
另外，如图9E所示，包括锡的第二键合金属焊盘312(或第四键合金属焊盘315)可在包括铜的第一键合金属焊盘311(或第三键合金属焊盘314)与包括钛或钽的第一连接势垒层313(或第一连接势垒层316)之间，并且可避免焊盘连接器210与连接金属势垒层220之间的电偶腐蚀。
图10A至图10C示出了根据一些示例实施例的半导体封装件的制造方法中的各阶段的剖视图。
参照图10A，可制备第二半导体芯片710和第三半导体芯片900。第二半导体芯片710可包括第二半导体层711和第三连接线结构810。第三连接线结构810可在第二半导体层711的第二表面711b上，其中第二表面711b面对第二半导体层711的第一表面711a。第三连接线结构810可包括第八至第十一层间电介质层821、823、825和827、第七至第十缓冲电介质层822、824、826和828、第一穿通过孔829、第三过孔831、第五焊盘830和第六焊盘840、第一连接势垒层2、第一键合金属焊盘4和第二键合金属焊盘6。第八层间电介质层821可布置在第二半导体层711的第二表面711b上。第一穿通过孔829可穿过第八层间电介质层821和第二半导体层711的一部分。第七缓冲电介质层822和第九层间电介质层823可按次序形成在第八层间电介质层821上。第五焊盘830和第三过孔831可形成在第七缓冲电介质层822和第九层间电介质层823中。第五焊盘830可接触第一穿通过孔829，并且第三过孔831可接触第五焊盘830。
第八缓冲电介质层824和第十层间电介质层825可按次序形成在第九层间电介质层823上。第六焊盘840可形成为穿过第八缓冲电介质层824和第十层间电介质层825。第六焊盘840可形成为接触第三过孔831。第九缓冲电介质层826、第十一层间电介质层827和第十缓冲电介质层828可按次序形成在第十层间电介质层825上。可通过图案化第九缓冲电介质层826、第十一层间电介质层827和第十缓冲电介质层828形成第一沟槽T1。第一沟槽T1可暴露出第六焊盘840。第一连接势垒层2、第一键合金属焊盘4和第二键合金属焊盘6可形成在第一沟槽T1中。可通过在第一沟槽T1中按次序形成第一金属层、第二金属层和第三金属层并随后执行平坦化工艺来形成第一连接势垒层2、第一键合金属焊盘4和第二键合金属焊盘6。平坦化工艺可允许第二键合金属焊盘6具有凸弯曲顶表面。例如，第一连接势垒层2可包括钛(Ti)或钽(Ta)。例如，第一键合金属焊盘4可包括锡(Sn)。例如，第二键合金属焊盘6可包括铜(Cu)、铝(Al)、镍(Ni)或钨(W)。
第三半导体芯片900可包括第三半导体层930和第四连接线结构910。光电转换装置PD可在第三半导体层930中。可通过离子植入工艺形成光电转换装置PD，其中第三半导体层930掺有杂质。滤色器CF可形成在第三半导体层930的第二表面930b上，并且微透镜MR可形成在滤色器CF上。第二键合焊盘942可形成在第三半导体层930的第二表面930b上。载体粘合剂层960可形成在第三半导体层930的第二表面930b上。载体粘合剂层960可覆盖滤色器CF和微透镜MR。载体衬底970可附着于载体粘合剂层960。
第四连接线结构910可形成在第三半导体层930的第一表面930a上。第四连接线结构910可包括第十二至第十五层间电介质层911、913、915和917、第十一至第十四缓冲电介质层912、914、916和918、第四过孔920、第七焊盘919和第八焊盘938、第二连接势垒层12、第三键合金属焊盘14和第四键合金属焊盘16。第十二层间电介质层911可形成在第三半导体层930的第一表面930a上。第二穿通过孔941可形成在第三半导体层930和第十二层间电介质层911中。第二穿通过孔941可接触第二键合焊盘942。第十一缓冲电介质层912和第十三层间电介质层913可形成在第十二层间电介质层911上。第七焊盘919可形成在第十一缓冲电介质层912和第十三层间电介质层913中。第七焊盘919可接触第二穿通过孔941。第四过孔920可形成在第十三层间电介质层913中。第四过孔920可接触第七焊盘919。
第十二缓冲电介质层914和第十四层间电介质层915可形成在第十三层间电介质层913上。第八焊盘938可穿过第十二缓冲电介质层914和第十四层间电介质层915。第八焊盘938可接触第四过孔920。第十三缓冲电介质层916、第十五层间电介质层917和第十四缓冲电介质层918可形成在第十四层间电介质层915上。可通过图案化第十三缓冲电介质层916、第十五层间电介质层917和第十四缓冲电介质层918形成第二沟槽T2。第二沟槽T2可暴露出第八焊盘938。第二连接势垒层12、第三键合金属焊盘14和第四键合金属焊盘16可形成在第二沟槽T2中。可通过在第二沟槽T2中按次序形成第四金属层、第五金属层和第六金属层并随后执行平坦化工艺来形成第二连接势垒层12、第三键合金属焊盘14和第四键合金属焊盘16。平坦化工艺可允许第四键合金属焊盘16具有凸弯曲顶表面。例如，第二连接势垒层12可包括钛(Ti)或钽(Ta)。例如，第三键合金属焊盘14可包括锡(Sn)。例如，第四键合金属焊盘16可包括铜(Cu)、铝(Al)、镍(Ni)或钨(W)。
参照图10B，第二半导体芯片710和第三半导体芯片900可彼此组合。例如，第二半导体芯片710与第三半导体芯片900的组合可包括将第二半导体芯片710的第一连接势垒层2、第一键合金属焊盘4和第二键合金属焊盘6布置在第三半导体芯片900的第二连接势垒层12、第三键合金属焊盘14和第四键合金属焊盘16上，并且执行退火工艺，以将第一连接势垒层2和第二连接势垒层12和第一至第四键合金属焊盘4、6、14和16彼此组合，以形成第二互连结构ICS2。可在约250℃至约350℃执行退火工艺。第二互连结构ICS2可包括第二焊盘连接器940和第二连接金属势垒层950。第十缓冲电介质层828和第十四缓冲电介质层918可彼此接触。
参照图10C，可对第二半导体层711的第一表面711a执行研磨工艺。研磨工艺可继续进行，直至暴露出第一穿通过孔829为止。因此，第二半导体层711的厚度可变小。
第二连接线结构715可形成在第二半导体层711的第一表面711a上。第二半导体芯片710还可包括第二连接线结构715。第二连接线结构715可包括第二至第四焊盘721、722和723、第四层间电介质层724、第三缓冲电介质层726、第五层间电介质层727、第四缓冲电介质层728、第六层间电介质层729、第五缓冲电介质层730、第七层间电介质层731、第六缓冲电介质层732、第一过孔733、第二过孔734、第三连接势垒层22、第五键合金属焊盘24和第六键合金属焊盘26。第二焊盘721可形成在第二半导体层711的第一表面711a上。第二焊盘721可接触第一穿通过孔829。第四层间电介质层724可形成在第二半导体层711的第一表面711a上。第四层间电介质层724可覆盖第二焊盘721。第一过孔733可形成在第四层间电介质层724中。第一过孔733可接触第二焊盘721。第三缓冲电介质层726和第五层间电介质层727可按次序形成在第四层间电介质层724上。第三焊盘722可形成在第三缓冲电介质层726和第五层间电介质层727中，第二过孔734可形成在第五层间电介质层727中并且与第三焊盘722接触。第四缓冲电介质层728和第六层间电介质层729可按次序形成在第五层间电介质层727上。第四焊盘723可形成为穿过第四缓冲电介质层728和第六层间电介质层729。第四焊盘723可接触第二过孔734。
第五缓冲电介质层730、第七层间电介质层731和第六缓冲电介质层732可按次序形成在第六层间电介质层729上。可通过图案化第五缓冲电介质层730、第七层间电介质层731和第六缓冲电介质层732形成第三沟槽T3。第三沟槽T3可暴露出第四焊盘723。第三连接势垒层22、第五键合金属焊盘24和第六键合金属焊盘26可形成在第三沟槽T3中。可通过在第三沟槽T3中按次序形成第七金属层、第八金属层和第九金属层并且随后执行平坦化工艺来形成第三连接势垒层22、第五键合金属焊盘24和第六键合金属焊盘26。平坦化工艺可允许第六键合金属焊盘26具有凸弯曲顶表面。例如，第三连接势垒层22可包括钛(Ti)或钽(Ta)。例如，第五键合金属焊盘24可包括锡(Sn)。例如，第六键合金属焊盘26可包括铜(Cu)、铝(Al)、镍(Ni)或钨(W)。
可制备第一半导体芯片600。第一半导体芯片600可包括第一半导体层611和第一连接线结构620。第一连接线结构620可形成在第一半导体层611的第一表面611a上。第一连接线结构620可包括第一缓冲电介质层621、第一层间电介质层622、第二缓冲电介质层623、第二层间电介质层624、第三缓冲电介质层625、第一焊盘626、第四连接势垒层32、第七键合金属焊盘34和第八键合金属焊盘36。第一缓冲电介质层621和第一层间电介质层622可按次序形成在第一半导体层611的第一表面611a上。第一焊盘626可穿过第一缓冲电介质层621和第一层间电介质层622。第一焊盘626可接触第一半导体层611的第一表面611a。第二缓冲电介质层623、第二层间电介质层624和第三缓冲电介质层625可按次序形成在第一层间电介质层622上。可通过图案化第二缓冲电介质层623、第二层间电介质层624和第三缓冲电介质层625形成第四沟槽T4。第四沟槽T4可暴露出第一焊盘626。第四连接势垒层32、第七键合金属焊盘34和第八键合金属焊盘36可形成在第四沟槽T4中。可通过在第四沟槽T4中按次序形成第十金属层、第十一金属层和第十二金属层并且随后执行平坦化工艺来形成第四连接势垒层32、第七键合金属焊盘34和第八键合金属焊盘36。平坦化工艺可允许第八键合金属焊盘36具有凸弯曲顶表面。例如，第四连接势垒层32可包括钛(Ti)或钽(Ta)。例如，第七键合金属焊盘34可包括锡(Sn)。例如，第八键合金属焊盘36可包括铜(Cu)、铝(Al)、镍(Ni)或钨(W)。
返回参照图6，第二半导体芯片710和第一半导体芯片600可彼此组合。例如，第二半导体芯片710与第一半导体芯片600的组合可包括：将第二半导体芯片710的第三连接势垒层22、第五键合金属焊盘24和第六键合金属焊盘26布置在第一半导体芯片600的第四连接势垒层32、第七键合金属焊盘34和第八键合金属焊盘36上；以及执行退火工艺以将第三连接势垒层22和第四连接势垒层32和第五至第八键合金属焊盘24、26、34和36彼此组合，以形成第一互连结构ICS1。可在约250℃至约350℃执行退火工艺。第一互连结构ICS1可包括第一焊盘连接器740和第一连接金属势垒层750。第三缓冲电介质层625和第六缓冲电介质层732可彼此接触。
可在封装件衬底500上设置其中第一半导体芯片600、第二半导体芯片710和第三半导体芯片900彼此结合的芯片结构。粘合剂层601可设置在第一半导体芯片600的第二表面上，第二表面面对第一表面611a，并且粘合剂层601可用于将芯片结构安装在封装件衬底500上。模制层650可形成在封装件衬底500上。模制层650可覆盖第一半导体芯片600的侧壁。封装件衬底500可包括形成在其顶表面上的第一键合焊盘510和形成在其相对的底表面上的凸块520。可去除载体粘合剂层960和载体衬底970以暴露出微透镜MR和第二键合焊盘942。键合线943可形成在第一键合焊盘510与第二键合焊盘942之间。支架980可设置在封装件衬底500上。支架980可支承透镜982。
通过总结和回顾的方式，体积不足的焊盘连接器可导致焊盘中的空隙。然而，增大焊盘连接器的体积可导致电介质层之间的间隙。
根据一些示例实施例，退火工艺可导致包括铜锡化合物的焊盘连接器的体积减小，并且体积减小可消除缓冲电介质层之间的间隙。因此，缓冲电介质层之间可具有增大的粘合力，因此可提高半导体装置的产量。
另外，包括锡的键合金属焊盘可形成在包括铜的键合金属焊盘与包括钛或钽的连接势垒层之间，并且可避免连接金属势垒层与通过含铜键合金属焊盘与含锡键合金属焊盘的组合形成的焊盘连接器之间的电偶腐蚀。
一个或多个实施例可提供一种可靠性提高的半导体装置。
一个或多个实施例可提供一种可靠性提高的半导体封装件。
本文已公开了示例实施例，虽然采用了特定术语，但是仅按照一般和描述性含义而非针对限制的目的使用和解释它们。在一些情况下，如本领域普通技术人员之一应该清楚的，除非另有说明，否则随着本申请的提交，结合特定实施例描述的特征、特性和/或元件可单独使用或者与结合其它实施例描述的特征、特性和/或元件联合使用。因此，本领域技术人员应该理解，在不脱离权利要求阐述的本发明的精神和范围的情况下，可作出各种形式和细节上的改变。

Claims (25)

1.一种半导体装置，包括：
第一缓冲电介质层，其位于第一电介质层上；
按次序布置在所述第一缓冲电介质层上的第二电介质层和第二缓冲电介质层，所述第二缓冲电介质层与所述第一缓冲电介质层接触；以及
焊盘互连结构，其穿过所述第一缓冲电介质层和所述第二缓冲电介质层，
其中，所述焊盘互连结构包括铜和锡。
2.根据权利要求1所述的半导体装置，其中：
所述焊盘互连结构包括焊盘连接器和包围所述焊盘连接器的连接金属势垒层，并且
所述焊盘连接器包括铜和锡。
3.根据权利要求2所述的半导体装置，其中，
所述焊盘互连结构中包含的锡的量在从所述焊盘连接器的外部向所述焊盘连接器的中心部分的方向上减小，并且
所述焊盘互连结构中包含的铜的量在从所述外部向所述中心部分的方向上增大。
4.根据权利要求1所述的半导体装置，其中：
所述焊盘互连结构包括焊盘连接器和包围所述焊盘连接器的连接金属势垒层，并且
所述焊盘连接器的粒度在从所述焊盘连接器的外部向所述焊盘连接器的中心部分的方向上增大。
5.根据权利要求1所述的半导体装置，其中：
所述焊盘互连结构包括焊盘连接器和包围所述焊盘连接器的连接金属势垒层，
所述焊盘连接器包括：
中心部分；
包围所述中心部分的第一中间部分；
包围所述第一中间部分的第二中间部分；以及
包围所述第二中间部分的外部，并且
所述连接金属势垒层包围所述焊盘连接器的外部。
6.根据权利要求5所述的半导体装置，其中，
所述第一中间部分包括Cu3Sn，并且
所述第二中间部分包括Cu6Sn5。
7.根据权利要求5所述的半导体装置，其中，
所述中心部分中包含的铜的量大于所述外部中包含的铜的量，并且
所述中心部分中包含的锡的量小于所述外部中包含的锡的量。
8.根据权利要求1所述的半导体装置，还包括：
第一焊盘，其位于所述第一电介质层中的第一沟槽中；以及
第二焊盘，其位于所述第二电介质层中的第二沟槽中，
其中，所述第一焊盘和所述第二焊盘与所述焊盘互连结构接触。
9.根据权利要求8所述的半导体装置，其中：
所述第一焊盘包括：
第一金属焊盘，其位于所述第一沟槽中；以及
第一金属势垒层，其位于所述第一沟槽中并且位于所述第一金属焊盘与所述第一电介质层之间，并且
所述第二焊盘包括：
第二金属焊盘，其位于所述第二沟槽中；以及
第二金属势垒层，其位于所述第二沟槽中并且位于所述第二金属焊盘与所述第二电介质层之间。
10.根据权利要求1所述的半导体装置，其中：
所述焊盘互连结构包括焊盘连接器和包围所述焊盘连接器的连接金属势垒层，
所述半导体装置还包括：
第三电介质层，其位于所述第一电介质层与所述第一缓冲电介质层之间；以及
第四电介质层，其位于所述第二电介质层与所述第二缓冲电介质层之间，所述焊盘连接器包括：
第一区段，其穿过所述第三电介质层和所述第一缓冲电介质层；以及
第二区段，其穿过所述第四电介质层和所述第二缓冲电介质层，并且
所述第一区段和所述第二区段彼此线性对称。
11.根据权利要求1所述的半导体装置，其中：
所述焊盘互连结构包括焊盘连接器和包围所述焊盘连接器的连接金属势垒层，
所述半导体装置还包括：
第三电介质层，其位于所述第一电介质层与所述第一缓冲电介质层之间；以及
第四电介质层，其位于所述第二电介质层与所述第二缓冲电介质层之间，
所述焊盘连接器包括：
第一区段，其穿过所述第三电介质层和所述第一缓冲电介质层；以及
第二区段，其穿过所述第四电介质层和所述第二缓冲电介质层，并且
所述第一区段和所述第二区段在反方向上关于划分所述第一区段和所述第二区段的平面彼此偏移。
12.根据权利要求1所述的半导体装置，其中，
所述第一电介质层和所述第二电介质层各自包括氧化硅层或PETOS层，并且
所述第一缓冲电介质层和所述第二缓冲电介质层各自包括氧化硅层或碳氮化硅层。
13.一种半导体装置，包括：
第一电介质层；
第二电介质层，其位于所述第一电介质层上；以及
焊盘连接器，其位于所述第一电介质层与所述第二电介质层之间，
其中，所述焊盘连接器包括中心部分和包围所述中心部分的外部，并且
其中，所述焊盘连接器的粒度在从所述外部向所述中心部分的方向上增加。
14.根据权利要求13所述的半导体装置，其中：
所述焊盘连接器包括锡和铜，
所述焊盘连接器中包含的铜的量在从所述外部向所述中心部分的方向上增加，并且
所述焊盘连接器中包含的锡的量在从所述外部向所述中心部分的方向上减小。
15.根据权利要求13所述的半导体装置，其中：
所述焊盘连接器包括：
包围所述中心部分的第一中间部分；以及
包围所述第一中间部分的第二中间部分，并且
所述外部包围所述第二中间部分。
16.根据权利要求15所述的半导体装置，其中：
所述第一中间部分包括Cu3Sn，并且
所述第二中间部分包括Cu6Sn5。
17.根据权利要求15所述的半导体装置，其中：
所述外部的粒度小于所述第二中间部分的粒度，
所述第二中间部分的粒度小于所述第一中间部分的粒度，并且
所述第一中间部分的粒度小于所述中心部分的粒度。
18.根据权利要求13所述的半导体装置，还包括包围所述焊盘连接器的连接金属势垒层，
其中，所述连接金属势垒层包括钽。
19.根据权利要求13所述的半导体装置，还包括：
第一焊盘，其位于所述第一电介质层中；以及
第二焊盘，其位于所述第二电介质层中，
其中，所述第一焊盘包括：
第一金属焊盘，其位于所述第一电介质层中，并且具有与所述焊盘连接器接触的第一表面；以及
第一金属势垒层，其覆盖所述第一金属焊盘的第二表面和侧壁，所述第一金属焊盘的第二表面面对所述第一金属焊盘的第一表面，并且
其中，所述第二焊盘包括：
第二金属焊盘，其位于所述第二电介质层中，并且具有与所述焊盘连接器接触的第一表面；以及
第二金属势垒层，其覆盖所述第二金属焊盘的第二表面和侧壁，所述第二金属焊盘的第二表面面对所述第二金属焊盘的第一表面。
20.根据权利要求13所述的半导体装置，其中，所述焊盘连接器具有规则六边形或矩形。
21.一种半导体封装件，包括：
封装件衬底；
第一半导体芯片，其位于所述封装件衬底上，所述第一半导体芯片包括第一半导体层和堆叠在所述第一半导体层的第一表面上的第一缓冲电介质层；
第二半导体芯片，其位于所述第一半导体芯片上，所述第二半导体芯片包括第二半导体层和堆叠在所述第二半导体层的第一表面上的第二缓冲电介质层，所述第二缓冲电介质层与所述第一缓冲电介质层接触；以及
第一焊盘互连结构，其穿过所述第一缓冲电介质层和所述第二缓冲电介质层，
其中，所述第一焊盘互连结构包括铜和锡。
22.根据权利要求21所述的半导体封装件，其中，所述第一焊盘互连结构包括焊盘连接器和包围所述焊盘连接器的连接金属势垒层；
其中，所述焊盘连接器包括铜和锡，
其中，所述连接金属势垒层包括钽。
23.根据权利要求22所述的半导体封装件，其中，所述焊盘连接器中包含的锡的量在从所述焊盘连接器的外部向所述焊盘连接器的中心部分的方向上减小。
24.根据权利要求21所述的半导体封装件，其中，所述第二半导体芯片还包括布置在与所述第二半导体层的第一表面相对的第二表面上的第三缓冲电介质层，
其中，所述半导体封装件还包括：
第三半导体芯片，其位于所述第二半导体芯片上并且包括第三半导体层和堆叠在所述第三半导体层的第一表面上的第四缓冲电介质层，所述第四缓冲电介质层与所述第三缓冲电介质层接触；以及
第二焊盘互连结构，其穿过所述第三缓冲电介质层和所述第四缓冲电介质层，
其中，所述第二焊盘互连结构包括铜和锡。
25.根据权利要求24所述的半导体封装件，其中，所述第一半导体芯片是存储器芯片，
其中，所述第二半导体芯片是逻辑芯片，
其中，所述第三半导体芯片是图像传感器芯片。
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