CN110867485B - 半导体装置和电源转换装置 - Google Patents

半导体装置和电源转换装置 Download PDF

Info

Publication number
CN110867485B
CN110867485B CN201910615173.7A CN201910615173A CN110867485B CN 110867485 B CN110867485 B CN 110867485B CN 201910615173 A CN201910615173 A CN 201910615173A CN 110867485 B CN110867485 B CN 110867485B
Authority
CN
China
Prior art keywords
electroless
electrode
semiconductor device
layer
plating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910615173.7A
Other languages
English (en)
Other versions
CN110867485A (zh
Inventor
古川智康
守田俊章
川濑大助
田畑利仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Power Semiconductor Device Ltd
Original Assignee
Hitachi Power Semiconductor Device Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=69526988&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=CN110867485(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Hitachi Power Semiconductor Device Ltd filed Critical Hitachi Power Semiconductor Device Ltd
Priority to CN202311274137.1A priority Critical patent/CN117253912A/zh
Publication of CN110867485A publication Critical patent/CN110867485A/zh
Application granted granted Critical
Publication of CN110867485B publication Critical patent/CN110867485B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • H01L29/7396Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346Plating
    • H01L2224/03464Electroless plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026Bonding areas specifically adapted for layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0501Shape
    • H01L2224/05016Shape in side view
    • H01L2224/05019Shape in side view being a non conformal layer on a patterned surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05023Disposition the whole internal layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05083Three-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/05186Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • H01L2224/05559Shape in side view non conformal layer on a patterned surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29347Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32238Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/45198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/45298Fillers
    • H01L2224/45299Base material
    • H01L2224/453Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45317Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45324Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83053Bonding environment
    • H01L2224/83054Composition of the atmosphere
    • H01L2224/83065Composition of the atmosphere being reducing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/83201Compression bonding
    • H01L2224/83203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8384Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemically Coating (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Inverter Devices (AREA)

Abstract

本发明提供一种半导体装置和电源转换装置,该半导体装置具有包含化学镀Ni层的电极,且化学镀Ni层中裂纹的产生少,可靠性高。半导体装置的特征在于,具备半导体元件和形成于前述半导体元件的第一表面的第一电极,前述第一电极为包含第一化学镀Ni层的层叠结构,前述第一化学镀Ni层含有Ni(镍)和P(磷)作为组成,前述第一化学镀Ni层的P(磷)浓度为2.5wt%以上6wt%以下,且前述第一化学镀Ni层中的Ni3P的结晶化率为0%以上20%以下。

Description

半导体装置和电源转换装置
技术领域
本发明涉及半导体装置的结构及其制造方法,特别是涉及对于搭载半导体装置的电源转换装置的小型化、高可靠性化有效的技术。
背景技术
半导体装置用于系统LSI(Large Scale Integration,大规模整合)、电源转换装置、混合动力汽车等的控制装置等广泛的领域。该半导体装置中,例如电子部件的电极端子与电路基板上的电路图案的电极端子的电气接合主流是利用含有铅的“焊锡”、“焊锡合金”来进行的。
而从地球环境保护的观点出发,铅的使用受到严格限制,正在开发限制铅的使用的、用不含铅的材料进行电极等的接合。尤其是关于“高温焊锡”,尚未发现有效作为其替代品的材料。半导体装置的安装技术中必须使用“无铅的层次焊锡(鉛フリーの階層はんだ)”,因此期待代替该“高温焊锡”的材料的出现。
此外,作为逆变器等电源转换器的主要部件的电源模块需要低成本化和小型化。同样地,电源模块内的功率器件芯片也需要低成本化和小型化,需要实现功率器件芯片的高输出电流密度的新技术。如果为高输出电流密度,则功率器件每单位芯片面积的损失会增加,芯片温度会上升。因此,需要即使损失密度增加也能够高温工作的高可靠性封装安装技术。
从这样的背景出发,代替“高温焊锡”,提出了使用金属粒子与有机化合物的复合材料作为高温高可靠性的材料的使电极接合的接合材料。
例如,专利文献1中公开了“作为可针对Ni或Cu电极获得优异的接合强度的接合技术,使用含有包含氧化铜(CuO)粒子和由有机物构成的还原剂的接合材料,在还原气氛下进行接合的半导体装置”。
专利文献1记载的半导体装置是在加热还原时生成100nm以下的铜粒子,将铜粒子彼此烧结而进行接合。专利文献1记载的使用氧化铜(CuO)粒子的接合技术与以往的纳米粒子接合相比,能够改善对于Ni、Cu的接合性,可以期待作为用于Ni电极或Cu电极的接合材料。
例如,电源转换装置的逆变器中使用的IGBT(Insulated Gate BipolarTransistor,绝缘栅双极晶体管)、续流二极管等能够介由由铜烧结层形成的接合层电连接于功率半导体芯片的Ni电极的连接端子。
关于功率半导体芯片的Ni电极,例如有通过化学镀敷法使Ni层在Al金属的表面上生长的Ni电极形成方法。
此外,专利文献2中公开了“具有通过化学镀敷法形成的Ni电极的半导体装置”。专利文献2记载的半导体装置在半导体芯片上具备低磷浓度的第一层Ni镀层和高磷浓度的第二层Ni镀层,第一层的Ni镀层的磷浓度为4wt%以上且低于6wt%。在Ni镀层的磷浓度低的情况下,即使实施热处理,也难以发生因镍与磷的合金(例如Ni3P)的析出所导致的硬化,难以产生镀膜的裂纹。此外,还记载了镀膜由于热处理而整体结晶化。
此外,专利文献3中公开了“具有通过化学镀敷法形成的Ni/Au电极的半导体装置”。专利文献3记载的半导体装置通过使Ni镀层为非晶质,晶体结构不会随着温度、应力变化而变化,不会产生粒界空隙而镀膜裂纹,可靠性提高。
现有技术文献
专利文献
专利文献1:日本特许第5006081号公报
专利文献2:日本特开2015-56532号公报
专利文献3:日本特许第5669780号公报
发明内容
发明所要解决的课题
然而,本申请发明人等进行了研究,结果发现,在像专利文献2那样磷浓度为4wt%以上且低于6wt%的情况下,根据化学镀Ni浴的种类、镀膜形成后的热处理条件的不同,也容易产生裂纹。如果化学镀Ni膜中产生裂纹则有可能由于温度、应力变化而裂纹扩大,发生特性不良。
此外,如果半导体芯片的化学镀Ni电极中有裂纹,则在使用由铜烧结层形成的接合层与连接端子电连接的情况下,存在下述课题:铜会由接合层向功率半导体芯片扩散,元件的漏电流增大,元件耐压劣化,元件的特性改变。
因此,本发明的目的在于,提供一种半导体装置及其制造方法,所述半导体装置具有包含化学镀Ni层的电极,其中,化学镀Ni层中裂纹的产生少,可靠性高。
用于解决课题的方法
为了解决上述课题,本发明的特征在于,具备半导体元件和形成于前述半导体元件的第一表面的第一电极,前述第一电极为包含第一化学镀Ni层的层叠结构,前述第一化学镀Ni层含有Ni(镍)和P(磷)作为组成,前述第一化学镀Ni层的P(磷)浓度为2.5wt%以上6wt%以下,且前述第一化学镀Ni层中的Ni3P的结晶化率为0%以上20%以下。
此外,本发明为一种电源转换装置,具有:一对直流端子,与交流输出的相数数量相等的交流端子,连接于前述一对直流端子间并将两个由开关元件和反极性的二极管构成的并联电路串联连接且与交流输出的相数数量相等的开关引线,以及控制前述开关元件的栅极电路;前述开关元件是具有上述记载的特征的半导体装置。
发明效果
根据本发明,能够实现一种半导体装置及其制造方法,所述半导体装置具有包含化学镀Ni层的电极,其中,化学镀Ni层中裂纹的产生少,可靠性高。
由此,能够实现搭载半导体装置的电源转换装置的小型化、高可靠性化。
除了上述以外的课题、构成和效果通过以下的实施方式说明来揭示。
附图说明
图1为本发明第一实施方式涉及的半导体装置的截面图。
图2为本发明第一实施方式涉及的半导体装置的制造方法中的各工序的截面图。
图3为本发明第一实施方式涉及的半导体装置的制造方法中的各工序的截面图。
图4为显示本发明第一实施方式涉及的化学镀Ni的工艺流程的图。
图5为显示本发明第一实施方式涉及的化学镀Ni的Ni镀膜中的磷浓度和Ni结晶化率与裂纹产生的关系的特性图。
图6为本发明第一实施方式涉及的化学镀Ni(A浴)的X射线衍射图形拟合图。
图7为本发明第一实施方式涉及的化学镀Ni(B浴)的X射线衍射图形拟合图。
图8为本发明第一实施方式涉及的化学镀Ni(C浴)的X射线衍射图形拟合图。
图9为本发明第一实施方式涉及的化学镀Ni(D浴)的X射线衍射图形拟合图。
图10为本发明第一实施方式涉及的化学镀Ni(E浴)的X射线衍射图形拟合图。
图11为本发明第一实施方式涉及的化学镀Ni(F浴)的X射线衍射图形拟合图。
图12为本发明第一实施方式涉及的化学镀Ni(G浴)的X射线衍射图形拟合图。
图13为显示本发明第一实施方式涉及的化学镀Ni(F浴)成膜的Ni结晶化率和Ni3P结晶化率的退火温度依赖性的特性图。
图14为显示本发明第一实施方式涉及的化学镀Ni(F浴)成膜的X射线衍射图形的退火温度依赖性的特性图。
图15为显示本发明第一实施方式涉及的化学镀Ni的磷浓度不同导致的Ni3P结晶化率的退火温度依赖性的特性图。
图16A为本发明第二实施方式涉及的半导体装置的截面图。
图16B为图16A的半导体装置引线键合后的截面图。
图17为本发明第三实施方式涉及的半导体装置的截面图。
图18为显示本发明第四实施方式涉及的电源转换装置的概要构成的电路图。
符号说明
90:Si晶圆(Si基板);100、200、300:半导体装置;101:陶瓷(绝缘)基板;102:导电部件;103:铜烧结层;104:Ni层(化学镀Ni膜);104a:Ni层的表面;106a:第一Al金属层;106b:第二Al金属层;107:Cu扩散防止层;108:半导体基板;108a:p型半导体层;108b:n型迁移层;108c:n+型半导体层;108d:(半导体基板的)第一表面;108e:(半导体基板的)第二表面;109:阳极电极(Al金属层);110:绝缘氧化膜;111:钝化膜(表面保护膜);112:第一半导体芯片的电极结构体(阴极电极);113:第二半导体芯片的电极结构体(阳极电极);150:半导体元件;151:键合线;301:第三半导体芯片的电极结构体(阳极电极);500:电源转换装置;501~506:电力开关元件;511~516:栅极电路;521~526:二极管;531:P端子;532:N端子;533:U端子;534:V端子;535:W端子。
具体实施方式
以下,参照附图详细地对本发明的实施方式进行说明。其中,各附图中对于同一构成给予相同符号,省略对重复部分的详细说明。
实施例1
参照图1至图15,对本发明第一实施方式涉及的半导体装置及其制造方法进行说明。图1为本发明第一实施方式涉及的半导体装置的截面图,显示的是应用于功率半导体芯片的续流二极管情况下的截面结构。其中,以下假定使用n型Si基板的二极管而进行说明,但并不限定于此。使用p型Si基板的情况下也可以同样地进行操作。此外,在使电流纵向流动的IGBT的电极结构中也可以同样地进行操作。进一步,关于SiC、GaN、GaO等宽隙半导体也可以同样地进行操作。
如图1所示,本实施方式的半导体装置100具备由n型Si形成的半导体基板108。半导体基板108从表面开始依次(从图1的上层侧向下层侧)具备p型半导体层108a、n型迁移层108b、由高浓度的n型杂质区域形成的n+型半导体层108c,形成由这些半导体层构成的半导体元件150。半导体基板108具有形成有第一半导体芯片的电极结构体(阴极电极)112的第一表面108d和形成有阳极电极109的第二表面108e。
半导体装置100在形成有半导体元件150的半导体基板108的n+型半导体层108c的第一表面108d具备第一半导体芯片的电极结构体(阴极电极)112,该第一半导体芯片的电极结构体112由与该半导体元件150电连接且由Al或Al合金形成的第一Al金属层106a、Cu扩散防止层107、由Al或Al合金形成的第二Al金属层106b和Ni层104按上述顺序(从图1的上层侧向下层侧)形成。半导体装置100还具有配置于Ni层104的表面104a且介由铜烧结层103与第一半导体芯片的电极结构体112接合的导电部件102。
这里,Ni层104为化学镀Ni层,含有Ni(镍)、P(磷)作为组成,P(磷)的浓度为2.5wt%以上6wt%以下。此外,Ni层(化学镀Ni层)104中的Ni(镍)的结晶化率为70%以上95%以下,Ni(镍)与P(磷)的化合物Ni3P的结晶化率为0%以上20%以下。
其中,第一半导体芯片构成为包括半导体基板108和第一半导体芯片的电极结构体(阴极电极)112。第一Al金属层106a、Cu扩散防止层107、第二Al金属层106b和Ni层104按上述顺序(从图1的上层侧向下层侧)构成作为半导体基板108背面侧的电极结构体的阴极电极112。阴极电极112使用铜烧结层103与陶瓷绝缘基板101上的导电部件102接合。
半导体基板108第二表面108e侧的阳极电极109具有由Al或Al合金形成的电极结构,一部分与半导体基板108的p型半导体层108a相接,另一部分与绝缘氧化膜110相接。此外,在绝缘氧化膜110上形成有钝化膜111。钝化膜111例如由聚酰亚胺构成。
[半导体装置100的制造方法]
接下来,使用图2和图3,对图1所示的本实施方式的半导体装置100的制造方法进行说明。图2和图3为显示半导体装置100的制造方法的各工序的图。
<半导体元件150的制作工序>
图2中的(a)为本实施方式中阳极P型半导体区域形成后的截面图。
首先,准备用于制作二极管的Si晶圆90。Si晶圆可以使用具有相应于耐压的电阻率的晶圆。例如,在具有1700V的耐压的二极管中,可以设为120Ωcm左右,在具有3.3kV的耐压的二极管中,可以设为250Ωcm左右。此时,Si晶圆90实现提高电阻率的n层的功能。下面将形成有p型半导体层108a的Si晶圆90称为n迁移层108b。
在图中未显示的最初的工序中,通过热氧化在Si基板90的表面整体形成氧化膜。接下来,进行用于形成设置p型半导体层108a的区域的光刻工序。该光刻工序中,通过在将抗蚀材料涂布在Si基板90的表面上后进行曝光、显影,形成留有p型半导体层108a区域的抗蚀剂。然后,将p型杂质离子注入。p型杂质例如可列举硼。然后,将抗蚀剂除去,实施用于使杂质活化的退火,从而形成如图2中的(a)所示的p型半导体层108a。
图2中的(b)为本实施方式中形成接触部后的截面图,图2中的(c)为形成阳极电极后的截面图。
接下来,通过热氧化在Si基板90的表面(主面)形成硅氧化膜,通过化学气相沉积(CVD:Chemical Vapor Deposition)法堆积绝缘氧化膜110,并进行用于形成连接p型半导体层108a与阳极电极109(图2中的(c)参照)的接触部的光刻工序。在绝缘氧化膜110的表面涂布抗蚀材料后,通过曝光、显影形成抗蚀剂图案,以此为掩模对绝缘氧化膜110进行蚀刻,从而形成如图2中的(b)所示连接p型半导体层108a与阳极电极的接触部。
然后,通过溅射法使由Al或Al合金形成的阳极电极109成膜,通过光刻工序使抗蚀剂图案化,进行蚀刻,从而形成如图2中的(c)所示的阳极电极109。
接下来,形成作为表面保护膜的钝化膜111(参照图3)。作为保护膜的形成方法,例如,可以涂布含有聚酰亚胺前体材料和感光材料的溶液,对终止区域进行曝光使前体聚酰亚胺化,从而形成钝化膜(表面保护膜)111。
接下来对背面阴极侧的制造工序进行说明。
<背面阴极侧的制作工序>
图3中的(a)为本实施方式中形成有表面保护膜的背面n+型半导体层形成后的截面图。
首先,对n型迁移层108b的背面进行研磨,减小晶圆厚度。晶圆厚度根据耐压的不同而不同,例如,1700V耐压品中为190μm左右,3300V耐压品中为400μm左右。
然后,从n型迁移层108b的背面侧对晶圆整个面进行n型杂质的离子注入。n型杂质例如可列举磷(P)、砷(As)等。
然后,为了使注入了离子的n型杂质活化而进行激光退火,形成n+型半导体层108c。
<背面阴极电极112的制作工序>
接下来,对背面的阴极电极112的制造方法进行说明。
图3中的(b)为本实施方式中背面的阴极电极112形成后的截面图。
阴极电极112是通过溅射依次使背面电极的第一Al金属层106a、Cu扩散防止层107、第二Al金属层106b成膜而形成的,第一Al金属层106a例如为0.6μm的AlSi合金,Cu扩散防止层107例如为0.2μm的钛(Ti),第二Al金属层106b例如为2μm的AlSi合金。
通过在背面的阴极电极112内设置由钛(Ti)形成的扩散防止层107,在使用后述由铜烧结层103形成的接合层与连接端子电连接的情况下,防止铜由该接合层向第一半导体芯片(p型半导体层108a,n型迁移层108b,n+型半导体层108c)扩散,提高长期接合可靠性。
其中,本实施方式中,Cu扩散防止层107使用了钛(Ti),例如,也可以同样地使用能够在确保导电性的情况下形成Cu扩散防止层的氮化钛(TiN)、钛钨(TiW)、钨(W)等材料。
<Ni层104的制作工序>
图3中的(c)为本实施方式中Ni层104形成后的截面图。
Ni层104通过化学镀敷法形成。图4显示的是化学镀Ni的工艺流程。虽然在图3中的(c)和图4中未显示,但本实施方式中,因为仅通过化学镀Ni使阴极电极112成膜,所以在阳极电极109侧粘贴表面保护胶带而进行化学镀Ni。此外,仅在阳极电极109侧使化学镀Ni成膜的情况下,在阴极电极112侧粘贴表面保护胶带而进行化学镀Ni。
化学镀Ni工艺用碱性脱脂剂对最初附着于第二Al金属层106b表面的油分进行清洁。(工序1)接下来,用以氢氧化钠(NaOH)为基础的强碱溶液对第二Al金属层106b进行蚀刻,将氧化皮膜除去。(工序2)接下来,通过酸洗将除去氧化皮膜时生成的Al(OH)3、杂质除去。(工序3)接下来,以在镀液中迅速进行Ni置换的方式进行被覆锌(Zn)的浸锌处理(工序4)。
这里,在图4所示的化学镀工序中,由于成为基础电极的第二Al金属层106b容易形成氧化皮膜,以提高与Ni镀膜的密合性为目的,进行了重复两次锌(Zn)置换的二次浸锌处理。(工序5、工序6)接下来,通过化学镀Ni使Ni膜例如以3μm成膜。(工序7)化学镀Ni的反应中,作为还原剂的次磷酸盐转变为被氧化的亚磷酸盐。
此时通过下述反应进行镀敷:放出电子,使Ni离子还原,形成Ni(镀膜)。
H2PO2 →H2PO3 +2e
Ni2 ++2e→Ni
因此,化学镀Ni膜104含有磷(P),得到由于P含量的不同而性质不同的被膜。此外,化学镀Ni膜的磷(P)含量由于络合剂、pH浓度的不同而不同。
对于安装于作为逆变器等电源转换器的主要部件的电源模块的半导体装置100是,功率半导体芯片与由导电部件102(例如Cu)形成了布线层的陶瓷绝缘基板101、导电部件102与芯片背面的阴极电极112以使用氧化铜(CuO)粒子的接合剂接合。该接合工序中,在还原气氛下进行多阶段加热和加压。接合工序中,多阶段加热是例如对功率半导体芯片施加350℃的热负荷。存在下述课题:如果由于该热负荷在化学镀Ni层104中产生裂纹,则铜由接合层扩散至功率半导体芯片,元件漏电流会增大,元件耐压劣化,改变元件的特性。
图5为本申请发明人等研究的,在化学镀Ni膜104成膜后进行350℃的热处理情况下Ni镀膜中的磷(P)浓度和Ni结晶化率的实验结果。P浓度是通过俄歇电子分光法分析化学镀Ni层104中的P浓度,Ni结晶化率是通过X射线衍射法在30≦2θ≦62deg的范围内用(结晶质峰值积分强度总和/全部峰值积分强度总和)×100%的算式求出。
由本申请发明人等研究的结果可知,即使在专利文献2的磷浓度为4wt%以上且低于6wt%的情况下,由于化学镀Ni浴的种类、镀膜形成后的热处理的不同,也存在容易产生裂纹的情况,对于抑制裂纹产生而言,除了磷浓度以外,提高Ni镀膜的Ni结晶化率也是必要的。
根据本结果,为了抑制裂纹,必须是Ni镀膜的磷(P)浓度为2.5wt%以上6wt%以下且镍(Ni)的结晶化率为70%以上95%以下。
图6至图12分别显示的是本申请发明人等研究的A浴(图6)至G浴(图12)的化学镀Ni膜104成膜后进行350℃的热处理情况下X射线衍射的图形拟合结果。A浴至G浴是设定为Ni镀膜中的磷(P)浓度分别为各图中所示浓度条件的镀浴。
对于Ni的结晶化率为70%以下且产生Ni镀膜裂纹的A浴、B浴、C浴和D浴,除了Ni(111)、Ni(200)的衍射峰以外,还观察到来自镍-磷的化合物的Ni3P(321)和(141)的衍射峰,认为由于热处理而产生发生相变化,导致裂纹产生。
另一方面,对于Ni的结晶化率70%以上的E浴、F浴和G浴,Ni(111)、Ni(200)的衍射峰占主导,仅略微观察到Ni3P(321)的峰,认为Ni镀膜由于热处理的相变化小,因此裂纹产生受到抑制。
图13显示的是由Ni镀膜中的磷浓度为2.7wt%的F浴得到的化学镀Ni膜104成膜后的结晶化率的退火温度依赖性。Ni3P的结晶化率与Ni的结晶化率同样地通过X射线衍射法在30≦2θ≦62deg的范围内由Ni3P的衍射峰用(Ni3P的结晶质峰值积分强度总和/全部峰值积分强度总和)×100%的算式求出。
在磷(P)浓度低且从Ni镀膜刚成膜后开始Ni结晶化率高的情况下,Ni结晶化率由于之后的热处理的变化也小,相变化小,因此能够抑制Ni镀膜的裂纹产生。而如果热负荷增大,作为镍-磷的化合物的Ni3P的结晶化率提高,则产生裂纹。
图14显示的是由Ni镀膜中的磷浓度为2.7wt%的F浴得到的化学镀Ni膜104成膜后的X射线衍射图形的退火温度依赖性。在Ni镀膜刚形成之后的阶段,能够确认到Ni的(111)和(200)的衍射线,如果热负荷增大,则衍射线变尖,可见越是高温,结晶化越是进行。如果退火温度为400℃,则生成作为镍-磷的化合物的Ni3P,能够确认到Ni3P(321)和(141)的衍射线。
图15显示的是磷(P)浓度不同的化学镀Ni膜的Ni3P结晶化率的退火温度依赖性。对于磷浓度为7.3wt%的A浴的Ni镀层,Ni3P的结晶化在250℃以上开始,Ni3P的结晶化率也高,在300℃以上,Ni镀膜中产生裂纹。此外,对于磷浓度为2.7wt%的F浴的Ni镀层,Ni3P的结晶化在350℃以上开始,在400℃,Ni3P的结晶化率为26%,Ni镀膜中产生裂纹。而对于磷浓度为2.5wt%的G浴的Ni镀层,Ni3P的结晶化在350℃以上开始,在400℃,Ni3P的结晶化率为20%,但Ni镀膜中未产生裂纹。以这种方式,随着退火温度的高温化,生成作为镍-磷的化合物的Ni3P,如果Ni3P的结晶化率超过20%,则Ni镀膜中产生裂纹。
如以上说明的那样,根据本实施方式的半导体装置及其制造方法,化学镀Ni层104含有Ni(镍)、P(磷)作为组成,P(磷)的浓度为2.5wt%以上6wt%以下,Ni(镍)的结晶化率为70%以上95%以下,Ni(镍)与P(磷)的化合物Ni3P的结晶化率为0%以上20%以下,通过设为上述特征,能够抑制Ni镀膜的相变化,能够获得高耐热性优异的特性。
即,能够实现一种半导体装置及其制造方法,所述半导体装置具有包含化学镀Ni层的电极,化学镀Ni层中裂纹的产生少,可靠性高。此外,由此能够实现搭载该半导体装置的电源转换装置的小型化、高可靠性化。
其中,本实施方式中,以“Ni层(化学镀Ni层)104含有Ni(镍)、P(磷)作为组成,P(磷)的浓度为2.5wt%以上6wt%以下,Ni层(化学镀Ni层)104中的Ni(镍)的结晶化率为70%以上95%以下,Ni(镍)与P(磷)的化合物Ni3P的结晶化率为0%以上20%以下”为特征,但这些条件中,通过至少满足“P(磷)浓度为2.5wt%以上6wt%以下,且前述第一化学镀Ni层中的Ni3P的结晶化率为0%以上20%以下”的条件,虽然效果程度降低,但也是能够比以往更抑制裂纹的产生。
实施例2
参照图16A和图16B对本发明第二实施方式涉及的半导体装置及其制造方法进行说明。图16A为本发明第二实施方式涉及的半导体装置200的截面图。图16B为图16A的半导体装置200的引线键合后的截面图。
本实施方式的半导体装置200与实施例1同样地是应用于功率半导体芯片的续流二极管情况下的例子。其中,以下假定使用了n型Si基板的二极管来进行说明,但不限定于此。使用p型Si基板的情况下也可以同样地进行操作。此外,在使电流纵向流动的IGBT的电极结构中也可以同样地进行操作。进一步,关于SiC、GaN、GaO等宽隙半导体,也可以同样地进行操作。
如图16A所示,本实施方式的半导体装置200进一步具备在形成有半导体元件150的半导体基板108的第二表面108e,由Al或Al合金形成的Al金属层109和Ni层104按上述顺序(从图16A的下层侧向上层侧)形成的第二半导体芯片的电极结构体113,与第一表面108d的第一半导体芯片的电极结构体112的Ni层104同样地,Ni层104为化学镀Ni层,含有Ni(镍)、P(磷)作为组成,P(磷)的浓度为2.5wt%以上6wt%以下。
第二半导体芯片的电极结构体113形成于与形成有第一半导体芯片的电极结构体112的半导体基板108的第一表面108d相反侧的第二表面108e。
此外,Ni层(化学镀Ni层)104中的Ni(镍)的结晶化率为70%以上95%以下,Ni(镍)与P(磷)的化合物Ni3P的结晶化率为0%以上20%以下。
以这种方式,本实施方式的半导体装置200中,第一半导体芯片的电极结构体112和第二半导体芯片的电极结构体113形成于半导体基板108的两面,导电部件102介由铜烧结层103与第一半导体芯片的电极结构体112接合。此外,如图16B所示,第二半导体芯片的电极结构体113由键合线151连接于陶瓷绝缘基板101上的导电部件102。即,第二半导体芯片的电极结构体113是键合线所接合的焊盘(焊盘电极)。
其中,第二半导体芯片的电极结构体113经过与第一实施方式的图2和图3中说明的第一半导体芯片的电极结构体112的制作工序同样的工序进行制作。
根据本实施方式的半导体装置及其制造方法,除了第一实施方式的效果以外,在半导体基板108的两面设置同样的电极构成体(第一半导体芯片的电极结构体112和第二半导体芯片的电极结构体113),在Si晶圆90的表面和背面形成有对称性良好的电极膜,因而能够减少因电极膜的应力所导致的晶圆翘曲,能够提高制造性。
此外,随着电源模块的高温工作,半导体芯片的表面电极发热,导致铝的晶粒粗大化,由于与半导体芯片的线性热膨胀系数差,对半导体芯片表面电极产生应力,在铝线(键合线151)的接合部下的表面电极内,裂纹会增大,可靠性变差。为了防止该现象,通过减少半导体芯片表面电极中产生的应力、通过化学镀Ni使具有的线性热膨胀系数比铝(Al)更接近硅(Si)的镍(Ni)在铝电极上成膜,可以提高电源模块的高温可靠性。
此外,可获得Ni结晶化率高、高硬度的Ni膜,因此能够减少引线键合时对半导体芯片的机械损伤。
实施例3
参照图17对本发明第三实施方式涉及的半导体装置及其制造方法进行说明。图17为本发明第三实施方式涉及的半导体装置300的截面图。
本实施方式的半导体装置300与实施例1同样地是应用于功率半导体芯片的续流二极管时的例子。其中,以下假定使用n型Si基板的二极管来进行说明,但不限定于此。使用p型Si基板的情况下也可以同样地进行操作。此外,在使电流纵向流动的IGBT的电极结构中也可以同样地进行操作。进一步,关于SiC、GaN、GaO等宽隙半导体,也可以同样地进行操作。
如图17所示,本实施方式的半导体装置300中,在形成有半导体元件150的半导体基板108的第二表面108e上,进一步具备由Al或Al合金形成的第一Al金属层106a、Cu扩散防止层107、由Al或Al合金形成的第二Al金属层106b、按上述顺序(从图17的下层侧向上层侧)形成Ni层104的第三半导体芯片的电极结构体301、配置于第三半导体芯片的电极结构体301的Ni层104的表面104a且介由铜烧结层103与第三半导体芯片的电极结构体301接合的导电部件102。与第一表面108d的第一半导体芯片的电极结构体112的Ni层104同样地,Ni层104为化学镀Ni层,含有Ni(镍)、P(磷)作为组成,P(磷)的浓度为2.5wt%以上6wt%以下。此外,Ni层(化学镀Ni层)104中的Ni(镍)的结晶化率为70%以上95%以下,Ni(镍)与P(磷)的化合物Ni3P的结晶化率为0%以上20%以下。
以这种方式,本实施方式的半导体装置300中,第一半导体芯片的电极结构体112和第三半导体芯片的电极结构体301形成于半导体基板108的两面,导电部件102介由铜烧结层103与第一半导体芯片的电极结构体112和第三半导体芯片的电极结构体301接合。
其中,第一半导体芯片的电极结构体112和第三半导体芯片的电极结构体301夹着半导体基板108(半导体元件150)上下对称地配置,并形成为构成第一半导体芯片的电极结构体112的各膜的膜厚与构成对称的第三半导体芯片的电极结构体301的各膜的膜厚大致相同。
其中,第三半导体芯片的电极结构体301经过与第一实施方式的图2和图3中说明的第一半导体芯片的电极结构体112的制作工序同样的工序进行制作。
根据本实施方式的半导体装置及其制造方法,除了第二实施方式的效果以外,在半导体基板108的两面设有同样的电极结构体(第一半导体芯片的电极结构体112和第三半导体芯片的电极结构体301),在Si晶圆90的表面和背面形成有对称性良好的电极膜,因而能够减小在高温环境下变得显著的各部件的热膨胀差所导致的热应力。理想地,通过使铜烧结层103的热膨胀系数与导电部件102的热膨胀系数一致,在铜烧结层103中所产生的热应力会最小,提高长期可靠性。
实施例4
参照图18对将本发明的半导体装置应用于电源转换装置的第四实施方式进行说明。图18为显示采用第一实施方式涉及的半导体装置100的电源转换装置500的构成的电路图。图18显示的是本实施方式的电源转换装置500的电路构成的一例与直流电源和三相交流马达(交流负载)的连接关系。其中,这里假定采用第一实施方式涉及的半导体装置100的情况进行说明,采用第二实施方式涉及的半导体装置200或第三实施方式涉及的半导体装置300的情况也是同样的。
本实施方式的电源转换装置500中使用第一实施方式的半导体装置100作为电力开关元件501~506。电力开关元件501~506例如为IGBT。
如图18所示,本实施方式的电源转换装置500具备作为一对直流端子的P端子531、N端子532以及作为与交流输出的相数数量相等的交流端子的U端子533、V端子534、W端子535。
此外,具备开关引线,其包括串联连接的一对电力开关元件501和502并以连接于该串联连接点的U端子533为输出。此外,具备与之相同结构的开关引线,其包括串联连接的电力开关元件503和504并以连接于该串联连接点的V端子534为输出。此外,还具备与之相同结构的开关引线,其包括串联连接的电力开关元件505和506并以连接于该串联连接点的W端子535为输出。
由电力开关元件501~506构成的分为3相的开关引线连接于P端子531、N端子532的直流端子间,由图中未显示的直流电源供应直流电。作为电源转换装置500的3相交流端子的U端子533、V端子534、W端子535作为三相交流电源连接于图中未显示的三相交流马达。
电力开关元件501~506分别反向并联地连接有二极管521~526。由IGBT形成的电力开关元件501~506的各自的栅极的输入端子连接有栅极电路511~516,电力开关元件501~506分别由栅极电路511~516来控制。其中,栅极电路511~516由总括控制电路(图中未显示)来总括控制。
由栅极电路511~516适当总括控制电力开关元件501~506,直流电源Vcc的直流电转变为三相交流电,由U端子533、V端子534、W端子535输出。
通过将上述实施例1至实施例3各实施方式涉及的半导体装置应用于电源转换装置500,提高电源转换装置500的长期可靠性。此外,能够搭载于高温环境场所,而且即使不具有专用的冷却器,也能够确保长期的可靠性。或者能够使冷却器小型化,能够使电源转换装置小型化。
其中,关于电子部件中的电气接合部(例如半导体元件与电路部件的接合部)的接合层,本发明特别适合应用于具有化学镀Ni层的半导体装置。
此外,实施例2和实施例3中给出了在半导体元件150的背面电极(电极结构体112)和表面电极(电极结构体113、电极结构体301)的两个化学镀Ni层104中应用本发明的例子,也可以是背面电极(电极结构体112)通过以往的方法制作而仅在表面电极(电极结构体113、电极结构体301)中应用本发明。
此外,实施例4中,作为本发明的半导体装置在电源转换装置中的应用例,对逆变器装置的情况进行了说明,但不限定于此,也可以应用于直流-直流变流器、交流-直流变流器等其他电源转换装置。
此外,本发明不限定于上述实施例,还包括各种变形例。例如,上述实施例为了使对本发明的说明容易理解而详细地进行了说明,并非限定必须具备说明的全部构成。此外,可以将某一实施例的构成的一部分替换为另一实施例的构成,此外,还可以在某一实施例的构成中增加其他实施例的构成。此外,对于各实施例的构成的一部分,可以进行其他构成的增加、去除、替换。
此外,图中的电气布线显示的是认为在说明上必要的布线,不限定在制品上必须显示全部电气布线。
其中,本发明还具有以下的附录1至附录6记载的特征。
[附录1]
一种半导体装置的制造方法,其特征在于,
具有下述工序:
(a)通过溅射使第一Al(铝)金属膜在半导体基板的背面成膜的工序,
(b)前述(a)工序之后,通过溅射使成为Cu扩散防止层的Ti(钛)膜在前述第一Al(铝)金属膜上成膜的工序,
(c)前述(b)工序之后,通过溅射使第二Al(铝)金属膜在前述Ti(钛)膜上成膜的工序,
(d)前述(c)工序之后,通过化学镀敷法使Ni(镍)膜在前述第二Al(铝)金属膜上成膜的工序;
前述Ni(镍)膜含有Ni(镍)和P(磷)作为组成,P(磷)浓度为2.5wt%以上6wt%以下,且前述Ni(镍)膜中的Ni3P的结晶化率为0%以上20%以下。
[附录2]
根据附录1所述的半导体装置的制造方法,其特征在于,前述Ni(镍)膜中Ni(镍)的结晶化率为70%以上95%以下。
[附录3]
一种半导体装置的制造方法,其特征在于,
具有下述工序:
(a)通过溅射使Al(铝)金属膜在半导体基板的表面成膜的工序,
(b)前述(a)工序之后,通过化学镀敷法使Ni(镍)膜在前述Al(铝)金属膜上成膜的工序;
前述Ni(镍)膜含有Ni(镍)和P(磷)作为组成,P(磷)浓度为2.5wt%以上6wt%以下,且前述Ni(镍)膜中的Ni3P的结晶化率为0%以上20%以下。
[附录4]
根据附录3所述的半导体装置的制造方法,其特征在于,前述Ni(镍)膜中Ni(镍)的结晶化率为70%以上95%以下。
[附录5]
根据附录1所述的半导体装置的制造方法,其特征在于,
在前述(a)工序之前或前述(d)工序之后具有下述工序:
(e)通过溅射使第一Al(铝)金属膜在半导体基板的表面成膜的工序,
(f)前述(e)工序之后,通过溅射使成为Cu扩散防止层的Ti(钛)膜在前述第一Al(铝)金属膜上成膜的工序,
(g)前述(f)工序之后,通过溅射使第二Al(铝)金属膜在前述Ti(钛)膜上成膜的工序,
(h)前述(g)工序之后,通过化学镀敷法使Ni(镍)膜在前述第二Al(铝)金属膜上成膜的工序;
前述Ni(镍)膜含有Ni(镍)和P(磷)作为组成,P(磷)浓度为2.5wt%以上6wt%以下,且前述Ni(镍)膜中的Ni3P的结晶化率为0%以上20%以下。
[附录6]
根据附录5所述的半导体装置的制造方法,其特征在于,前述Ni(镍)膜中Ni(镍)的结晶化率为70%以上95%以下。

Claims (8)

1.一种半导体装置,其特征在于,
具备半导体元件和形成于所述半导体元件的第一表面的第一电极,
所述第一电极为包含第一化学镀Ni层的层叠结构,
所述第一化学镀Ni层含有Ni即镍和P即磷作为组成,
所述第一化学镀Ni层的P浓度为2.5wt%以上6wt%以下,且所述第一化学镀Ni层中的Ni3P的结晶化率为0%以上20%以下,
所述第一化学镀Ni层中,Ni的结晶化率为70%以上95%以下。
2.根据权利要求1所述的半导体装置,其特征在于,所述第一化学镀Ni层在所述第一电极中配置于所述第一表面的相反侧,介由铜烧结层与导电部件接合。
3.根据权利要求1所述的半导体装置,其特征在于,
进一步具备形成于所述半导体元件的与所述第一表面相反侧的第二表面的第二电极,
所述第二电极为包含第二化学镀Ni层的层叠结构,
所述第二化学镀Ni层含有Ni和P作为组成,
所述第二化学镀Ni层的P浓度为2.5wt%以上6wt%以下,且所述第二化学镀Ni层中的Ni3P的结晶化率为0%以上20%以下。
4.根据权利要求3所述的半导体装置,其特征在于,所述第二化学镀Ni层中Ni的结晶化率为70%以上95%以下。
5.根据权利要求3所述的半导体装置,其特征在于,所述第二化学镀Ni层在所述第二电极中配置于所述第二表面的相反侧,介由铜烧结层与导电部件接合。
6.根据权利要求3所述的半导体装置,其特征在于,
所述第一电极的层叠结构和所述第二电极的层叠结构是夹着所述半导体元件而对称配置的层叠结构,
构成所述第一电极的层叠结构的膜的膜厚与构成对称的所述第二电极的层叠结构的膜的膜厚相同。
7.根据权利要求3所述的半导体装置,其特征在于,所述第二电极是键合线所接合的焊盘。
8.一种电源转换装置,其特征在于,具有:
一对直流端子,
与交流输出的相数数量相等的交流端子,
连接于所述一对直流端子间并将两个由开关元件和反极性的二极管构成的并联电路串联连接且与交流输出的相数数量相等的开关引线,以及
控制所述开关元件的栅极电路;
所述开关元件为权利要求1至7中任一项所述的半导体装置。
CN201910615173.7A 2018-08-28 2019-07-09 半导体装置和电源转换装置 Active CN110867485B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311274137.1A CN117253912A (zh) 2018-08-28 2019-07-09 半导体装置和电源转换装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-159171 2018-08-28
JP2018159171A JP7075847B2 (ja) 2018-08-28 2018-08-28 半導体装置および電力変換装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN202311274137.1A Division CN117253912A (zh) 2018-08-28 2019-07-09 半导体装置和电源转换装置

Publications (2)

Publication Number Publication Date
CN110867485A CN110867485A (zh) 2020-03-06
CN110867485B true CN110867485B (zh) 2023-09-26

Family

ID=69526988

Family Applications (2)

Application Number Title Priority Date Filing Date
CN202311274137.1A Pending CN117253912A (zh) 2018-08-28 2019-07-09 半导体装置和电源转换装置
CN201910615173.7A Active CN110867485B (zh) 2018-08-28 2019-07-09 半导体装置和电源转换装置

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN202311274137.1A Pending CN117253912A (zh) 2018-08-28 2019-07-09 半导体装置和电源转换装置

Country Status (4)

Country Link
US (1) US10847614B2 (zh)
JP (1) JP7075847B2 (zh)
CN (2) CN117253912A (zh)
DE (1) DE102019210821B4 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230040727A1 (en) * 2020-05-13 2023-02-09 Mitsubishi Electric Corporation Semiconductor device
CN111540680A (zh) * 2020-05-29 2020-08-14 上海华虹宏力半导体制造有限公司 应用于igbt器件的化镀方法
JP7410822B2 (ja) * 2020-08-20 2024-01-10 株式会社 日立パワーデバイス 半導体パワーモジュールおよび半導体パワーモジュールの製造方法
JP2023049645A (ja) * 2021-09-29 2023-04-10 株式会社 日立パワーデバイス めっき欠陥推定方法および半導体装置の製造方法
JP2024044822A (ja) * 2022-09-21 2024-04-02 株式会社デンソー 半導体装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006206985A (ja) * 2005-01-31 2006-08-10 C Uyemura & Co Ltd 無電解ニッケル−リンめっき皮膜及び無電解ニッケル−リンめっき浴
JP2013194291A (ja) * 2012-03-21 2013-09-30 Mitsubishi Electric Corp 半導体装置およびその半導体装置の製造方法
CN104425580A (zh) * 2013-09-09 2015-03-18 株式会社东芝 功率用半导体装置及其制造方法
CN105931954A (zh) * 2015-02-26 2016-09-07 株式会社日立功率半导体 半导体装置、半导体装置的制造方法以及电力变换装置
WO2016155965A2 (de) * 2015-03-30 2016-10-06 Robert Bosch Gmbh Kontaktanordnung und verfahren zu herstellung der kontaktanordnung
CN106531620A (zh) * 2015-09-15 2017-03-22 三菱电机株式会社 半导体装置的制造方法
WO2018131144A1 (ja) * 2017-01-13 2018-07-19 三菱電機株式会社 半導体装置及びその製造方法
WO2018135239A1 (ja) * 2017-01-19 2018-07-26 株式会社 日立パワーデバイス 半導体装置および電力変換装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3599060A (en) * 1968-11-25 1971-08-10 Gen Electric A multilayer metal contact for semiconductor device
US6136702A (en) * 1999-11-29 2000-10-24 Lucent Technologies Inc. Thin film transistors
JP2003037133A (ja) * 2001-07-25 2003-02-07 Hitachi Ltd 半導体装置およびその製造方法ならびに電子装置
US6555411B1 (en) * 2001-12-18 2003-04-29 Lucent Technologies Inc. Thin film transistors
JP5006081B2 (ja) 2007-03-28 2012-08-22 株式会社日立製作所 半導体装置、その製造方法、複合金属体及びその製造方法
JP5483906B2 (ja) * 2009-03-04 2014-05-07 三菱電機株式会社 半導体装置およびその製造方法
JP5812090B2 (ja) * 2011-03-10 2015-11-11 富士電機株式会社 電子部品および電子部品の製造方法
JP2013243338A (ja) * 2012-04-23 2013-12-05 Denso Corp 半導体装置
JP6017834B2 (ja) * 2012-05-16 2016-11-02 Dowaエレクトロニクス株式会社 半導体素子の製造方法ならびに半導体素子集合体および半導体素子
JP5725073B2 (ja) * 2012-10-30 2015-05-27 三菱電機株式会社 半導体素子の製造方法、半導体素子
JP2015056532A (ja) * 2013-09-12 2015-03-23 株式会社東芝 半導体装置及びその製造方法
WO2016002455A1 (ja) * 2014-07-03 2016-01-07 Jx日鉱日石金属株式会社 放射線検出器用ubm電極構造体、放射線検出器及びその製造方法
US11309251B2 (en) * 2017-07-31 2022-04-19 AdTech Ceramics Company Selective metallization of integrated circuit packages

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006206985A (ja) * 2005-01-31 2006-08-10 C Uyemura & Co Ltd 無電解ニッケル−リンめっき皮膜及び無電解ニッケル−リンめっき浴
JP2013194291A (ja) * 2012-03-21 2013-09-30 Mitsubishi Electric Corp 半導体装置およびその半導体装置の製造方法
CN104425580A (zh) * 2013-09-09 2015-03-18 株式会社东芝 功率用半导体装置及其制造方法
CN105931954A (zh) * 2015-02-26 2016-09-07 株式会社日立功率半导体 半导体装置、半导体装置的制造方法以及电力变换装置
WO2016155965A2 (de) * 2015-03-30 2016-10-06 Robert Bosch Gmbh Kontaktanordnung und verfahren zu herstellung der kontaktanordnung
CN106531620A (zh) * 2015-09-15 2017-03-22 三菱电机株式会社 半导体装置的制造方法
WO2018131144A1 (ja) * 2017-01-13 2018-07-19 三菱電機株式会社 半導体装置及びその製造方法
WO2018135239A1 (ja) * 2017-01-19 2018-07-26 株式会社 日立パワーデバイス 半導体装置および電力変換装置

Also Published As

Publication number Publication date
DE102019210821B4 (de) 2022-09-08
US10847614B2 (en) 2020-11-24
CN117253912A (zh) 2023-12-19
US20200075722A1 (en) 2020-03-05
DE102019210821A1 (de) 2020-03-05
JP7075847B2 (ja) 2022-05-26
JP2020035812A (ja) 2020-03-05
CN110867485A (zh) 2020-03-06

Similar Documents

Publication Publication Date Title
CN110867485B (zh) 半导体装置和电源转换装置
JP6300236B2 (ja) 半導体装置、半導体装置の製造方法および電力変換装置
US8198104B2 (en) Method of manufacturing a semiconductor device
US8592986B2 (en) High melting point soldering layer alloyed by transient liquid phase and fabrication method for the same, and semiconductor device
US9673163B2 (en) Semiconductor device with flip chip structure and fabrication method of the semiconductor device
CN105103272B (zh) 半导体装置的制造方法
TWI638461B (zh) 半導體裝置及電力變換裝置
JP4479577B2 (ja) 半導体装置
US11710709B2 (en) Terminal member made of plurality of metal layers between two heat sinks
US9087833B2 (en) Power semiconductor devices
JP2017059720A (ja) 半導体装置および半導体装置の製造方法
JP2014120639A (ja) パワーモジュール半導体装置
CN109075198B (zh) 电力用半导体装置
CN111819697B (zh) 半导体装置、电力变换装置
JP7386662B2 (ja) 半導体装置および電力変換装置
US20130221514A1 (en) Semiconductor device and fabrication method for the same
WO2022038833A1 (ja) 半導体パワーモジュールおよび半導体パワーモジュールの製造方法
WO2022270305A1 (ja) 半導体装置、および半導体装置の製造方法
JP2023178555A (ja) 半導体装置および電力変換装置
JP2023158319A (ja) 半導体装置および電力変換装置
CN116601759A (zh) 具有优化的冷却和接触的用于运行电动车驱动装置的功率模块
JP2014067821A (ja) 回路基板および電子装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant