CN110634865B - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN110634865B
CN110634865B CN201910553241.1A CN201910553241A CN110634865B CN 110634865 B CN110634865 B CN 110634865B CN 201910553241 A CN201910553241 A CN 201910553241A CN 110634865 B CN110634865 B CN 110634865B
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contact
gate
pattern
semiconductor device
source
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CN110634865A (zh
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郑元根
李宪福
申忠桓
蔡荣锡
玄尚镇
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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Abstract

一种半导体器件，包括在其中具有有源图案的基板、横跨有源图案延伸的栅电极和在有源图案上与栅电极横向相邻的源/漏区。该器件还包括接触结构，该接触结构包括在源/漏区上的第一接触、在第一接触上的第二接触以及在第一和第二接触的侧壁上的间隔物。

Description

半导体器件
技术领域
本公开的示例实施方式涉及半导体器件，更具体地，涉及包括场效应晶体管的半导体器件及其制造方法。
背景技术
小尺寸、多功能和/或低成本的半导体器件用于电子设备中。半导体器件分为存储逻辑数据的半导体存储器件、处理逻辑数据的半导体逻辑器件、以及包括存储元件和逻辑元件的混合半导体器件。随着电子工业的发展，对半导体器件的特性(例如，高速、高可靠性和/或多功能)的需求不断增加。为了满足这种需求，半导体器件的结构已经复杂化，并且半导体器件已经变得更加高度集成。
发明内容
根据本发明构思的示例实施方式，半导体器件包括在其中具有有源图案的基板、横跨有源图案延伸的栅电极、以及在有源图案上与栅电极横向相邻的源/漏区。该器件还包括接触结构，该接触结构包括在源/漏区上的第一接触、在第一接触上的第二接触、以及在第一和第二接触的侧壁上并具有与第二接触的上表面共面的上表面的间隔物。
根据本发明构思的其他示例实施方式，半导体器件包括在其中具有有源图案的基板、横跨有源图案延伸的栅电极、在有源图案上与栅电极横向相邻的源/漏区、以及电连接到栅电极的栅极接触。该器件还包括接触结构，该接触结构电连接到源/漏区并且包括在源/漏区上的第一接触和在第一接触上的第二接触，其中第二接触的上表面与栅极接触的上表面共面，并且其中第一接触的上表面低于栅极接触的下表面。
根据本发明构思的又一示例实施方式，半导体器件包括在其中具有有源图案的基板、沿第一方向横跨有源图案纵向延伸的栅电极、以及在有源图案上横向邻近栅电极的源/漏区。该器件还包括接触结构，该接触结构包括在源/漏区上的第一接触、在第一接触上并沿第一方向具有比第一接触的最大宽度小的最大宽度的第二接触。绝缘层设置在第一接触的侧壁上。
附图说明
图1是示出根据示例实施方式的半导体器件的平面图。
图2A、2B和2C分别是沿图1的线A-A'、B-B'和C-C'截取的剖视图。
图3、5、7、9、11和13是示出根据示例实施方式的制造半导体器件的方法的平面图。
图4、6A、8A、10A、12A和14A分别是沿图3、5、7、9、11和13的线A-A'截取的剖视图。
图6B、8B、10B、12B和14B分别是沿图5、7、9、11和13的线B-B'截取的剖视图。
图6C、8C、10C、12C和14C分别是沿图5、7、9、11和13的线C-C'截取的剖视图。
图15至20示出了根据示例实施方式的接触结构，并且是图2A的部分M和图2B的部分N的剖视图。
具体实施方式
现在将在下文中参考附图更全面地描述各种示例实施方式。在本申请中，相同的附图标记可以指代相同的元件。
图1是示出根据示例实施方式的半导体器件的平面图。图2A、2B和2C分别是沿图1的线A-A'、B-B'和C-C'截取的剖视图。
参照图1和图2A至2C，基板100可以包括PMOSFET区PR和NMOSFET区NR。基板100可以是包括硅、锗等的半导体基板或化合物半导体基板。作为示例，基板100可以是硅基板。
在一些实施方式中，PMOSFET区PR和NMOSFET区NR可以是逻辑单元区，在其中设置构成半导体器件的逻辑电路的逻辑晶体管。例如，构成处理核心或输入/输出(I/O)端子的逻辑晶体管可以设置在逻辑单元区的基板100上。PMOSFET区PR和NMOSFET区NR可以包括一些逻辑晶体管。
PMOSFET区PR和NMOSFET区NR可以由形成在基板100的上部中的第二沟槽TR2限定。第二沟槽TR2可以设置在PMOSFET区PR和NMOSFET区NR之间。PMOSFET区PR和NMOSFET区NR可以在第一方向D1上彼此间隔开，其间具有第二沟槽TR2。PMOSFET区PR和NMOSFET区NR中的每个可以在与第一方向D1交叉的第二方向D2上延伸。第一方向D1和第二方向D2可以平行于基板100的上表面。
多个有源图案AP1和AP2可以设置在PMOSFET区PR和NMOSFET区NR上，并且可以在第二方向D2上延伸。有源图案AP1和AP2可以包括在PMOSFET区PR上的第一有源图案AP1和在NMOSFET区NR上的第二有源图案AP2。第一和第二有源图案AP1和AP2可以是基板100的部分，例如，垂直突出部分。第一沟槽TR1可以限定在相邻的第一有源图案AP1之间和相邻的第二有源图案AP2之间。
器件隔离层ST可以填充第一和第二沟槽TR1和TR2。器件隔离层ST可以包括绝缘材料，例如，硅氧化物。第一有源图案AP1和第二有源图案AP2的上部可以在器件隔离层ST上方垂直突出。第一有源图案AP1和第二有源图案AP2的每个上部可以具有鳍形状。器件隔离层ST可以不覆盖第一有源图案AP1和第二有源图案AP2的上部。器件隔离层ST可以覆盖第一有源图案AP1和第二有源图案AP2的下侧壁。
第一源/漏区SD1可以设置在第一有源图案AP1上。第一源/漏区SD1中的每个可以包括第一导电类型(例如，p型)杂质区。第一沟道区CH1可以插置在一对第一源/漏区SD1之间。第二源/漏区SD2可以设置在第二有源图案AP2上。每个第二源/漏区SD2可以包括第二导电类型(例如，n型)杂质区。第二沟道区CH2可以插置在一对第二源/漏区SD2之间。
第一和第二源/漏区SD1和SD2可以是通过选择性外延生长工艺形成的外延图案。第一和第二源/漏区SD1和SD2的上表面可以位于比第一沟道区CH1和第二沟道区CH2的上表面更高的水平。在一些实施方式中，第一源/漏区SD1可以包括具有比基板100的半导体元素的晶格常数更大的晶格常数的半导体元素(例如，SiGe)。因此，第一源/漏区SD1可以对第一沟道区CH1施加压缩应力。在一些实施方式中，第二源/漏区SD2可以包括与基板100相同的元素(例如，Si)。
栅电极GE可以设置为横过第一和第二有源图案AP1和AP2，并且可以在第一方向D1上延伸。栅电极GE可以彼此间隔开。栅电极GE可以垂直地重叠第一和第二沟道区CH1和CH2。参考图2C，每个栅电极GE可以覆盖第一和第二沟道区CH1和CH2中的每个的上表面和侧壁。栅电极GE可以包括导电金属氮化物(例如，钛氮化物或钽氮化物)、和/或金属(例如，钛、钽、钨、铜或铝)。
一对栅极间隔物GS可以设置在每个栅电极GE的相反侧壁上。栅极间隔物GS可以沿着栅电极GE在第一方向D1上延伸。相对于基板100的上表面，栅极间隔物GS的上表面可以高于栅电极GE的上表面。栅极间隔物GS的上表面可以与稍后将描述的第一层间绝缘层110的上表面共面。栅极间隔物GS可以包括SiCN、SiCON和SiN中的至少一种。在一些实施方式中，每个栅极间隔物GS可以包括由SiCN、SiCON和SiN中的至少两种形成的多层膜。
栅极电介质图案GI可以插置在栅电极GE与第一和第二有源图案AP1和AP2之间。每个栅极电介质图案GI可以沿着每个栅电极GE的下表面延伸。每个栅极电介质图案GI可以覆盖第一沟道区CH1和第二沟道区CH2中的每个的上表面和侧壁。栅极电介质图案GI可以包括高k电介质材料。例如，高k电介质材料可包括铪氧化物、铪硅氧化物、镧氧化物、锆氧化物、锆硅氧化物、钽氧化物、钛氧化物、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、锂氧化物、铝氧化物、铅钪钽氧化物和铌酸铅锌中的至少一种。
栅极覆盖图案GP可以分别设置在栅电极GE上。栅极覆盖图案GP可以沿着栅电极GE在第一方向D1上延伸。栅极覆盖图案GP可以包括相对于第一层间绝缘层110和稍后将描述的第二层间绝缘层120具有蚀刻选择性的材料。栅极覆盖图案GP可以包括SiON、SiCN、SiCON和SiN中的至少一种。
第一层间绝缘层110可以设置在基板100上。第一层间绝缘层110可以覆盖栅极间隔物GS以及第一和第二源/漏区SD1和SD2。第一层间绝缘层110的上表面可以与栅极覆盖图案GP的上表面基本上共面。第二层间绝缘层120可以设置在第一层间绝缘层110上以覆盖栅极覆盖图案GP。第一和第二层间绝缘层110和120可包括例如硅氧化物。
接触结构AC可以设置为穿过第一层间绝缘层110和第二层间绝缘层120并且电连接到第一和第二源/漏区SD1和SD2。具体地，接触孔CNH可以被限定为穿过第一和第二层间绝缘层110和120以暴露第一源/漏区SD1和/或第二源/漏区SD2。每个接触结构AC可以设置在接触孔CNH中。每个接触结构AC可以设置在一对栅电极GE之间。
每个接触结构AC可以包括第一接触CT1、第一接触CT1上的第二接触CT2、接触间隔物CSP和绝缘层MIL。接触间隔物CSP可以共形地覆盖接触孔CNH的内侧壁。
第一接触CT1可以设置在接触孔CNH的下部中。第一接触CT1可以包括第一阻挡图案BM1和第一导电图案FM1。第一阻挡图案BM1可以插置在第一导电图案FM1与接触间隔物CSP之间以及在第一导电图案FM1与第一和第二源/漏区SD1和SD2的每个之间。第一阻挡图案BM1可以覆盖第一导电图案FM1的侧壁和下表面。第一阻挡图案BM1可以不覆盖第一导电图案FM1的上表面。作为示例，第一阻挡图案BM1的上表面可以与第一导电图案FM1的上表面共面。第一接触CT1的上表面可以相对于基板100的上表面低于每个栅电极GE的上表面。
第二接触CT2和绝缘层MIL可以设置在接触孔CNH的上部中。绝缘层MIL可以插置在第二接触CT2和接触间隔物CSP之间。第二接触CT2可以接触第一接触CT1的上表面。相对于基板100的上表面，第二接触CT2的下表面可以低于每个栅电极GE的上表面。第二接触CT2的上表面可以与接触间隔物CSP的上表面、绝缘层MIL的上表面和第二层间绝缘层120的上表面共面。
第一阻挡图案BM1可以包括金属氮化物，例如，钛氮化物、钨氮化物和钽氮化物中的至少一种。第一导电图案FM1可以包括金属，例如，铝、铜、钨、钼和钴中的至少一种。第二接触CT2可以包括金属，例如，铝、铜、钨、钼和钴中的至少一种。作为示例，第二接触CT2可以包括与第一导电图案FM1不同的金属。第一导电图案FM1可以包括钨，第二接触CT2可以包括钴。接触间隔物CSP可以包括SiCN、SiCON和SiN中的至少一种。绝缘层MIL可以包括硅氧化物或硅氮化物。
再次参照图2B，第一接触CT1在第一方向D1上的最大宽度可以是第一宽度W1，第二接触CT2在第一方向D1上的最大宽度可以是第二宽度W2。第一宽度W1可以大于第二宽度W2。第一接触CT1的上部在第二方向D2上的宽度也可以大于第二接触CT2的下部在第二方向D2上的宽度，如图2A所示。
第一接触CT1可以包括在第一方向D1上彼此相邻的第一部分P1和第二部分P2。例如，第一部分P1可以设置在一对第一有源图案AP1中的一个上，第二部分P2可以设置在一对第一有源图案AP1中的另一个上。第二接触CT2可以设置在第一部分P1或第二部分P2上。由于如上所述的第一宽度W1大于第二宽度W2，所以第二接触CT2可以设置在第一部分P1和第二部分P2中的任一个上。
再次参照图1和图2A至2C，硅化物层可以插置在第一和第二源/漏区SD1和SD2中的每个与第一接触CT1之间。接触结构AC可以电连接到第一源/漏区SD1和第二源/漏区SD2。硅化物层可包括金属硅化物，例如，钛硅化物、钽硅化物、钨硅化物、镍硅化物和钴硅化物中的至少一种。
栅极接触GC可以被设置为穿过第二层间绝缘层120和栅极覆盖图案GP以电连接到栅电极GE。每个栅极接触GC可以包括第二阻挡图案BM2、第二导电图案FM2和接触间隔物CSP。第二阻挡图案BM2可以插置在第二导电图案FM2和接触间隔物CSP之间以及在第二导电图案FM2和每个栅电极GE之间。第二阻挡图案BM2可以覆盖第二导电图案FM2的侧壁和下表面。第二阻挡图案BM2可以不覆盖第二导电图案FM2的上表面。
第二阻挡图案BM2可以包括金属氮化物。第二导电图案FM2可以包括金属。每个栅极接触GC的接触间隔物CSP可以包括与每个接触结构AC的接触间隔物CSP相同的材料。
每个栅极接触GC可以接触每个栅电极GE的上表面。相对于基板100的上表面，每个栅极接触GC的下表面可以高于每个接触结构AC的第一接触CT1的上表面。相对于基板100的上表面，每个栅极接触GC的下表面可以高于每个接触结构AC的第二接触CT2的下表面。栅极接触GC的上表面可以与第二层间绝缘层120的上表面共面。
作为示例实施方式，至少一个栅极接触GC可以设置在每个第一有源图案AP1或每个第二有源图案AP2上。栅极接触GC可以在第二方向D2上与接触结构AC相邻。在下文中，将详细描述栅极接触GC和与其相邻的接触结构AC之间的关系。
作为示例，接触结构AC的第一接触CT1的第一部分P1可以在第二方向D2上与栅极接触GC相邻。接触结构AC的第二接触CT2可以设置在第一接触CT1的第二部分P2上。换句话说，接触结构AC的第二接触CT2可以从栅极接触GC偏移。
在平面图中，接触结构AC的第二接触CT2可以与栅极接触GC间隔开最小距离ML。因此，可以防止栅极接触GC和接触结构AC的第二接触CT2之间的电短路。如果接触结构AC的第二接触CT2设置在第一接触CT1的第一部分上，则栅极接触GC和第二接触CT2可以彼此非常接近，使得可以产生电短路。
另外，如上所述，相对于基板100的上表面，栅极接触GC的下表面可以高于接触结构AC的第一接触CT1的上表面。因此，可以防止栅极接触AC和接触结构AC的第一接触CT1之间的电短路。
第三层间绝缘层130可以设置在第二层间绝缘层120上。布线MI和通孔VI可以设置在第三层间绝缘层130中。每个通孔VI可以插置在每个布线MI和每个接触结构AC之间以及在每个布线MI和每个栅极接触GC之间，并且可以垂直连接它们。布线MI和通孔VI可以包括金属，例如铝、铜、钨、钼和钴。
根据示例实施方式，由于栅极接触GC设置在PMOSFET区PR和NMOSFET区NR中，所以可以减小PMOSFET区PR和NMOSFET区NR之间的距离。随着第一方向D1上的逻辑单元的长度减小，可以增加半导体器件的集成密度。
与栅极接触GC相邻的接触结构AC可以包括双接触结构，其包括第一接触CT1和第二接触CT2。第一接触CT1可以相对于基板100的上表面位于比栅极接触GC更低的水平。第二接触CT2可以定位在与栅极接触GC基本相同的水平。第二接触CT2可以从栅极接触GC偏移，使得可以确保第二接触CT2和栅极接触GC之间的最小距离。因此，可以防止栅极接触GC和接触结构AC之间的电短路，从而提高半导体器件的可靠性。
图3、5、7、9、11和13是示出根据示例实施方式的制造半导体器件的方法的平面图。图4、6A、8A、10A、12A和14A分别是沿图3、5、7、9、11和13的线A-A'截取的剖视图。图6B、8B、10B、12B和14B分别是沿图5、7、9、11和13的线B-B'截取的剖视图。图6C、8C、10C、12C和14C分别是沿图5、7、9、11和13的线C-C'截取的剖视图。
参照图3和图4，基板100的上部可以被图案化以形成第一有源图案AP1和第二有源图案AP2。第一沟槽TR1可以形成在第一有源图案AP1之间和第二有源图案AP2之间。第二沟槽TR2可以形成在其中形成有第一有源图案AP1的PMOSFET区PR和其中形成有第二有源图案AP2的NMOSFET区NR之间。
器件隔离层ST可以形成在基板100上以填充第一和第二沟槽TR1和TR2。器件隔离层ST可以包括绝缘材料，例如硅氧化物。器件隔离层ST可以凹进直到第一和第二有源图案AP1和AP2的上部被暴露，使得第一和第二有源图案AP1和AP2的上部可以在器件隔离层ST上方垂直突出。
参照图5和图6A至图6C，牺牲图案PP可以形成在基板100上以横过第一有源图案AP1和第二有源图案AP2。牺牲图案PP可以形成为沿第一方向D1延伸的线形或条形。具体地，牺牲图案PP的形成可以包括在基板100的整个表面上形成牺牲层，在牺牲层上形成硬掩模图案MA，以及使用硬掩模图案MA作为蚀刻掩模来图案化牺牲层。牺牲层可以包括多晶硅层。
一对栅极间隔物GS可以形成在每个牺牲图案PP的相反侧壁上。栅极间隔物GS可以形成在第一有源图案AP1和第二有源图案AP2中每个的相反侧壁上。由栅极间隔物GS覆盖的第一有源图案AP和第二有源图案AP的侧壁可以是未被器件隔离层ST和牺牲图案PP覆盖的表面。
栅极间隔物GS的形成可以包括在基板100的整个表面上共形地形成栅极间隔物层并且各向异性地蚀刻栅极间隔物层。栅极间隔物层可以包括SiCN、SiCON和SiN中的至少一种。在一些实施方式中，栅极间隔物层可以是包括SiCN、SiCON和SiN中的至少两种的多层膜。
参照图7和图8A至图8C，第一源/漏区SD1可以形成在每个第一有源图案AP上。一对第一源/漏区SD1可以形成在每个牺牲图案PP的相反侧。
具体地，使用硬掩模图案MA和栅极间隔物GS作为蚀刻掩模可以蚀刻第一有源图案AP1的上部，以形成第一凹陷区域。在蚀刻第一有源图案AP1的上部期间，也可以去除每个第一有源图案AP1的侧壁上的栅极间隔物GS。另外，在蚀刻第一有源图案AP1的上部期间，第一有源图案AP1之间的器件隔离层ST可以被凹进。
选择性外延生长工艺可以使用第一有源图案AP1的第一凹陷区域的内表面作为籽晶来执行，以形成第一源/漏区SD1。当形成第一源/漏区SD1时，第一沟道区CH1可以插置在一对第一源/漏区SD1之间。选择性外延生长工艺可包括化学气相沉积(CVD)工艺或分子束外延(MBE)工艺。第一源/漏区SD1可以包括晶格常数大于基板100的半导体元素的晶格常数的半导体元素(例如，SiGe)。每个第一源/漏区SD1可以由多个半导体层形成。
在一些实施方式中，在用于形成第一源/漏区SD1的选择性外延生长工艺期间可以原位注入杂质。在一些实施方式中，在形成第一源/漏区SD1之后，杂质可以被注入第一源/漏区SD1中。第一源/漏区SD1可以掺杂有第一导电类型(例如，p型)的杂质。
第二源/漏区SD2可以形成在每个第二有源图案AP2上。一对第二源/漏区SD2可以形成在每个牺牲图案PP的相反侧。
具体地，使用硬掩模图案MA和栅极间隔物GS作为蚀刻掩模可以蚀刻第二有源图案AP2的上部，以形成第二凹陷区域。选择性外延生长工艺可以使用第二有源图案AP2的第二凹陷区域的内表面作为籽晶来执行，以形成第二源/漏区SD2。当形成第二源/漏区SD2时，第二沟道区CH2可以插置在一对第二源/漏区SD2之间。第二源/漏区SD2可以包括与基板100相同的半导体元素(例如，Si)。第二源/漏区SD2可以掺杂有第二导电类型(例如，n型)的杂质。
第一源/漏区SD1和第二源/漏区SD2可以通过不同的工艺顺序地形成。换句话说，第一源/漏区SD1和第二源/漏区SD2可以不同时形成。
参照图9和图10A至图10C，第一层间绝缘层110可以形成为覆盖第一和第二源/漏区SD1和SD2、硬掩模图案MA和栅极间隔物GS。第一层间绝缘层110可以包括例如硅氧化物。
第一层间绝缘层110可以被平坦化以暴露牺牲图案PP的上表面。第一层间绝缘层110的平坦化可以通过回蚀工艺或化学机械抛光(CMP)工艺来执行。在平坦化工艺期间可以完全去除硬掩模图案MA。因此，第一层间绝缘层110的上表面可以与牺牲图案PP的上表面和栅极间隔物GS的上表面共面。
牺牲图案PP可以用栅电极GE代替。具体地，可以选择性地去除暴露的牺牲图案PP。随着牺牲图案PP被去除，可以形成空的空间。栅极电介质图案GI、栅电极GE和栅极覆盖图案GP可以形成在每个空的空间中。可以共形地形成栅极电介质图案GI，以不完全填充每个空的空间。通过原子层沉积(ALD)工艺或化学气相沉积(CVD)工艺可以形成栅极电介质图案GI。栅极电介质图案GI可以包括例如高k电介质材料。
通过形成栅电极层以完全填充每个空的空间然后平坦化栅电极层可以形成栅电极GE。栅电极层可以包括例如金属氮化物和/或金属。
此后，栅电极GE的上部可以凹进。栅极覆盖图案GP可以形成在凹入的栅电极GE上。栅极覆盖图案GP可以包括SiON、SiCN、SiCON和SiN中的至少一种。
参照图11和图12A至12C，第二层间绝缘层120可以形成在第一层间绝缘层110上。第二层间绝缘层120可以包括例如硅氧化物层或低k氧化物层。低k氧化物层可以包括碳掺杂的硅氧化物，诸如，SiCOH。通过化学气相沉积(CVD)工艺可以形成第二层间绝缘层120。
接触孔CNH可以形成为穿过第二层间绝缘层120和第一层间绝缘层110，以暴露第一源/漏区SD1和/或第二源/漏区SD2。接触间隔物CSP可以形成为覆盖接触孔CNH的内侧壁。接触间隔物CSP可以通过共形地形成接触间隔物层以覆盖接触孔CNH的内侧壁并且对接触间隔物层进行各向异性蚀刻来形成。接触间隔物层可以包括SiCN、SiCON和SiN中的至少一种。
第一接触CT1可以形成为填充接触孔CNH的下部。第一接触CT1可以接触第一和第二源/漏区SD1和SD2。第一接触CT1的形成可以包括形成第一阻挡图案BM1和第一导电图案FM1。具体地，形成第一阻挡层以填充接触孔CNH，然后可以在第一阻挡层上形成第一导电层。第一阻挡层和第一导电层可以凹进以分别形成第一阻挡图案BM1和第一导电图案FM1。第一阻挡层可包括金属氮化物。第一导电图案可以包括金属。
参照图13和图14A至14C，可以在基板100上形成绝缘层MIL。绝缘层MIL可以填充接触孔CNH。绝缘层MIL可以覆盖接触孔CNH的顶部。绝缘层MIL可以包括硅氧化物或硅氮化物。
绝缘层MIL可以被图案化以在接触孔CNH中形成子接触孔sCNH。子接触孔sCNH可以暴露第一接触CT1的上表面。子接触孔sCNH可以暴露第一接触CT1的第一部分P1或第二部分P2。
参照图1和图2A至2C，可以形成第二接触CT2以填充子接触孔sCNH。可以执行平坦化工艺以暴露第二层间绝缘层120的上表面。因此，可以形成包括第一接触CT1和第二接触CT2的接触结构AC。
栅极接触GC可以形成为穿过第二层间绝缘层120和第一层间绝缘层110，以分别电连接到栅电极GE。栅极接触GC的形成可以类似于第一接触CT1的形成。例如，每个栅极接触GC的形成可以包括形成接触孔以穿过第二层间绝缘层120和第一层间绝缘层110以暴露每个栅电极GE的上表面，在接触孔的内侧壁上形成接触间隔物CSP，以及形成第二阻挡图案BM2和第二导电图案FM2。在一些实施方式中，栅极接触GC可以与第一接触CT1一起形成。在一些实施方式中，栅极接触GC可以通过与接触结构AC分开的工艺形成。
第三层间绝缘层130可以形成在第二层间绝缘层120上。布线MI可以形成在第三层间绝缘层130中，以电连接到接触结构AC和栅极接触GC。
图15至20分别示出了根据示例实施方式的接触结构，并且是图2A的部分M和图2B的部分N的剖视图。将省略与上面参照图1和图2A至2C描述的半导体器件重叠的技术特征的详细描述，并且将更详细地描述不同之处。
参照图15，第一导电图案FM1的上表面FMt可以相对于基板100的上表面低于第一阻挡图案BM1的上表面BMt。相对于基板100的上表面，第二接触CT2的下表面CTb可以低于第一阻挡图案BM1的上表面BMt。在根据示例实施方式的接触结构AC中，第一导电图案FM1可以通过比第一阻挡图案BM1凹进更多而形成。
参照图16，第二接触CT2可以从延伸通过第一接触CT1的轴向中心的第一接触CT1的中心线偏移。第一阻挡图案BM1可以在其第一侧具有第一上表面BMt1。第一阻挡图案BM1可以在其与其第一侧相反的第二侧具有第二上表面BMt2。第一阻挡图案BM1的第二上表面BMt2可以接触第二接触CT2。第一阻挡图案BM1的第二表面BMt2可以相对于基板100的上表面低于其第一表面BMt1。
参照图17，相对于基板100的上表面，第一导电图案FM1的上表面FMt可以高于第一阻挡图案BM1的上表面BMt。相对于基板100的上表面，第二接触CT2的下表面CTb可以高于第一阻挡图案BM1的上表面BMt。第一导电图案FM1的高于第一阻挡图案BM1的上表面BMt定位的上侧壁可以被绝缘层MIL覆盖。在根据示例实施方式的接触结构AC中，第一阻挡图案BM1可以通过比第一导电图案FM1凹进更多而形成。
参照图18，相对于基板100的上表面，第一导电图案FM1的上表面FMt可以高于第一阻挡图案BM1的上表面BMt。第一导电图案FM1的上部UP可以覆盖第一阻挡图案BM1的上表面BMt。换句话说，第一导电图案FM1的横截面可以具有T形。根据示例实施方式的接触结构AC的形成可以包括形成第一阻挡图案BM1，在第一阻挡图案BM1上形成第一导电层，以及使第一导电层凹进以不暴露第一阻挡图案BM1以形成第一导电图案FM1。
参照图19，第二接触CT2可以包括第三阻挡图案BM3和第三导电图案FM3。第三阻挡图案BM3可以插置在第三导电图案FM3和绝缘层MIL之间以及在第三导电图案FM3和第一接触CT1之间。第三阻挡图案BM3可以覆盖第三导电图案FM3的相反侧壁和下表面。第三阻挡图案BM3可以包括金属氮化物。第三导电图案FM3可以包括金属。
参照图20，可以省略在第一接触CT1中的第一阻挡图案BM1。例如，第一接触CT1可以由单一金属材料形成。第二接触CT2可以包括第三阻挡图案BM3和第三导电图案FM3。
尽管已经参考本发明的示例实施方式示出并描述了本发明构思，但是本领域普通技术人员将理解，在不脱离如权利要求所述的本发明构思的精神和范围的情况下，可以对形式和细节进行各种改变。
本申请要求于2018年6月25日向韩国专利局提交的韩国专利申请第10-2018-0072891的优先权，其全部内容通过引用结合在此。

Claims (16)

1.一种半导体器件，包括：
基板，在其中具有有源图案；
栅电极，横跨所述有源图案延伸；
源/漏区，在所述有源图案上，横向邻近所述栅电极；和
接触结构，包括：
在所述源/漏区上的第一接触；
在所述第一接触上的第二接触；和
间隔物，在所述第一和第二接触的侧壁上，并具有与所述第二接触的上表面共面的上表面；
电连接到所述接触结构的布线；和
通孔，设置在所述接触结构和所述布线之间并连接所述布线和所述接触结构，
其中所述第一接触和所述第二接触是导体，
其中所述第一接触包括导电图案和插置在所述导电图案与所述间隔物之间以及在所述导电图案与所述源/漏区之间的阻挡图案。
2.根据权利要求1所述的半导体器件，其中所述接触结构还包括在所述第二接触和所述间隔物之间的绝缘层。
3.根据权利要求1所述的半导体器件，其中所述栅电极沿第一方向纵向延伸，并且其中所述第一接触沿所述第一方向的最大宽度大于所述第二接触沿所述第一方向的最大宽度。
4.根据权利要求1所述的半导体器件，其中所述阻挡图案的上表面与所述导电图案的上表面处于不同的水平。
5.根据权利要求1所述的半导体器件，其中所述导电图案的上部覆盖所述阻挡图案的上表面。
6.根据权利要求1所述的半导体器件，其中所述阻挡图案具有第一上表面和第二上表面，其中所述第二接触接触所述第二上表面，并且其中所述阻挡图案的所述第二上表面低于所述阻挡图案的所述第一上表面。
7.根据权利要求1所述的半导体器件，还包括电连接到所述栅电极的栅极接触，其中所述栅电极沿第一方向纵向延伸，其中所述第一接触包括沿所述第一方向彼此相邻的第一部分和第二部分，其中所述第一接触的所述第一部分在交叉所述第一方向的第二方向上与所述栅极接触相邻，并且其中所述第二接触设置在所述第一接触的所述第二部分上。
8.根据权利要求7所述的半导体器件，其中所述第二接触的上表面与所述栅极接触的上表面共面，并且其中所述第一接触的上表面低于所述栅极接触的下表面。
9.一种半导体器件，包括：
基板，在其中具有有源图案；
栅电极，横跨所述有源图案延伸；
源/漏区，在所述有源图案上，横向邻近所述栅电极；
栅极接触，电连接到所述栅电极；和
接触结构，电连接到所述源/漏区并包括：
在所述源/漏区上的第一接触；
在所述第一接触上的第二接触；和
在所述第一和第二接触的侧壁上的间隔物，
其中所述第二接触的上表面与所述栅极接触的上表面共面，并且其中所述第一接触的上表面低于所述栅极接触的下表面，
其中所述第一接触包括导电图案和插置在所述导电图案与所述间隔物之间以及在所述导电图案与所述源/漏区之间的阻挡图案，
其中所述栅极接触、所述第一接触和所述第二接触是导体。
10.根据权利要求9所述的半导体器件，其中所述接触结构还包括在所述第二接触和所述间隔物之间的绝缘层。
11.根据权利要求9所述的半导体器件，其中所述栅电极沿第一方向纵向延伸，其中所述第一接触包括在所述第一方向上彼此相邻的第一部分和第二部分，其中所述第一接触的所述第一部分在交叉所述第一方向的第二方向上与所述栅极接触相邻，并且其中所述第二接触设置在所述第一接触的所述第二部分上。
12.根据权利要求9所述的半导体器件，其中所述栅电极沿第一方向纵向延伸，并且其中所述第一接触沿所述第一方向的最大宽度大于所述第二接触沿所述第一方向的最大宽度。
13.一种半导体器件，包括：
基板，在其中具有有源图案；
栅电极，沿第一方向横跨所述有源图案纵向延伸；
源/漏区，在所述有源图案上，横向邻近所述栅电极；和
接触结构，包括：
在所述源/漏区上的第一接触；
第二接触，在所述第一接触上并沿所述第一方向具有比所述第一接触的最大宽度小的最大宽度；和
在所述第一接触的侧壁上的绝缘层，
其中所述第一接触和所述第二接触是导体，
其中所述接触结构还包括在所述第一和第二接触的侧壁上的间隔物，并且其中所述绝缘层插置在所述第二接触和所述间隔物之间。
14.根据权利要求13所述的半导体器件，其中所述绝缘层覆盖所述第一接触的上表面的一部分和所述第二接触的侧壁。
15.根据权利要求13所述的半导体器件，还包括电连接到所述栅电极的栅极接触，其中所述第一接触包括在所述第一方向上彼此相邻的第一部分和第二部分，其中所述第一接触的所述第一部分在交叉所述第一方向的第二方向上与所述栅极接触相邻，并且其中所述第二接触设置在所述第一接触的所述第二部分上。
16.根据权利要求15所述的半导体器件，其中所述第二接触的上表面与所述栅极接触的上表面共面，并且其中所述第一接触的上表面低于所述栅极接触的下表面。
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