CN111092047B - 半导体装置以及其制作方法 - Google Patents

半导体装置以及其制作方法 Download PDF

Info

Publication number
CN111092047B
CN111092047B CN201811235109.8A CN201811235109A CN111092047B CN 111092047 B CN111092047 B CN 111092047B CN 201811235109 A CN201811235109 A CN 201811235109A CN 111092047 B CN111092047 B CN 111092047B
Authority
CN
China
Prior art keywords
conductive structure
conductive
opening
layer
lower portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811235109.8A
Other languages
English (en)
Other versions
CN111092047A (zh
Inventor
许得彰
林哲贤
黄正邺
黄俊仁
苏昱志
王尧展
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to CN201811235109.8A priority Critical patent/CN111092047B/zh
Priority to US16/194,379 priority patent/US10700163B2/en
Publication of CN111092047A publication Critical patent/CN111092047A/zh
Priority to US16/878,542 priority patent/US10957762B2/en
Application granted granted Critical
Publication of CN111092047B publication Critical patent/CN111092047B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Geometry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开一种半导体装置以及其制作方法，该半导体装置的制作方法包括下列步骤。提供半导体基底。多个栅极结构形成于半导体基底上。源极/漏极区形成于半导体基底中且形成于多个栅极结构之间。介电层形成于源极/漏极区上且位于多个栅极结构之间。形成开孔贯穿源极/漏极区上的介电层。在开孔中形成第一导电结构的下部。在第一导电结构的下部上以及开孔的内壁上形成介电间隙壁。在开孔中以及第一导电结构的下部上形成第一导电结构的上部。介电间隙壁围绕第一导电结构的上部。以两阶段方式形成第一导电结构可形成围绕上部的介电间隙壁，由此改善半导体装置的电性表现。

Description

半导体装置以及其制作方法
技术领域
本发明涉及一种半导体装置以及其制作方法，尤其是涉及一种具有介电间隙壁的半导体装置以及其制作方法。
背景技术
半导体集成电路的技术随着时间不断地进步成长，每个新世代制作工艺下的产品都较前一个世代具有更小且更复杂的电路设计。在各芯片区域上的功能元件因产品革新需求而必须使其数量与密度不断地提升，当然也就使得各元件几何尺寸需越来越小。举例来说，在场效晶体管(field effect transistor，FET)中，栅极线之间的间距需变得越来越小以提升集成电路的积集度。在栅极线的尺寸以及间距持续缩小的状况下，于栅极线之间或/及栅极线上形成导电插塞的制作工艺容许范围(process window)会非常小，且导电插塞之间的介电材料的时间相依介电质击穿(time dependent dielectric breakdown，TDDB)会随之恶化，导致电性表现以及可靠度受到影响。
发明内容
本发明提供了一种半导体装置以及其制作方法，利用两阶段方式形成第一导电结构，由此于第一导电结构的下部上形成围绕上部的介电间隙壁。介电间隙壁可增加不同导电结构之间的距离，进而达到改善半导体装置的电性表现与可靠度的效果。
本发明的一实施例提供一种半导体装置的制作方法，包括下列步骤。首先，提供一半导体基底。多个栅极结构形成于半导体基底上，一源极/漏极区形成于半导体基底中且形成于多个栅极结构之间，且一介电层形成于源极/漏极区上且位于多个栅极结构之间。形成一开孔贯穿源极/漏极区上的介电层。在开孔中形成一第一导电结构的一下部。在第一导电结构的下部上以及开孔的一内壁上形成一介电间隙壁。在开孔中以及第一导电结构的下部上形成第一导电结构的一上部，且介电间隙壁围绕第一导电结构的上部。
本发明的一实施例提供一种半导体装置，包括一半导体基底、多个栅极结构、一源极/漏极区、一介电层、一开孔、一第一导电结构、一导电阻障层以及一介电间隙壁。栅极结构设置于半导体基底上。源极/漏极区设置于半导体基底中且设置于多个栅极结构之间。介电层设置于源极/漏极区上且位于多个栅极结构之间。开孔贯穿源极/漏极区上的介电层。第一导电结构设置于开孔中。第一导电结构包括一下部以及一上部。上部设置于下部上。导电阻障层设置于开孔中且围绕第一导电结构。介电间隙壁设置于第一导电结构的下部上且围绕第一导电结构的上部。介电间隙壁设置于导电阻障层以及第一导电结构的上部之间。
附图说明
图1至图5为本发明第一实施例的半导体装置的制作方法示意图，其中
图2为图1之后的状况示意图；
图3为图2之后的状况示意图；
图4为图3之后的状况示意图；
图5为图4之后的状况示意图。
图6为本发明第二实施例的半导体装置的示意图。
主要元件符号说明
10 半导体基底
11 沟槽隔离
12 栅极间隙壁
13 源极/漏极区
14 接触蚀刻停止层
15 介电层
21 界面层
22 栅极介电层
23 阻障层
24 第一功函数层
25 第二功函数层
26 第三功函数层
27 第四功函数层
28 栅极电极
29 栅极盖层
30 覆盖层
41 导电阻障层
41A 第一部分
41B 第二部分
42 硅化物层
43 第一导电材料
43A 下部
43B 第二导电结构
44 间隙壁材料层
44S 介电间隙壁
45 第二导电材料
45A 上部
91 蚀刻制作工艺
92 平坦化制作工艺
101-102 半导体装置
CS 第一导电结构
D1 第一方向
D2 第二方向
GS 栅极结构
H1 第一开孔
H2 第二开孔
具体实施方式
以下本发明的详细描述已披露足够的细节以使本领域的技术人员能够实践本发明。以下阐述的实施例应被认为是说明性的而非限制性的。对于本领域的一般技术人员而言显而易见的是，在不脱离本发明的精神和范围的情况下，可以进行形式及细节上的各种改变与修改。
在进一步的描述各实施例之前，以下先针对全文中使用的特定用语进行说明。
用语“在…上”、“在…上方”和“在…之上”的含义应当以最宽方式被解读，以使得“在…上”不仅表示“直接在”某物上而且还包括在某物上且其间有其他居间特征或层的含义，并且“在…上方”或“在…之上”不仅表示在某物“上方”或“之上”的含义，而且还可以包括其在某物“上方”或“之上”且其间没有其他居间特征或层(即，直接在某物上)的含义。
用语“底部”、“下方”、“上方”、“顶部”等是用以描述附图中不同组成元件的相对位置。然而，当将附图翻转使其上下颠倒时，前述的“上方”即成为“下方”。由此可知，本发明中所使用的相对性描述用语可依据设备或设备的方位而定。
在下文中使用术语“形成”或“设置”来描述将材料层施加到基底的行为。这些术语旨在描述任何可行的层形成技术，包括但不限于热生长、溅射、蒸发、化学气相沉积、外延生长、电镀等。
请参阅图1至图5。图1至图5所绘示为本发明第一实施例的半导体装置的制作方法示意图，其中图2绘示了图1之后的状况示意图，图3绘示了图2之后的状况示意图，图4绘示了图3之后的状况示意图，而图5绘示了图4之后的状况示意图。如图5所示，本实施例提供一种半导体装置101的制作方法，包括下列步骤。首先，提供一半导体基底10。多个栅极结构GS形成于半导体基底10上，一源极/漏极区13形成于半导体基底10中且形成于多个栅极结构GS之间，且一介电层15形成于源极/漏极区13上且位于多个栅极结构GS之间。然后，形成一开孔(例如图5中所示的第一开孔H1)贯穿源极/漏极区13上的介电层15。在第一开孔H1中形成一第一导电结构CS的一下部43A。在第一导电结构CS的下部43A上以及第一开孔H1的一内壁上形成一介电间隙壁44S。在第一开孔H1中以及第一导电结构CS的下部43A上形成第一导电结构CS的一上部45A，且介电间隙壁44S围绕第一导电结构CS的上部45A。
更进一步说明，本实施例的半导体装置101的制作方法可包括但并不限于下列步骤。首先，如图1所示，在一些实施例中，半导体基底10可包括硅基底、外延硅基底、硅锗基底、碳化硅基底或绝缘层覆硅(silicon-on-insulator，SOI)基底，但并不以此为限。在一些实施例中，半导体基底10可视需要而具有鳍状结构，而栅极结构GS可设置于半导体基底10的鳍状结构上，但并不以此为限。此外，半导体基底10中可形成有沟槽隔离11，用以隔离多个鳍状结构。沟槽隔离11可由单层或多层的绝缘材料例如氮化硅、氮氧化硅、氮碳化硅或其他适合的绝缘材料所形成。在一些实施例中，各栅极结构GS可包括一界面层21、一栅极介电层22、一阻障层23、单一或多层功函数层(例如图1中所示的第一功函数层24、第二功函数层25、第三功函数层26或/及第四功函数层27)以及一栅极电极28，一栅极盖层29可形成于栅极结构GS上，而各栅极结构GS以及栅极盖层29的侧壁上可形成有一栅极间隙壁12，但并不以此为限。
界面层21可包括氧化硅或其他适合的介电材料。栅极介电层22可包括一高介电常数(high-k)介电层例如氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium siliconoxide，HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化铝(aluminum oxide，Al2O3)、氧化钽(tantalum oxide，Ta2O5)、氧化锆(zirconium oxide，ZrO2)或其他适合的高介电常数材料。第一功函数层24、第二功函数层25、第三功函数层26以及第四功函数层27可分别包括氮化钽(tantalum nitride，TaN)、氮化钛(titaniumnitride，TiN)、碳化钛(titanium carbide，TiC)、铝钛合金(titanium aluminide，TiAl)、碳化钛铝(titanium aluminum carbide，TiAlC)或其他适合的N型或/及P型功函数材料。栅极电极28可包括一低电阻金属材料例如铝(Al)、钨(W)、铜(Cu)、钛铝合金或其他适合的低电阻金属导电材料。栅极盖层29与栅极间隙壁12可分别包括氮化硅、氮碳化硅或其他适合的绝缘材料，且栅极间隙壁12可为单层或多层绝缘材料所构成的结构。
在一些实施例中，栅极结构GS可利用取代栅极(replacement metal gate，RMG)制作工艺所形成，而栅极结构GS可形成于由介电层15与栅极间隙壁12所形成的沟槽中，但并不以此为限。此外，在栅极间隙壁12形成之后，可于半导体基底10中形成源极/漏极区13。源极/漏极区13可包括外延结构、掺杂区或其它适合的源极/漏极结构型态。在一些实施例中，在形成源极/漏极区13之后以及形成介电层15之前，可于栅极间隙壁12上以及源极/漏极区13上共形地形成一接触蚀刻停止层(contact etching stop layer，CESL)14，但并不以此为限。介电层15的材料可包括氧化硅或其他适合的绝缘材料，而接触蚀刻停止层14的材料可包括氮化硅或其它适合的绝缘材料。在一些实施例中，栅极结构GS以及栅极盖层29可于栅极间隙壁12、接触蚀刻停止层14以及介电层15形成之后才形成，但并不以此为限。然后，可形成一覆盖层30覆盖栅极结构GS、栅极盖层29以及介电层15，并于覆盖层30形成之后再形成上述的第一开孔H1。覆盖层30可包括四乙氧基硅烷(tetraethoxysilane，TEOS)或其他适合的绝缘材料。在一些实施例中，第一开孔H1可贯穿位于源极/漏极区13上的接触蚀刻停止层14、介电层15以及覆盖层30，由此暴露出部分的源极/漏极区13。此外，在一些实施例中，可更形成一第二开孔H2贯穿位于栅极结构GS上的覆盖层30以及栅极盖层29，由此暴露出部分的栅极结构GS，但并不以此为限。
在一些实施例中，在第一开孔H1以及第二开孔H2形成之后，可于覆盖层30上、第一开孔H1中以及第二开孔H2中共形地形成一导电阻障层41。部分的导电阻障层41可共形地形成于第一开孔H1的底部以及第一开孔H1的内壁上，且部分的导电阻障层41可共形地形成于第二开孔H2的底部以及第二开孔H2的内壁上。第一开孔H1中的导电阻障层41可被视为导电阻障层41的第一部分41A，而第二开孔H2中的导电阻障层41可被视为导电阻障层41的第二部分41B。在一些实施例中，导电阻障层41可包括钛、氮化钛或其他适合的金属导电材料所构成的单层或多层结构。此外，在一些实施例中，可利用一热制作工艺于导电阻障层41与源极/漏极区13之间形成一硅化物层42，而硅化物层42可包括硅化钛或其他适合的金属硅化物，用以降低源极/漏极区13与第一导电结构的下部之间的接触阻抗，但并不以此为限。
接着，如图2所示，在第一开孔H1中形成第一导电结构的下部43A。换句话说，导电阻障层41可于在形成第一导电结构的下部43A之前形成。在一些实施例中，第一导电结构的下部43A可利用于第一开孔H1中填入第一导电材料43，并对此第一导电材料43进行回蚀刻而形成。第一导电材料43的形成方法可包括化学气相沉积或其他适合的沉积制作工艺，而第一导电材料43可包括电阻率相对较低的材料例如铜、铝、钨等，但并不以此为限。在一些实施例中，也可视需要以其他制作工艺方式形成第一导电结构的下部43A。此外，第一导电结构的下部43A的最上表面(topmost surface)于半导体基底10的厚度方向(例如图2中所示的第一方向D1)上可低于栅极盖层29以及栅极结构GS的上表面，但并不以此为限。
在一些实施例中，部分的第一导电材料43可填入第二开孔H2中，由此于栅极结构GS上形成一第二导电结构43B，且第二导电结构43B与对应的栅极结构GS电连接。换句话说，第二导电结构43B与第一导电结构的下部43A可同时形成，但并不以此为限。在一些实施例中，部分的栅极结构GS可为虚置(dummy)栅极结构(例如图2中左侧的栅极结构)，故可不需于虚置栅极结构上形成第二开孔H2以及第二导电结构43B。此外，在一些实施例中，在利用回蚀刻制作工艺对第一导电结构的下部43A的高度进行调整时，可视需要以掩模(未绘示)覆盖第二导电结构43B，但并不以此为限。因此，第一导电结构的下部43A的上表面(例如其最上表面)可于第一方向D1上低于第二导电结构43B的上表面(例如其最上表面)。
然后，如图3与图4所示，在第一导电结构的下部43A上以及第一开孔H1的内壁上形成介电间隙壁44S。形成介电间隙壁44S的步骤可包括但并不限于先于第一导电结构的下部43A上以及第一开孔H1的内壁上共形地形成一间隙壁材料层44，接着再对间隙壁材料层44进行一蚀刻制作工艺91，用以移除位于第一导电结构的下部43A上的间隙壁材料层44的一部分而形成介电间隙壁44S。换句话说，第一导电结构的下部43A上的间隙壁材料层44的一部分被移除而暴露出部分的第一导电结构的下部43A。在一些实施例中，间隙壁材料层44可包括氮化硅或其他适合的介电材料，而间隙壁材料层44可利用原子层沉积(atomic layerdeposition，ALD)制作工艺或其他适合的成膜制作工艺形成。
之后，如图5所示，在第一开孔H1中以及第一导电结构CS的下部43A上形成第一导电结构CS的上部45A。换句话说，介电间隙壁44S可于形成第二导电结构43B之后以及形成第一导电结构CS的上部45A之前形成。第一导电结构CS的上部45A可与第一导电结构CS的下部43A直接接触且连接，而第一导电结构CS可与对应的源极/漏极区13电连接。此外，介电间隙壁44S可于第一开孔H1中围绕第一导电结构CS的上部45A，且导电阻障层41可于第一开孔H1中围绕介电间隙壁44S以及第一导电结构CS。形成介电间隙壁44S的步骤可包括但并不限于先于覆盖层30上以及第一开孔H1中形成第二导电材料45，使得第一开孔H1被第二导电材料45、介电间隙壁44S、第一导电结构CS的下部43A以及导电阻障层41填满，然后进行一平坦化制作工艺92，用以移除第一开孔H1之外的第二导电材料45而形成第一导电结构CS的上部45A。此外，平坦化制作工艺92可包括化学机械研磨(chemical mechanical polishing，CMP)制作工艺或其他适合的平坦化方法。在一些实施例中，部分的覆盖层30或/及形成于第二导电结构43B上的间隙壁材料层44可一并被平坦化制作工艺92移除，而覆盖层30的上表面可因此具有一凹陷(dishing)，但并不以此为限。
第二导电材料45可包括电阻率相对较低的材料例如铜、铝、钨等，而第二导电材料45的形成方法可包括化学气相沉积或其他适合的沉积制作工艺，但并不以此为限。在一些实施例中，第一导电材料43的组成可与第二导电材料45的组成相同，故第一导电结构CS的上部45A的材料组成可与第一导电结构CS的下部43A的材料组成相同，但并不以此为限。在一些实施例中，也可视需要使用不同的导电材料分别形成第一导电结构CS的下部43A与上部45A。此外，第一导电材料43以及第二导电材料45的电阻率可低于导电阻障层41的电阻率，使得导电阻障层41可使用阻障效果较好的导电材料来形成，但并不以此为限。
通过上述的制作方法，可形成如图5所示的半导体装置101。半导体装置101可包括半导体基底10、多个栅极结构GS、源极/漏极区13、介电层15、第一开孔H1、第一导电结构CS、导电阻障层41以及介电间隙壁44S。栅极结构CS设置于半导体基底10上。源极/漏极区13设置于半导体基底10中且设置于多个栅极结构GS之间。介电层15设置于源极/漏极区13上且位于多个栅极结构GS之间。第一开孔H1贯穿源极/漏极区13上的介电层15。第一导电结构CS设置于第一开孔H1中。第一导电结构CS包括下部43A以及上部45A。上部45A设置于下部43A上。导电阻障层41设置于第一开孔H1中且围绕第一导电结构CS。介电间隙壁44S设置于第一导电结构CS的下部43A上且围绕第一导电结构CS的上部45A。介电间隙壁44S设置于导电阻障层41以及第一导电结构CS的上部45A之间。
在一些实施例中，介电间隙壁44S可于自第一开孔H1的一中心指向多个栅极结构GS其中的一者的方向(例如图5中所示的第二方向D2以及与第二方向D2相反的一方向)上位于第一导电结构CS的上部45A与导电阻障层41之间。介电间隙壁44S可于第一开孔H1中围绕第一导电结构CS的上部45A，而导电阻障层41可于第一开孔H1中围绕介电间隙壁44S以及第一导电结构CS的上部45A与下部43A。在一些实施例中，导电阻障层41的最上表面、介电间隙壁44S的最上表面、第一导电结构CS的上部45A的最上表面、第二导电结构43B的最上表面以及覆盖层30的最上表面可大体上共平面，但并不以此为限。此外，于第一开孔H1中，导电阻障层41的底面以及第一导电结构CS的上部45A的底面可与第一导电结构CS的下部43A的上表面大体上共平面，而第一导电结构CS的下部43A的上表面可于第一方向D1上低于栅极盖层29以及栅极结构GS的上表面，但并不以此为限。
在一些实施例中，半导体装置101可还包括硅化物层42设置于源极/漏极区13与导电阻障层41之间，但并不以此为限。在一些实施例中，半导体装置101可还包括第二导电结构43B设置于多个栅极结构GS其中的一者上且与栅极结构GS电连接。在一些实施例中，第一导电结构CS的下部43A的上表面于半导体基底10的厚度方向(也就是第一方向D1)上可低于第二导电结构43B的上表面。在一些实施例中，半导体装置101可更包括接栅极间隙壁12、接触蚀刻停止层14以及覆盖层30。栅极间隙壁12可设置于栅极结构GS以及栅极盖层29的侧壁上，接触蚀刻停止层14可部分设置于介电层15与栅极间隙壁12之间且部分设置于介电层15与源极/漏极区13之间，而覆盖层30可设置于栅极盖层29以及介电层15上。第一导电结构CS可设置于贯穿覆盖层30、介电层15以及接触蚀刻停止层14的第一开孔H1中，而第二导电结构43B可设置于贯穿覆盖层30以及栅极盖层29的第二开孔H2中。此外，导电阻障层41可包括第一部分41A设置于第一开孔H1中并围绕第一导电结构CS，且导电阻障层41可包括第二部分41B设置于第二开孔H2中并围绕第二导电结构43B，但并不以此为限。通过于第一开孔H1中以分段方式形成第一导电结构CS并于第一导电结构CS的下部43A上形成围绕上部45A的介电间隙壁44S，可加大第一导电结构CS的上部45A与第二导电结构43B之间的距离(例如于第二方向D2上的距离)并改善第一导电结构CS与第二导电结构43B之间的隔离效果，进而可改善半导体装置101的电性表现以及可靠度，例如可改善半导体装置101的时间相依介电质击穿(time dependent dielectric breakdown，TDDB)，但并不以此为限。
下文将针对本发明的不同实施例进行说明，且为简化说明，以下说明主要针对各实施例不同之处进行详述，而不再对相同之处作重复赘述。此外，本发明的各实施例中相同的元件是以相同的标号进行标示，以利于各实施例间互相对照。
请参阅图6。图6所绘示为本发明第二实施例的半导体装置102的示意图。如图6所示，与上述第一实施例不同的地方在于，在半导体装置102中，导电阻障层41于第一方向D1上的最上表面可低于覆盖层30的最上表面。在一些实施例中，介电间隙壁44S可于半导体基底10的厚度方向(也就是第一方向D1)上覆盖导电阻障层41的上表面(例如导电阻障层41的第一部分41A的最上表面)。此外，导电阻障层41的上表面于第一开孔H1中可于第一方向D1上低于第一导电结构CS的上部45A的上表面。在一些实施例中，可于形成间隙壁材料层44之前对导电阻障层41进行蚀刻(例如用以形成第一导电结构CS的下部43A的蚀刻制作工艺，但并不以此为限)而使得导电阻障层41的最上表面低于覆盖层30的最上表面。此外，在一些实施例中，位于第二开孔H2中的导电阻障层41的最上表面可于第一方向D1上低于覆盖层30的最上表面以及第二导电结构43B的最上表面，而第二导电结构43B可于第一方向D1上覆盖导电阻障层41的第二部分41B的最上表面，但并不以此为限。
综上所述，在本发明的半导体装置以及其制作方法中，可于第一开孔中以分段方式形成第一导电结构的下部与上部，由此于第一导电结构的下部上形成围绕上部的介电间隙壁。经由介电间隙壁的设置，可加大对应源极/漏极区的第一导电结构与对应栅极结构的第二导电结构之间的距离并加强第一导电结构与第二导电结构之间的隔离效果，进而可改善半导体装置的电性表现或/及可靠度。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (16)

1.一种半导体装置的制作方法，包括：
提供半导体基底，其中多个栅极结构形成于该半导体基底上，源极/漏极区形成于该半导体基底中且形成于该多个栅极结构之间，且介电层形成于该源极/漏极区上且位于该多个栅极结构之间；
形成开孔贯穿该源极/漏极区上的该介电层；
在该开孔中形成第一导电结构的下部；
在该第一导电结构的该下部上以及该开孔的内壁上形成介电间隙壁；
在该开孔中以及该第一导电结构的该下部上形成该第一导电结构的上部，其中该介电间隙壁围绕该第一导电结构的该上部；以及
在形成该第一导电结构的该下部之前，在该开孔的底部以及该开孔的该内壁上共形地形成导电阻障层，其中，该导电阻障层的最上表面与该介电间隙壁的最上表面共平面。
2.如权利要求1所述的半导体装置的制作方法，其中形成该介电间隙壁的步骤包括：
在该第一导电结构的该下部上以及该开孔的该内壁上共形地形成间隙壁材料层；以及
对该间隙壁材料层进行蚀刻制作工艺，用以移除位于该第一导电结构的该下部上的该间隙壁材料层的一部分而形成该介电间隙壁。
3.如权利要求1所述的半导体装置的制作方法，其中该第一导电结构的该上部的材料组成与该第一导电结构的该下部的材料组成相同。
4.如权利要求1所述的半导体装置的制作方法，其中该导电阻障层于该开孔中围绕该介电间隙壁以及该第一导电结构。
5.如权利要求1所述的半导体装置的制作方法，其中该介电间隙壁于自该开孔的中心指向该多个栅极结构其中的一者的方向上位于该第一导电结构的该上部与该导电阻障层之间。
6.如权利要求1所述的半导体装置的制作方法，还包括：
在该源极/漏极区与该导电阻障层之间形成硅化物层。
7.如权利要求1所述的半导体装置的制作方法，还包括：
在该多个栅极结构其中的一者上形成第二导电结构，该第二导电结构与该栅极结构电连接，其中该第二导电结构与该第一导电结构的该下部同时形成，且该第一导电结构的该下部的上表面于该半导体基底的厚度方向上低于该第二导电结构的上表面。
8.如权利要求7所述的半导体装置的制作方法，其中该介电间隙壁在形成该第二导电结构之后以及形成该第一导电结构的该上部之前形成。
9.如权利要求1所述的半导体装置的制作方法，其中该第一导电结构与该源极/漏极区电连接。
10.一种半导体装置，其特征在于，包括：
半导体基底；
多个栅极结构，设置于该半导体基底上；
源极/漏极区，设置于该半导体基底中且设置于该多个栅极结构之间；
介电层，设置于该源极/漏极区上且位于该多个栅极结构之间；
开孔，贯穿该源极/漏极区上的该介电层；
第一导电结构，设置于该开孔中，其中该第一导电结构包括：
下部；以及
上部，设置于该下部上；
导电阻障层，设置于该开孔中且围绕该第一导电结构；以及
介电间隙壁，设置于该第一导电结构的该下部上且围绕该第一导电结构的该上部，其中该介电间隙壁设置于该导电阻障层以及该第一导电结构的该上部之间，且该导电阻障层的最上表面与该介电间隙壁的最上表面共平面。
11.如权利要求10所述的半导体装置，其中该导电阻障层于该开孔中围绕该介电间隙壁。
12.如权利要求10所述的半导体装置，其中该介电间隙壁于自该开孔的中心指向该多个栅极结构其中的一者的方向上位于该第一导电结构的该上部与该导电阻障层之间。
13.如权利要求10所述的半导体装置，其中该第一导电结构与该源极/漏极区电连接。
14.如权利要求10所述的半导体装置，其中该第一导电结构的该上部的材料组成与该第一导电结构的该下部的材料组成相同。
15.如权利要求10所述的半导体装置，还包括：
硅化物层，设置于该源极/漏极区与该导电阻障层之间。
16.如权利要求10所述的半导体装置，还包括：
第二导电结构，设置于该多个栅极结构其中的一者上且与该栅极结构电连接，其中该第一导电结构的该下部的上表面于该半导体基底的厚度方向上低于该第二导电结构的上表面。
CN201811235109.8A 2018-10-23 2018-10-23 半导体装置以及其制作方法 Active CN111092047B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201811235109.8A CN111092047B (zh) 2018-10-23 2018-10-23 半导体装置以及其制作方法
US16/194,379 US10700163B2 (en) 2018-10-23 2018-11-18 Semiconductor device including conductive structure and manufacturing method thereof
US16/878,542 US10957762B2 (en) 2018-10-23 2020-05-19 Manufacturing method of semiconductor device including conductive structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811235109.8A CN111092047B (zh) 2018-10-23 2018-10-23 半导体装置以及其制作方法

Publications (2)

Publication Number Publication Date
CN111092047A CN111092047A (zh) 2020-05-01
CN111092047B true CN111092047B (zh) 2022-09-27

Family

ID=70279689

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811235109.8A Active CN111092047B (zh) 2018-10-23 2018-10-23 半导体装置以及其制作方法

Country Status (2)

Country Link
US (2) US10700163B2 (zh)
CN (1) CN111092047B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110875237B (zh) * 2018-08-29 2021-12-14 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US11282934B2 (en) * 2019-07-26 2022-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Structure for metal gate electrode and method of fabrication
US11081396B2 (en) * 2019-09-12 2021-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11257755B2 (en) * 2020-06-15 2022-02-22 Taiwan Semiconductor Manufacturing Co., Ltd. Metal loss prevention in conductive structures
US11610982B2 (en) 2020-09-15 2023-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Void elimination for gap-filling in high-aspect ratio trenches
KR20220045314A (ko) * 2020-10-05 2022-04-12 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US12068387B2 (en) * 2021-10-19 2024-08-20 International Business Machines Corporation Multiple threshold voltage scheme in complementary metal oxide semiconductor transistors

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7329599B1 (en) * 2005-03-16 2008-02-12 Advanced Micro Devices, Inc. Method for fabricating a semiconductor device
TW201310577A (zh) * 2011-08-30 2013-03-01 United Microelectronics Corp 電阻及其製作方法
CN107104051A (zh) * 2016-02-22 2017-08-29 联华电子股份有限公司 半导体元件以及其制作方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107189A (en) 1997-03-05 2000-08-22 Micron Technology, Inc. Method of making a local interconnect using spacer-masked contact etch
CN100514596C (zh) * 2006-01-13 2009-07-15 联华电子股份有限公司 金属内连线的制作方法与结构
US8129235B2 (en) 2007-03-15 2012-03-06 United Microelectronics Corp. Method of fabricating two-step self-aligned contact
US8614106B2 (en) * 2011-11-18 2013-12-24 International Business Machines Corporation Liner-free tungsten contact
KR102264160B1 (ko) * 2014-12-03 2021-06-11 삼성전자주식회사 비아 구조체 및 배선 구조체를 갖는 반도체 소자 제조 방법
CN105810565B (zh) * 2014-12-31 2019-07-23 联华电子股份有限公司 形成半导体元件的方法
US9397008B1 (en) 2015-04-21 2016-07-19 United Microelectronics Corp. Semiconductor device and manufacturing method of conductive structure in semiconductor device
US10170358B2 (en) * 2015-06-04 2019-01-01 International Business Machines Corporation Reducing contact resistance in vias for copper interconnects
KR102480447B1 (ko) * 2015-11-20 2022-12-22 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9449921B1 (en) * 2015-12-15 2016-09-20 International Business Machines Corporation Voidless contact metal structures
US10121873B2 (en) * 2016-07-29 2018-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate and contact plug design and method forming same
KR102593561B1 (ko) * 2018-06-25 2023-10-26 삼성전자주식회사 반도체 소자

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7329599B1 (en) * 2005-03-16 2008-02-12 Advanced Micro Devices, Inc. Method for fabricating a semiconductor device
TW201310577A (zh) * 2011-08-30 2013-03-01 United Microelectronics Corp 電阻及其製作方法
CN107104051A (zh) * 2016-02-22 2017-08-29 联华电子股份有限公司 半导体元件以及其制作方法

Also Published As

Publication number Publication date
US20200279917A1 (en) 2020-09-03
US10957762B2 (en) 2021-03-23
US20200127089A1 (en) 2020-04-23
US10700163B2 (en) 2020-06-30
CN111092047A (zh) 2020-05-01

Similar Documents

Publication Publication Date Title
CN111092047B (zh) 半导体装置以及其制作方法
US10157783B2 (en) Semiconductor devices, FinFET devices and methods of forming the same
CN106803484B (zh) 半导体元件及其制作方法
US10262894B2 (en) FinFET device and method for forming the same
CN110299320B (zh) 半导体装置以及其制作方法
US10068797B2 (en) Semiconductor process for forming plug
TWI727068B (zh) 半導體裝置以及其製作方法
US20130285157A1 (en) Semiconductor structure and method for manufacturing the same
CN108231774B (zh) 具有沟槽型器件隔离膜的半导体器件
US20190096679A1 (en) Gate stack processes and structures
US11164948B2 (en) Field-effect transistor and method of manufacturing the same
CN116913964A (zh) 半导体器件
CN107104051B (zh) 半导体元件以及其制作方法
US20210399133A1 (en) Semiconductor device and manufacturing method thereof
US11804436B2 (en) Self-aligned buried power rail cap for semiconductor devices
CN110828377A (zh) 一种具有不对称功函数金属层的半导体元件
CN220710324U (zh) 半导体器件
US11937417B2 (en) Method for forming semiconductor device with composite dielectric structure
US20230042567A1 (en) Reduced parasitic capacitance semiconductor device containing at least one local interconnect passthrough structure
US20230130088A1 (en) Buried power rail with robust connection to a wrap around contact
US20180366552A1 (en) Semiconductor device
CN116613188A (zh) 半导体器件及其制作方法
CN117457498A (zh) 制造半导体器件的方法
CN116598363A (zh) 半导体元件及其制造方法
CN118076096A (zh) 动态随机存取存储器及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant