CN110534422A - 全边切削的晶圆加工方法 - Google Patents

全边切削的晶圆加工方法 Download PDF

Info

Publication number
CN110534422A
CN110534422A CN201810863992.9A CN201810863992A CN110534422A CN 110534422 A CN110534422 A CN 110534422A CN 201810863992 A CN201810863992 A CN 201810863992A CN 110534422 A CN110534422 A CN 110534422A
Authority
CN
China
Prior art keywords
wafer
semiconductor crystal
crystal wafer
periphery
processing method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201810863992.9A
Other languages
English (en)
Inventor
邱垂良
徐坤基
曾仁栋
巫勤达
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Powertech Technology Inc
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Publication of CN110534422A publication Critical patent/CN110534422A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67092Apparatus for mechanical treatment
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043Making grooves, e.g. cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68735Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Dicing (AREA)
  • Grinding Of Cylindrical And Plane Surfaces (AREA)
  • Laser Beam Processing (AREA)

Abstract

一种晶圆加工方法,使用直径小于待加工的半导体晶圆的加工平台。因此,可在半导体晶圆的周边进行全切穿的边缘切削,以于周边形成全切穿的平直面,且于周边形成平坦部,进而在胶带贴合与背面研磨制程利用平坦部作定位。

Description

全边切削的晶圆加工方法
技术领域
本发明关于一种晶圆加工方法,尤指一种进行全边切削及以平坦边缘进行定位的晶圆加工方法。
背景技术
随着晶圆接合加工应用的发展越来越普及,边缘导向加工技术的重要性也随之提高。在已知边缘导向加工技术中,在将晶圆送至下列制程进行处理时,例如半切割、胶带贴合、背面研磨、晶圆黏片等,边缘切削通常应用于晶圆接合元件。边缘切削制程通常移除元件晶圆(device wafer)的直径的一小部分,而非载具晶圆(carrier wafer),以消除元件晶圆上常会发生接合空隙的窄边区域,进而减小最可能造成破裂或其它制程问题的区域。由于晶圆边缘通常是晶圆上最不均匀的区域,因此,将此区域移除将有助于后续的晶圆接合步骤。
然而,现有的边缘切削制程为半切削,进一步来说,由于承载晶圆的平台需考虑刀具的切削深度,因此,边缘切削制程仅会切削晶圆厚度的一半。在对晶圆边缘进行半切削后,晶圆边缘会在后续的胶带贴合制程中留下额外的突出胶带,进而在晶圆边缘留下较差的背面研磨胶带薄层。
此外,晶圆边缘的V形凹槽对于后续制程来说为重要的定位结构。然而,在经过边缘切削制程后,会使晶圆边缘的V形凹槽的尺寸变小甚至消失,进而增加后续制程利用V形凹槽作定位的困难度。
发明内容
根据本发明的一实施例,本发明提供了一种晶圆加工方法,以解决上述问题。全边切削的晶圆加工方法包含下列步骤:提供一半导体晶圆,该半导体晶圆具有一正面以及一背面,该正面与该背面相对,该半导体晶圆还具有一厚度以及一第一直径;提供一加工平台,该加工平台具有一第二直径,该加工平台用以承载该半导体晶圆,其中该第二直径小于该第一直径;对该半导体晶圆的一周边进行边缘切削,以削除具有该厚度的该半导体晶圆的一部分;对该半导体晶圆的该正面进行胶带贴合;以及对该半导体晶圆的该背面进行背面研磨。
根据本发明的另一实施例,晶圆加工方法还包含下列步骤:切削该半导体晶圆的该周边而在该半导体晶圆的该周边形成一平坦部,该平坦部连接于该周边的一弧形部而形成该半导体晶圆的该周边。
根据本发明的另一实施例,切削该半导体晶圆的该周边而在该周边形成该平坦部的步骤是在边缘切削中进行。
根据本发明的另一实施例,对该半导体晶圆的该正面进行胶带贴合的步骤利用该周边的该平坦部作定位。
根据本发明的另一实施例,对该半导体晶圆的该背面进行背面研磨的步骤利用该周边的该平坦部作定位。
根据本发明的另一实施例,对该半导体晶圆的该周边进行边缘切削的步骤在该半导体晶圆的该周边形成一平直面,该平直面连接该正面与该背面。
根据本发明的另一实施例,对该半导体晶圆的该正面进行胶带贴合的步骤包含下列步骤:沿该半导体晶圆的该周边的该平直面切割胶带。
根据本发明的另一实施例,该平直面垂直该正面与该背面。
根据本发明的另一实施例,晶圆加工方法还包含下列步骤:在将该半导体晶圆放置于该加工平台前,对该半导体晶圆的该正面或该背面进行一半切割制程。
根据本发明的另一实施例,该半切割制程包含刀片切割、雷射切割以及隐形切割。
本发明的实施例所述的晶圆加工方法使用直径小于待加工的半导体晶圆的加工平台。因此,可在半导体晶圆的周边进行全切穿的边缘切削,以在周边形成全切穿的平直面,且在周边形成平坦部,进而在胶带贴合与背面研磨制程利用平坦部作定位。因此,可在晶圆边缘提供较佳的背面研磨胶带薄层,以防止边缘破裂。此外,以平坦部取代已知V形凹槽,可使晶圆定位识别更容易。再者,不需考虑刀具形状,可大幅降低用于边缘切削制程的刀具的更换频率。
关于本发明的优点与精神可以借由以下的发明详述及附图得到进一步的了解。
附图说明
在此描述的附图仅用于解释目的,而不意图以任何方式来限制本发明公开的范围。另外,图中的各部件的形状和比例尺寸等仅为示意性的,用于帮助对本发明的理解,并不是具体限定本发明各部件的形状和比例尺寸。本领域的技术人员在本发明的教导下,可以根据具体情况选择各种可能的形状和比例尺寸来实施本发明。
图1为根据本发明一实施例的晶圆加工方法的流程图。
图2为边缘切削制程的一实施例的示意图。
图3为半导体晶圆经过边缘切削前后的俯视图。
图4为对半导体晶圆进行胶带贴合制程的示意图。
附图标记说明:
1 半导体晶圆
3 加工平台
5、6 刀具
7 胶带
11 正面
12 背面
13 平直面
100 晶圆加工方法
110-170 步骤
D1 第一直径
D2 第二直径
P、P' 部分
P1 平坦部
P2 弧形部
T 厚度
W 切削量
具体实施方式
结合附图和本发明具体实施方式的描述,能够更加清楚地了解本发明的细节。但是,在此描述的本发明的具体实施方式,仅用于解释本发明的目的,而不能以任何方式理解成是对本发明的限制。在本发明的教导下,技术人员可以构想基于本发明的任意可能的变形,这些都应被视为属于本发明的范围。
在说明书及权利要求范围当中使用了某些词汇来指称特定的元件。本领域技术人员应可理解,制造商可能会用不同的名词来称呼同一个元件。本说明书及后续的申请专利范围并不以名称的差异来作为区分元件的方式,而是以元件在功能上的差异来作为区分的准则。在通篇说明书及后续的请求项当中所提及的“包含”为一开放式的用语,故应解释成“包含但不限定于”。此外,“耦接”或“连接”一词在此包含任何直接及间接的电气或结构连接手段。因此,若文中描述一第一装置耦接/连接于一第二装置,则代表该第一装置可直接电气/结构连接于该第二装置,或透过其他装置或连接手段间接地电气/结构连接至该第二装置。
请参阅图1,图1为根据本发明一实施例的晶圆加工方法的流程图。晶圆加工方法100为全边切削,适用于边缘切削制程且包含下列步骤:
步骤110:提供一半导体晶圆;
步骤120:对该半导体晶圆的正面或背面进行半切割制程;
步骤130:提供一加工平台,以承载该半导体晶圆;
步骤140:对该半导体晶圆进行边缘切削;
步骤150:在该半导体晶圆的周边形成一平坦部;
步骤160:对该半导体晶圆的该正面进行胶带贴合;
步骤170:对该半导体晶圆的该背面进行背面研磨。
请一并参阅图2,图2为边缘切削制程的一实施例的示意图。步骤110提供一半导体晶圆1。半导体晶圆1具有一正面11以及一背面12,其中正面11与背面12相对。此外,半导体晶圆1具有一厚度T以及一第一直径D1。在一实施例中,在经由本发明的方法处理之前,半导体晶圆1的周边已先经过边缘研磨。在将半导体晶圆1放置于加工平台3前,步骤120对半导体晶圆1的正面11或背面12进行一半切割制程,以减少整体厚度T,在一实施例中,可减少为不大于厚度T的一半。特别地,步骤120中的半切割制程可包含刀片切割(blade cut)、雷射切割(laser grooving)以及隐形切割(stealth dicing),但不以此为限。
在步骤130中,加工平台3用以在后续的边缘切削制程中承载半导体晶圆1。加工平台3具有一第二直径D2,为了使刀具5可在半导体晶圆1上进行全切穿切削制程,加工平台3的第二直径D2小于半导体晶圆1的第一直径D1,特别地,半导体晶圆1与加工平台3的半径差值((D1-D2)/2)不小于所需的切削量,如图2中的W所示。
请参阅图2与图3。图3为半导体晶圆1经过边缘切削前后的俯视图。步骤140中对半导体晶圆1的周边进行全边切削,以削除厚度T(亦即,半导体晶圆1的总厚度)的一部分P。刀具5自背面12至正面11切穿半导体晶圆1的厚度T,以削除部分P,进而于半导体晶圆1的周边形成一平直面13,其中平直面13连接正面11与背面12,且在一实施例中,平直面13垂直正面11与背面12。在步骤150中,借由自半导体晶圆1的周边切除额外的部分P',可进一步在半导体晶圆1的周边形成一平坦部P1。在半导体晶圆1经由步骤140与步骤150处理后,平坦部P1为一平坦边缘且连接于半导体晶圆1的周边的一弧形部P2。在一实施例中,切削半导体晶圆1的周边而形成平坦部P1的步骤150可在步骤140的边缘切削制程中进行。
本发明的实施例公开在对半导体晶圆1进行表面研磨后且对半导体晶圆1进行胶带贴合前,进行全切穿边缘切削制程。请参阅图4,图4为对半导体晶圆进行胶带贴合制程的示意图。在对半导体晶圆1进行边缘切削后,步骤160将一胶带7设置在半导体晶圆1的正面11上。由于先前制程已形成平直面13,因此,用于胶带贴合制程的刀具6可沿着位于半导体晶圆1的周边的平直面13将多余的胶带7切除。需说明的是,对半导体晶圆1的周边进行全切穿边缘切削可在后续制程有效地防止半导体晶圆1的周边产生破裂,且增进生产良率与效益。在进行胶带贴合制程之后,步骤170对半导体晶圆1的背面12进行背面研磨,此为本领域技术人员所熟知的步骤。
在制程中对半导体晶圆1进行定位也至关重要。在进行步骤160、170中的胶带贴合与背面研磨制程之前,半导体晶圆1上需有定位标记,以进行精确定位。不同于已知V形凹槽可能会在边缘切削制程中减小或消失,胶带贴合与背面研磨制程可轻易地利用平坦部P1在边缘切削制程中作定位。
本发明的实施例所述的晶圆加工方法使用直径小于待加工的半导体晶圆的加工平台。因此,可在半导体晶圆的周边进行全切穿的边缘切削,以在周边形成全切穿的平直面,且在周边形成平坦部,进而在胶带贴合与背面研磨制程利用平坦部作定位。
以上所述仅为本发明的较佳实施例,凡依本发明申请专利范围所做的均等变化与修饰,皆应属本发明的涵盖范围。

Claims (10)

1.一种全边切削的晶圆加工方法,其特征在于,所述全边切削的晶圆加工方法包含下列步骤:
提供一半导体晶圆,所述半导体晶圆具有一正面以及一背面,所述正面与所述背面相对,所述半导体晶圆还具有一厚度以及一第一直径;
提供一加工平台,所述加工平台具有一第二直径,所述加工平台用以承载所述半导体晶圆,其中所述第二直径小于所述第一直径;
对所述半导体晶圆的一周边进行边缘切削,以削除具有所述厚度的所述半导体晶圆的一部分;
对所述半导体晶圆的所述正面进行胶带贴合;以及
对所述半导体晶圆的所述背面进行背面研磨。
2.如权利要求1所述的晶圆加工方法,其特征在于,所述全边切削的晶圆加工方法还包含下列步骤:
切削所述半导体晶圆的所述周边而在所述半导体晶圆的所述周边形成一平坦部,所述平坦部连接于所述周边的一弧形部而形成所述半导体晶圆的所述周边。
3.如权利要求2所述的晶圆加工方法,其特征在于,切削所述半导体晶圆的所述周边而在所述周边形成所述平坦部的步骤是在边缘切削中进行。
4.如权利要求2所述的晶圆加工方法,其特征在于,对所述半导体晶圆的所述正面进行胶带贴合的步骤利用所述周边的所述平坦部作定位。
5.如权利要求2所述的晶圆加工方法,其特征在于,对所述半导体晶圆的所述背面进行背面研磨的步骤利用所述周边的所述平坦部作定位。
6.如权利要求1所述的晶圆加工方法,其特征在于,对所述半导体晶圆的所述周边进行边缘切削的步骤在所述半导体晶圆的所述周边形成一平直面,所述平直面连接所述正面与所述背面。
7.如权利要求6所述的晶圆加工方法,其特征在于,对所述半导体晶圆的所述正面进行胶带贴合的步骤包含下列步骤:
沿所述半导体晶圆的所述周边的所述平直面切割胶带。
8.如权利要求6所述的晶圆加工方法,其特征在于,所述平直面垂直所述正面与所述背面。
9.如权利要求1所述的晶圆加工方法,其特征在于,所述全边切削的晶圆加工方法还包含下列步骤:
在将所述半导体晶圆放置于所述加工平台前,对所述半导体晶圆的所述正面或所述背面进行一半切割制程。
10.如权利要求9所述的晶圆加工方法,其特征在于,所述半切割制程包含刀片切割、雷射切割以及隐形切割。
CN201810863992.9A 2018-05-25 2018-08-01 全边切削的晶圆加工方法 Pending CN110534422A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/989,203 US10388535B1 (en) 2018-05-25 2018-05-25 Wafer processing method with full edge trimming
US15/989,203 2018-05-25

Publications (1)

Publication Number Publication Date
CN110534422A true CN110534422A (zh) 2019-12-03

Family

ID=67620671

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810863992.9A Pending CN110534422A (zh) 2018-05-25 2018-08-01 全边切削的晶圆加工方法

Country Status (4)

Country Link
US (1) US10388535B1 (zh)
JP (1) JP2019204940A (zh)
CN (1) CN110534422A (zh)
TW (1) TW202003150A (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110729178A (zh) * 2019-10-18 2020-01-24 记忆科技(深圳)有限公司 一种3d晶圆的加工方法
US11610812B2 (en) * 2019-10-31 2023-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-wafer capping layer for metal arcing protection
DE102020126234B4 (de) * 2019-10-31 2024-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-wafer-abdeckschicht für metalldurchschlagschutz und verfahren zu ihrer herstellung
JP7403919B2 (ja) * 2020-02-27 2023-12-25 株式会社ディスコ 研削方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1278236A1 (en) * 2001-07-09 2003-01-22 Sanyo Electric Co., Ltd. Method of dicing a compound semiconductor wafer and compound semiconductor substrate thereby formed
KR20050003974A (ko) * 2003-07-01 2005-01-12 미쓰비시덴키 가부시키가이샤 반도체 웨이퍼 및 반도체소자의 제조방법
JP2005150200A (ja) * 2003-11-12 2005-06-09 Disco Abrasive Syst Ltd 平面研削方法
JP2007288010A (ja) * 2006-04-19 2007-11-01 Lintec Corp シート切断装置及び切断方法
JP2013115187A (ja) * 2011-11-28 2013-06-10 Disco Abrasive Syst Ltd ウェーハの加工方法
CN103441104A (zh) * 2013-08-29 2013-12-11 华进半导体封装先导技术研发中心有限公司 晶圆切割方法
JP2014239135A (ja) * 2013-06-07 2014-12-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN107818917A (zh) * 2017-09-26 2018-03-20 合肥新汇成微电子有限公司 一种半导体晶圆的切割方法
JP2018049973A (ja) * 2016-09-23 2018-03-29 株式会社岡本工作機械製作所 半導体装置の製造方法及び半導体製造装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG92771A1 (en) * 2000-12-19 2002-11-19 Chee Peng Neo In-process tape bur monitoring
JP4752384B2 (ja) * 2005-08-02 2011-08-17 株式会社東京精密 ウェーハ外周研削方法及びウェーハ外周研削装置
JP2008034776A (ja) * 2006-07-31 2008-02-14 M Tec Kk ワークのエッジの加工方法及び装置
US20080044984A1 (en) 2006-08-16 2008-02-21 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of avoiding wafer breakage during manufacture of backside illuminated image sensors
KR101578956B1 (ko) * 2008-02-22 2015-12-18 니혼 미크로 코팅 가부시끼 가이샤 반도체 웨이퍼 외주 단부의 연삭 방법 및 연삭 장치
US10643853B2 (en) * 2012-02-10 2020-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer thinning apparatus having feedback control and method of using
KR102012538B1 (ko) * 2012-06-12 2019-08-20 에리히 탈너 기판-제품 기판 조합 및 기판-제품 기판 조합을 제조하기 위한 장치 및 방법
US20140054748A1 (en) 2012-08-21 2014-02-27 Genmao Liu Edge trimming method for semiconductor wafer and semiconductor wafer having trimmed edge
WO2014040001A1 (en) * 2012-09-07 2014-03-13 Axus Technology, Llc Method and apparatus for wafer backgrinding and edge trimming on one machine
US20140113452A1 (en) 2012-10-18 2014-04-24 United Microelectronics Corp. Wafer edge trimming method
JP6427320B2 (ja) * 2014-01-27 2018-11-21 株式会社東京精密 ウエハ研削装置及びウエハ製造方法
JP6286256B2 (ja) * 2014-03-31 2018-02-28 株式会社東京精密 ウエハマーキング・研削装置及びウエハマーキング・研削方法
JP2015217461A (ja) * 2014-05-16 2015-12-07 株式会社ディスコ ウェーハの加工方法
JP6583663B2 (ja) * 2015-05-22 2019-10-02 日本電気硝子株式会社 ガラス基板の研削方法
JP6635860B2 (ja) * 2016-04-07 2020-01-29 株式会社ディスコ 加工方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1278236A1 (en) * 2001-07-09 2003-01-22 Sanyo Electric Co., Ltd. Method of dicing a compound semiconductor wafer and compound semiconductor substrate thereby formed
KR20050003974A (ko) * 2003-07-01 2005-01-12 미쓰비시덴키 가부시키가이샤 반도체 웨이퍼 및 반도체소자의 제조방법
JP2005150200A (ja) * 2003-11-12 2005-06-09 Disco Abrasive Syst Ltd 平面研削方法
JP2007288010A (ja) * 2006-04-19 2007-11-01 Lintec Corp シート切断装置及び切断方法
JP2013115187A (ja) * 2011-11-28 2013-06-10 Disco Abrasive Syst Ltd ウェーハの加工方法
JP2014239135A (ja) * 2013-06-07 2014-12-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN103441104A (zh) * 2013-08-29 2013-12-11 华进半导体封装先导技术研发中心有限公司 晶圆切割方法
JP2018049973A (ja) * 2016-09-23 2018-03-29 株式会社岡本工作機械製作所 半導体装置の製造方法及び半導体製造装置
CN107818917A (zh) * 2017-09-26 2018-03-20 合肥新汇成微电子有限公司 一种半导体晶圆的切割方法

Also Published As

Publication number Publication date
US10388535B1 (en) 2019-08-20
JP2019204940A (ja) 2019-11-28
TW202003150A (zh) 2020-01-16

Similar Documents

Publication Publication Date Title
CN110534422A (zh) 全边切削的晶圆加工方法
US5904548A (en) Trench scribe line for decreased chip spacing
US8198705B2 (en) Ultra-thin die and method of fabricating same
US8148240B2 (en) Method of manufacturing semiconductor chips
KR20100110266A (ko) 웨이퍼의 가공 방법
KR20160026860A (ko) 반도체편의 제조 방법, 반도체편을 포함하는 회로 기판 및 화상 형성 장치
JP2006344816A (ja) 半導体チップの製造方法
CN108603077B (zh) 粘接片及其使用方法
JP2017041525A (ja) ウエーハの分割方法
CN108987268A (zh) 晶片的加工方法
CN110098115A (zh) 晶圆的切割方法
EP0776029A1 (en) Improvements in or relating to semiconductor chip separation
JP6509614B2 (ja) ウエーハの分割方法
US20210273001A1 (en) Packaging unit, component packaging structure and preparation method thereof
US9961777B2 (en) Method for cutting a carrier for electrical components
KR20200125444A (ko) 웨이퍼의 브레이크 방법 및 브레이크 장치
JP5911670B2 (ja) 半導体ウエハの製造方法及び半導体ウエハ
JPH1083976A (ja) 半導体装置及び半導体装置の製造方法
JP3276506B2 (ja) 半導体装置の製造方法
JP2003100575A (ja) 半導体ウェハの劈開方法および半導体ウェハ
CN108231571A (zh) 半导体晶圆切割方法
US20150367450A1 (en) Dicing method
KR101866824B1 (ko) 취성 기판의 분단 방법
CN215988667U (zh) 一种晶圆贴膜机的贴膜台
TWI783395B (zh) 晶圓薄化方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20191203