CN110419097B - 半导体元件接合体及其制造方法、半导体装置 - Google Patents

半导体元件接合体及其制造方法、半导体装置 Download PDF

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CN110419097B
CN110419097B CN201780086549.9A CN201780086549A CN110419097B CN 110419097 B CN110419097 B CN 110419097B CN 201780086549 A CN201780086549 A CN 201780086549A CN 110419097 B CN110419097 B CN 110419097B
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semiconductor element
recess
substrate
metal film
metal
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CN110419097A (zh
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山崎浩次
加东智明
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

半导体元件接合体具有设置有凹部的基板、以及在配置于凹部的状态下搭载于基板的半导体元件。基板的设置有凹部的部分由Cu构成。形成于凹部的外周部的台阶的高度d为20[μm]以上且小于50[μm]。当设为激光的波长λ＝632.8[nm]时，凹部的底面的平坦度为λ/8.7[μm]以上且λ/1.2[μm]以下。金属膜设置于半导体元件。凹部的底面与金属膜相互直接接合。

Description

半导体元件接合体及其制造方法、半导体装置
技术领域
本发明涉及电子设备等所使用的半导体元件接合体、半导体装置以及半导体元件接合体的制造方法。
背景技术
以往，已知将包含金属粒子和有机溶剂的金属膏用作接合材料而将半导体芯片接合于基板的半导体装置的制造方法。在这样的以往的半导体装置的制造方法中，在将半导体芯片经由金属膏粘接于基板之后，使有机溶剂从金属膏挥发，使金属膏成为凝集体，在使凝集体中的金属粒子还原之后，将半导体芯片按压到基板而压碎凝集体，从而将半导体芯片接合于基板(例如参照专利文献1)。
另外，以往，还已知半导体元件经由包括金属的固溶体层以及金属层的接合层接合于基板的半导体装置(例如参照专利文献2)。
进而，以往，还已知半导体元件利用粘接剂接合于形成于基板的镀金层的半导体装置(例如参照专利文献3)。
现有技术文献
专利文献
专利文献1：日本特开2012-54358号公报
专利文献2：日本特开2013-187418号公报
专利文献3：日本特开2008-205265号公报
发明内容
但是，在专利文献1以及3所示的以往的半导体装置中，在半导体元件与基板之间存在接合材料或者粘接剂，所以接合材料或者粘接剂成为热阻，由半导体元件产生的热难以传递到基板。由此，半导体元件的散热性恶化。
另外，在专利文献2所示的以往的半导体装置中，半导体元件经由具有固溶体层以及金属层的接合层接合于基板，所以接合层的构造变复杂，对于接合温度、接合时间、各层的厚度的管理花费工夫。因而，缺乏量产性以及接合质量的稳定性。另外，接合层的构造复杂，所以不仅在制造多个半导体装置时各自的接合层的热阻的偏差也变大，而且对于提高半导体元件的散热性也存在界限。
在此，为了实现半导体元件的散热性的提高，优选不经由接合材料而将半导体元件与基板直接接合的固相扩散接合。但是，为了通过固相扩散接合将半导体元件与基板接合，需要对接合半导体元件的基板的接合面进行研磨而使其平滑。因而，当在将半导体元件配置于基板的接合面的状态下用自动设备将半导体元件与基板接合时，由于接合时的振动等而半导体元件相对于基板的位置会偏离。
本发明是为了解决如上所述的课题而完成的，其目的在于得到能够实现半导体元件的散热性的提高、能够抑制产生半导体元件相对于安装部件的位置偏离的半导体元件接合体、半导体装置以及半导体元件接合体的制造方法。
本发明的半导体元件接合体具备设置有凹部的安装部件、以及在配置于凹部的状态下搭载于安装部件的半导体元件，安装部件的设置有凹部的部分由金属构成，形成于凹部的外周部的台阶的高度为20[μm]以上且小于50[μm]，当设为激光的波长λ＝632.8[nm]时，凹部的底面的平坦度为λ/8.7[μm]以上且λ/1.2[μm]以下，金属膜设置于半导体元件，凹部的底面与金属膜相互直接接合。
根据本发明的半导体元件接合体、半导体装置以及半导体元件接合体的制造方法，能够使凹部的底面与金属膜的接合性良好，能够实现半导体元件的散热性的提高。另外，能够抑制产生半导体元件相对于安装部件的位置偏离。
附图说明
图1是示出本发明的实施方式1的半导体装置的剖视图。
图2是示出制造图1的半导体元件接合体时的次序的流程图。
图3是示出未设置图1的凹部的基板的剖视图。
图4是示出进行了针对图3的基板的按压加工的状态的剖视图。
图5是示出在图4的基板形成有凹部的状态的剖视图。
图6是示出半导体元件接合于图5的基板的状态的剖视图。
图7是示出关于比较例1～7以及实施例1～5各自的评价的结果的表。
图8是示出图7的比较例1～7以及实施例1～5各自中的台阶的高度d与H/C后的接合率的关系的曲线图。
图9是示出图7的比较例1～7以及实施例1～5各自中的平坦度λ/a与H/C后的接合率的关系的曲线图。
图10是示出图6的半导体元件的金属膜与基板的第1表面层的接合部的剖面照相(附图代用照相)。
图11是示出在本发明的实施方式2的半导体元件接合体的基板设置有抗蚀剂膜的状态的剖视图。
图12是示出图11的抗蚀剂膜从基板被去除的状态的剖视图。
图13是示出本发明的实施方式3的半导体元件接合体的第1表面层的剖视图。
图14是示出在图13的第1表面层设置有凹部的状态的剖视图。
图15是示出本发明的实施方式4的未设置半导体元件接合体的凹部的金属板的剖视图。
图16是示出进行了针对图15的金属板的按压加工的状态的剖视图。
图17是示出图16的金属板形成有凹部的状态的剖视图。
图18是示出半导体元件接合于图17的金属板的状态的剖视图。
(附图标记说明)
1：半导体装置；2：半导体元件接合体；3：接合材料；4：散热板；5：基板(安装部件)；6：半导体元件；10：凹部；12：金属膜；41：金属板(安装部件)。
具体实施方式
以下，参照附图，说明本发明的实施方式。
实施方式1.
图1是示出本发明的半导体装置的剖视图。在图中，半导体装置1具有半导体元件接合体2、以及经由接合材料3接合于半导体元件接合体2的散热板4。
半导体元件接合体2具有作为安装部件的基板5、以及搭载于基板5的半导体元件6。
作为基板5，使用DBC(Direct Bonded Copper，直接敷铜)基板。基板5具有第1表面层7、第2表面层8、配置于第1表面层7以及第2表面层8间的中间层9。第1表面层7以及第2表面层8分别为由Cu构成的金属层。中间层9为由Si3N4构成的陶瓷层。
第1表面层7以及第2表面层8分别与中间层9用钎料(brazing filler metal)接合。作为将第1表面层7以及第2表面层8分别与中间层9接合的钎料，例如，使用Ag－Cu共晶钎料、或者为了促进与陶瓷的反应而添加有少量的Ti的Ag－Cu－Ti钎料。
在第1表面层7设置有凹部10。因而，基板5的设置有凹部10的部分由金属Cu构成。凹部10设置于第1表面层7的预先设定的设定搭载区域S。当将He－Ne激光的波长设为λ＝632.8[nm]＝0.6328[μm]时，凹部10的底面的平坦度[μm]为(λ/1.2)[μm]以下。在此，平坦度是指从准确的平面偏离的程度。当在相互平行的两个平面之间隔着底面时用两个平面的间隔最小时的两个平面之间的距离表示底面的平坦度。
半导体元件6嵌合于凹部10。由此，半导体元件6配置于基板5的设定搭载区域S。形成于凹部10的外周部的台阶沿着半导体元件6的外周面包围半导体元件6的外周面。形成于凹部10的外周部的台阶的高度d、即凹部10的外周部的深度d为20[μm]以上且小于50[μm]。
散热板4经由包含金属粒子的接合材料3接合于第2表面层8。因而，来自基板5的热经由接合材料3传递到散热板4。传递到散热板4的热从散热板4扩散到外部。
金属膜12设置于半导体元件6。金属膜12介于凹部10的底面与半导体元件6之间。在该例中，仅在与凹部10的底面对置的半导体元件6的接合面形成有金属膜12。另外，在该例中，由Au构成的膜、即Au膜被用作金属膜12。
凹部10的底面与金属膜12相互直接接合。即，金属膜12与第1表面层7直接接合。第1表面层7与金属膜12不经由接合材料，而通过基于固相状态下的金属扩散的接合、即固相扩散接合而相互接合。多个通电用的导线13与半导体元件6连接。
接下来，说明制造半导体元件接合体2的方法。图2是示出制造图1的半导体元件接合体2时的次序的流程图。另外，图3～图6是示出图1的半导体元件接合体2的制造时的状态的剖视图，图3是示出基板5的剖视图，图4是示出进行了针对基板5的按压加工的状态的剖视图，图5是示出在基板5形成有凹部10的状态的剖视图，图6是示出半导体元件6接合于基板5的状态的剖视图。
在制造半导体元件接合体2时，首先，如图3所示，准备作为安装部件的基板5。在该例中，准备DBC基板来作为基板5。
之后，如图4所示，将按压用夹具21的按压面21a压到基板5的第1表面层7的设定搭载区域S，从而对基板5进行按压加工。在该例中，用80MPa以上且120MPa以下的按压压力对基板5进行按压加工。由此，如图5所示，在第1表面层7的设定搭载区域S形成凹部10，制造出设置有凹部10的基板5。按压用夹具21的按压面21a为平坦度高且表面粗糙度低的平滑的面。因而，按压面21a的平坦度通过按压加工转印到基板5的第1表面层7的设定搭载区域S。由此，凹部10的底面的平坦度以及表面粗糙度与按压面21a的平坦度以及表面粗糙度相同(凹部形成工序)。
之后，将设置有金属膜12的半导体元件6嵌合于凹部10。此时，在将金属膜12与凹部10的底面重叠的状态下将半导体元件6配置于凹部10。金属膜12设置于半导体元件6的接合面。凹部10的形状与半导体元件6的接合面的形状相匹配地决定(装配工序)。
之后，在大气中对基板5以及半导体元件6进行加热以及加压，从而将金属膜12与基板5相互直接接合。此时，以比构成基板5的第1表面层7的金属即Cu的融点1083[℃]、以及构成金属膜12的金属即Au的融点1063[℃]分别低的温度对基板5以及半导体元件6进行加热。具体而言，利用200[℃]以上且小于350[℃]的温度、以及1[MPa]以上且小于50[MPa]的加压力，在基板5的第1表面层7与金属膜12之间产生固相状态下的金属扩散，将基板5与金属膜12相互接合(接合工序)。由此，如图6所示，半导体元件接合体2完成。
通过经由接合材料3将散热板4接合于半导体元件接合体2的第2表面层8，并且将多个导线13与半导体元件接合体2的半导体元件6连接，从而制造半导体装置1。
接下来，为了评价半导体元件接合体2的金属膜12与半导体元件6之间的接合状态，如下所述制造出作为样本的半导体元件接合体2。
首先，准备SiC芯片来作为半导体元件6，准备DBC基板来作为基板5。半导体元件6的接合面尺寸为□10[mm]，半导体元件6的厚度为0.35[mm]。在此，“□”为表示正方形的尺寸的尺寸辅助记号。例如“□10[mm]”意味着纵以及横的长度为10[mm]的正方形。
在半导体元件6的接合面形成有金属膜12。通常，在焊料(solder)材料的接合中，根据防止氧化以及焊料的润湿性的观点，将形成于半导体元件的金属膜设为Au膜。在该例中，同样地，作为形成于半导体元件6的接合面的金属膜12，使用Au膜。
关于基板5的平面尺寸，由Cu构成的第1表面层7的平面尺寸为□25[mm]，由Si3N4构成的中间层9的平面尺寸为□29[mm]，由Cu构成的第2表面层8的平面尺寸为□25[mm]。因而，中间层9的平面尺寸比第1表面层7以及第2表面层8各自的平面尺寸大。由此，中间层9的外周部成为不与第1表面层7以及第2表面层8重叠的露出部。中间层9的露出部遍及中间层9的整个周部而从第1表面层7以及第2表面层8突出(29[mm]－25[mm])/2＝2[mm]。第1表面层7的厚度为0.8[mm]，中间层9的厚度为0.32[mm]，第2表面层8的厚度为0.8[mm]。
此外，有时对DBC基板的表面实施外观上光泽性良好的镀Ni或者镀Ag，但在该例中，不对基板5的表面实施镀敷。
之后，准备由作为钢材的SKD11构成的按压用夹具21。考虑半导体元件6的接合面尺寸□10[mm]以及贴片机(mounter)的搭载精度±0.1[mm]，将按压用夹具21的按压面21a的尺寸设为□10.3[mm]。
按压用夹具21的按压面21a的平坦度用基于He－Ne激光的激光干涉仪测定出。以专利文献1为参考，根据通过He－Ne激光的照射而形成的干涉条纹的间距以及干涉条纹的弯曲度来进行基于激光干涉仪的平坦度的测定。此外，平坦度的测定分为使用了千分表(dial gauge)的测定、使用了光学平面(optical flat)的测定以及使用了激光器的测定。在使用了千分表的测定中，将千分表安装于臂部，一边描对象物，一边读取数值的变化，从而测定表面的翘曲以及起伏。在使用了光学平面的测定中，使由具有平坦的测定面的透明玻璃形成的基准标准器具“光学平面”与测定对象的表面接触，根据作为将短波长的光照射到接触面时形成的条纹图案的光波干涉条纹、即牛顿环的根数进行测定。在使用了激光的测定中，将激光照射到测定对象，利用CMOS传感器使其反射光成像而测定。此外，在JIS中，在JIS B 7441定义了测定方法。另外，按照遵循(JIS B0633；2001)的次序，使用触针式表面粗糙度测定机而测定出按压用夹具21的按压面21a的表面粗糙度。
上述测定的结果，当使用He－Ne激光的波长λ＝632.8[nm]＝0.6328[μm]时，按压用夹具21的按压面21a的平坦度大致为(λ/10)[μm]。另外，按压用夹具21的按压面21a的表面粗糙度Ra大致为0.1[μm]，按压用夹具21的按压面21a的表面粗糙度Rz大致为0.2[μm]。在此，Ra以及Rz是指以JIS B 0601－2001(ISO 4287－1997)为规格的表面粗糙度的指标。Ra为算术平均粗糙度。Ra为以基准长度抽出用粗糙度仪测定出的粗糙度曲线的一部分并将其区间的凹凸状体用平均值表示的数值。另外，Rz为最大高度。Rz为以基准长度抽出用粗糙度仪测定出的粗糙度曲线的一部分，在其区间最高的部分即最大山高度Rp与在其区间最深的部分即最大谷深度Rv之和的值。
之后，使用按压用夹具21对基板5的第1表面层7的设定搭载区域S进行按压加工，从而在第1表面层7形成有凹部10(凹部形成工序)。此时，在将温度设为室温25℃、将环境设为大气中的状态下进行基板5的按压加工。通过在用按压用夹具21对第1表面层7施加按压压力的状态下保持时间30[秒]而形成凹部10。针对0、50、60、70、80、90、100、110、120、130、140以及150[MPa]这相互不同的12个种类的按压压力的每个按压压力而制作出各n＝5个在第1表面层7形成有凹部10的样本。
在此，将以0[MPa]的按压压力形成凹部10的样本作为比较例1，将以50[MPa]的按压压力形成凹部10的样本作为比较例2，将以60[MPa]的按压压力形成凹部10的样本作为比较例3，将以70[MPa]的按压压力形成凹部10的样本作为比较例4。同样地，将以80、90、100、110以及120[MPa]的按压压力形成凹部10的各样本分别作为实施例1、实施例2、实施例3、实施例4以及实施例5。另外，将以130、140以及150[MPa]的按压压力形成凹部10的各样本分别作为比较例5、比较例6以及比较例7。
在凹部形成工序之后，通过由SAT(Scanning Acoustic Tomograph，超声波影像装置，探伤的频率10MHz，装置名：日立パワーソリューションズ(Hitachi Power SolutionsCo.,Ltd.)制FineSAT III)进行的观察以及外观观察，针对比较例1～7以及实施例1～5的每一个而做出形成有凹部10的基板5有无基板开裂的判断。具体而言，当在样本的个数n＝5个中的哪怕1个样本中发生基板5的开裂的情况下，都做出有基板开裂的判断(×)，当在样本的个数n＝5个中的所有的样本中都未发生基板5的开裂的情况下，做出没有基板开裂的判断(○)。
另外，针对比较例1～7以及实施例1～5的每一个而用激光变位仪测定出样本的凹部10的台阶的高度d。测定部位设为凹部10的四个角，从n＝5个样本分别获取四个角的台阶的高度中的最大的数值，将获取到的各数值的平均值(单位：μm)设为样本的台阶的高度d而求出。关于样本的台阶的高度d，对小数点以下进行四舍五入。
另外，在凹部形成工序之后，按照与按压用夹具21的按压面21a的平坦度的测定方法同样的方法，针对比较例1～7以及实施例1～5的每一个而对n＝5个样本测定出在凹部形成工序中形成的凹部10的底面的平坦度。即，针对比较例1～7以及实施例1～5的每一个而关于所有的样本测定出凹部10的底面的平坦度。关于平坦度，通常使用用于测定的He－Ne激光的波长λ＝0.6328[μm]和平坦度的指标值a而记载为(λ/a)[μm]。因而，在本实施方式中，也根据各样本的平坦度的测定值来计算平坦度的单独的指标值，针对比较例1～7以及实施例1～5的每一个而计算出n＝5个样本的凹部10的平坦度的单独的指标值的平均值作为平坦度的指标值a。关于平坦度的指标值a，对小数点第2位以下进行四舍五入。另外，关于平坦度λ/a，将对小数点第3位以下进行四舍五入而得到的值用于评价。
之后，在形成于第1表面层7的凹部10通过贴片机而配置半导体元件6(装配工序)。此时，在将金属膜12与凹部10的底面重叠的状态下将半导体元件6配置于凹部10。
在装配工序之后，针对比较例1～7以及实施例1～5的每一个而进行通过装配工序而配置于凹部10的半导体元件6的位置是否从作为目标的设定搭载区域S偏离的判断。具体而言，在半导体元件6的位置从设定搭载区域S偏离0.3[mm]以上的情况、或者半导体元件6从设定搭载区域S旋转2[°]以上的情况下，做出有半导体元件6的位置偏离的判断(×)，在除此以外的情况下，做出没有半导体元件6的位置偏离的判断(○)。
之后，在大气中将用比构成基板5的第1表面层7的金属即Cu的融点1083[℃]、以及构成金属膜12的金属即Au的融点1063[℃]分别低的温度即温度300[℃]对基板5以及半导体元件6进行加热、且用压力30[MPa]对基板5以及半导体元件6进行加压的状态保持5[分钟]，从而在基板5的第1表面层7与金属膜12之间产生固相状态下的金属扩散，将金属膜12与基板5直接接合(接合工序)。这样，制造出作为样本的半导体元件接合体2。
另外，关于完成的半导体元件接合体2，针对比较例1～7以及实施例1～5的每一个而进行金属膜12与基板5的初始接合率[％]是否为目标值以上的判断。具体而言，利用SAT来观察金属膜12与基板5的接合部的剖面，用软件对由SAT得到的图像进行2值化，计算出初始接合率[％]。关于初始接合率，将对小数点以下进行四舍五入而得到的值用于评价。另外，考虑金属膜12与基板5的接合部的热阻而将初始接合率[％]的目标值设定为95[％]。因而，在初始接合率[％]为目标值95[％]以上的情况下，做出接合性良好的判断(○)，在初始接合率[％]小于目标值95[％]的情况下，做出接合性不良的判断(×)。
进而，针对比较例1～7以及实施例1～5的每一个而对完成的半导体元件接合体2进行作为可靠性试验的热循环试验。热循环试验(以下，有时还简称为“H/C”)是对试验对象物重复低温以及高温的试验，是通过判断试验对象物有无产生不良的情况，从而评价试验对象物的可靠性的试验。在此，对半导体元件接合体2进行把将低温－55[℃]保持15分钟的状态和将高温175[℃]保持15分钟的状态重复600次的热循环试验。
另外，关于进行了热循环试验的半导体元件接合体2，针对比较例1～7以及实施例1～5的每一个而进行金属膜12与基板5的接合率[％]是否为目标值以上的判断。即，针对比较例1～7以及实施例1～5的每一个而进行H/C后的接合率[％]是否为目标值以上的判断。具体而言，关于进行了热循环试验的半导体元件接合体2，与初始接合率的计算同样地，利用SAT来观察金属膜12与基板5的接合部的剖面，用软件对由SAT得到的图像进行2值化，计算出H/C后的接合率[％]。然后，在H/C后的接合率[％]为目标值95[％]以上的情况下，做出H/C性良好的判断(○)，在H/C后的接合率[％]小于目标值95[％]的情况下，做出H/C性不良的判断(×)。
图7是示出关于比较例1～7以及实施例1～5的每一个的评价的结果的表。另外，图8是示出图7的比较例1～7以及实施例1～5各自中的台阶的高度d与H/C后的接合率的关系的曲线图。进而，图9是示出图7的比较例1～7以及实施例1～5各自中的平坦度λ/a与H/C后的接合率的关系的曲线图。此外，在图8以及图9中，用白圈表示比较例1～7，用黑圈表示实施例1～5。如图7所示，在凹部形成工序中的按压压力为0[MPa]以上且70[MPa]以下的比较例1～4中，做出有半导体元件6相对于基板5的位置偏离的判断，并且初始接合率小于95[％]，所以还做出接合性不良的判断。另外，在凹部形成工序中的按压压力为130[MPa]以上且150[MPa]以下的比较例5～7中，由于过剩的按压压力而发生基板5的开裂，做出有基板开裂的判断。当发生基板5的开裂时，由H/C施加到接合部的剪应力未正常地施加，所以关于比较例5～7，不进行H/C而判断为NG。
另一方面，在凹部形成工序中的按压压力为80[MPa]以上且120[MPa]以下的实施例1～5中，既未发生基板5的开裂，也未发生半导体元件6相对于基板5的位置偏离，另外，做出接合性以及H/C性都良好的判断。另外，从图7以及图8可知，在实施例1～5中，凹部10的台阶的高度d为20[μm]以上且小于50[μm]。因而，在凹部10的台阶的高度d为20[μm]以上且小于50[μm]的情况下，确认半导体元件6相对于基板5的位置偏离的产生被抑制。进而，从图7以及图9可知，在平坦度的指标值a为1.2以上且8.7以下的情况、即凹部10的底部的平坦度λ/a为λ/8.7以上且λ/1.2以下的情况下，确认金属膜12与基板5的接合性变良好。因而，本实施方式中的凹部10的底部的平坦度λ/a的上限值为λ/1.2，下限值为λ/8.7。此外，关于在凹部形成工序中形成的凹部10的底面的表面粗糙度，在实施例1～5的所有的实施例中，Ra小于0.5[μm]，Rz小于1[μm]。
接下来，作为比较例8，制造用接合材料将基板5与半导体元件6接合的半导体元件接合体。比较例8的基板5使用了以100[MPa]的按压压力设置有凹部10的实施例3的基板5。另外，比较例8的接合材料使用了DOWA ELECTRONICS制的烧结型Ag膏。进而，在比较例8中，也在与比较例1～7以及实施例1～5的接合条件同样的接合条件、即在大气中以温度300℃以及压力30[MPa]保持5[分钟]的条件下，用接合材料将金属膜12与基板5接合。
另外，对比较例8的半导体元件接合体也进行与上述同样的评价。在图7中，除了示出了针对比较例1～7以及实施例1～5的评价结果之外，还示出了针对比较例8的评价结果。从图7可知，在比较例8中，初始接合性为良好，但通过H/C在基板5与半导体元件6的接合部产生裂纹，H/C后的接合率大幅下降，H/C性变不良。
在此，一般被认为在H/C中施加到接合部的剪应力在具有接合层的烧结Ag膏中更加分散，所以经由接合材料将基板与半导体元件接合的半导体元件接合体的H/C性良好。但是，在本评价中为不同的结果。因而，关于实施例1～5，在接合工序之后进行了半导体元件6的金属膜12与基板5的接合部的剖面观察。
图10是示出图6的半导体元件6的金属膜12与基板5的第1表面层7的接合部的剖面照相。在由Au构成的金属膜12与由Cu构成的第1表面层7的接合界面存在平均空孔直径为以上且小于的空孔25。这被认为是因Au与Cu的相互扩散系数的不同所致的科肯德尔效应(Kirkendall effect)或者基板5的表面的微细的凹凸的影响而造成的。
另外，在实施例1～5中，接合环境为大气中，所以在阻碍金属彼此的扩散反应的Cu的氧化膜、即CuO、Cu2O残留于第1表面层7的表面的状态下，不进行氧化膜的去除处理而接合。虽然如此，但在实施例1～5中，半导体元件6的金属膜12与第1表面层7良好地接合被认为是因为金属膜12的Au的扩散快，Au相对于Cu的扩散与第1表面层7的表面处的氧化膜的生长、即Cu以及O的扩散相比起到支配性作用。
在比较例1～7以及实施例1～5中，金属膜12以及第1表面层7通过Au以及Cu的金属扩散而接合。因而，在金属膜12与第1表面层7的界面存在Au以及Cu的固溶层、Au3Cu、AuCu以及AuCu3。
此外，关于将第1表面层7以及第2表面层8各自的厚度设定为在0.1[mm]以上且1.2[mm]以下的范围的相互不同的厚度的多个半导体元件接合体2而进行上述评价，得到同样的结果。
当变更第1表面层7、第2表面层8以及中间层9各自的厚度以及材质时，基板5的等效热膨胀系数改变，由H/C产生于接合部的剪应力也改变。在该例中，用于评价的基板5的热膨胀系数α大致为12.5[ppm]。当将第1以及第2表面层7、8各自的厚度变更为1.2[mm]时，基板5的热膨胀系数α大致为13.6[ppm]，当将第1以及第2表面层7、8各自的厚度变更为0.1[mm]时，基板5的热膨胀系数α大致为5.9[ppm]。因而，只要基板5的热膨胀系数α为6[ppm]以上且13[ppm]以下，即使构成基板5的中间层9的材料不是Si3N4，而是AlN或者Al2O3，也能够得到同样的效果。
在这样的半导体元件接合体2中，凹部10的台阶的高度d为20[μm]以上且小于50[μm]，并且凹部10的底面的平坦度为(λ/8.7)[μm]以上且(λ/1.2)[μm]以下，基板5的设置有凹部10的部分由金属Cu构成，设置于半导体元件6的金属膜12与凹部10的底面相互直接接合，所以能够使凹部10的底面与金属膜12的接合性良好。由此，能够降低半导体元件6的金属膜12与基板5的接合部的热阻，能够实现半导体元件6的散热性的提高。另外，还能够抑制产生半导体元件6相对于基板5的位置偏离。进而，金属膜12与基板5直接接合，所以能够不使用接合材料而将金属膜12与基板5接合，能够容易地且廉价地制造半导体元件接合体2。
另外，在构成金属膜12的材料中包含金属Au，所以能够使得在金属膜12的金属Au与基板5的金属之间容易产生金属扩散，能够将基板5与金属膜12更可靠地接合。
另外，在凹部10的底面与金属膜12的界面存在平均空孔直径为以上且小于的空孔，所以能够将存在于凹部10的底面与金属膜12的界面的空孔的直径限制在一定的范围内。由此，能够良好地保持基板5与金属膜12的接合性，能够进一步实现半导体元件6的散热性的提高。
另外，在半导体装置1中，散热板4经由接合材料3接合于半导体元件接合体2的基板5，所以能够得到与半导体元件接合体2的效果同样的效果，并且能够利用散热板4更可靠地提高半导体元件6的散热性。
另外，在半导体元件接合体2的制造方法中，在制造出设置有凹部10的基板5之后，将半导体元件6配置于凹部10，用200[℃]以上且小于350[℃]的温度、以及1[MPa]以上且小于50[MPa]的加压力将半导体元件6的金属膜12与基板5相互接合，所以能够使凹部10的底面与金属膜12的接合性良好，能够实现半导体元件6的散热性的提高。另外，通过使凹部10形成于基板5，还能够抑制发生半导体元件6相对于基板5的位置偏离。进而，能够不使用接合材料而将金属膜12与基板5接合，能够容易地且廉价地制造半导体元件接合体2。
另外，在将凹部10形成于基板5时，用80[MPa]以上且120[MPa]以下的按压压力对基板5进行按压加工，所以能够防止产生基板5的开裂，并且能够将抑制半导体元件6相对于基板5的位置偏离的凹部10形成于基板5。
实施方式2.
在实施方式1中，在凹部形成工序中通过针对基板5的按压加工将凹部10形成于基板5，但不限定于此，也可以在凹部形成工序中通过针对基板5的蚀刻使凹部10形成于基板5。
即，图11是示出在本发明的实施方式2的半导体元件接合体的基板5设置有抗蚀剂膜31的状态的剖视图。另外，图12是示出图11的抗蚀剂膜31从基板5被去除后的状态的剖视图。在凹部形成工序中，如图11所示，避开设定于基板5的第1表面层7的设定搭载区域S、即设置凹部10的区域，而在第1表面层7设置抗蚀剂膜31。之后，在凹部形成工序中，对第1表面层7的设定搭载区域S进行基于蚀刻液的蚀刻，在第1表面层7的设定搭载区域S设置凹部10。此时，使形成于凹部10的外周部的台阶的高度d成为20[μm]以上且小于50[μm]。另外，此时，利用微细加工用的蚀刻液来调整针对凹部10的底面的蚀刻，使凹部10的底面的平坦度成为(λ/8.7)[μm]以上且(λ/1.2)[μm]以下。之后，在凹部形成工序中，如图12所示，从第1表面层7去除抗蚀剂膜31。由此，制造出设置有凹部10的基板5。其它结构以及次序与实施方式1相同。
这样，通过针对基板5的蚀刻也能够将凹部10形成于基板5。
实施方式3.
图13是示出本发明的实施方式3的半导体元件接合体的第1表面层7的剖视图。另外，图14是示出在图13的第1表面层7设置有凹部10的状态的剖视图。在本实施方式中，如图13以及图14所示，在凹部形成工序中，对与中间层9分离的单独的第1表面层7进行按压加工，从而在第1表面层7的设定搭载区域S形成凹部10。将与实施方式1同样的按压用夹具21压到第1表面层7，进行针对第1表面层7的按压加工。
之后，在凹部形成工序中，将第1表面层7以及第2表面层8分别接合于中间层9，从而如图5所示，制造出设置有凹部10的基板5。一般第1表面层7以及第2表面层8分别与中间层9利用Ag－Cu共晶钎料、或者Ag－Cu－Ti钎料接合，但不限定于此，例如，也可以对第1表面层7以及第2表面层8各个和中间层9实施金属镀敷，不经由钎料而直接接合。其它结构以及次序与实施方式1相同。
这样，当在第1表面层7先形成有凹部10之后，将第1表面层7以及第2表面层8分别接合于中间层9，从而制造出设置有凹部10的基板5，也能够得到与实施方式1同样的效果。
此外，在上述例中，当在第1表面层7形成有凹部10之后，将第1表面层7以及第2表面层8分别接合于中间层9，从而制造出设置有凹部10的基板5，但也可以将第2表面层8与中间层9先接合，之后，将形成有凹部10的第1表面层7接合于中间层9，制造出设置有凹部10的基板5。
另外，在上述例中，对第1表面层7进行按压加工，从而在第1表面层7形成有凹部10，但也可以与实施方式2同样地，对第1表面层7进行蚀刻，从而在第1表面层7形成凹部10。
实施方式4.
图15～图18是示出本发明的实施方式4的半导体元件接合体的制造时的状态的剖视图，图15是示出金属板41的剖视图，图16是示出进行了针对金属板41的按压加工的状态的剖视图，图17是示出在金属板41形成有凹部10的状态的剖视图，图18是示出半导体元件6接合于金属板41的状态的剖视图。
在本实施方式中，不是DBC基板，而是以引线框架为代表的金属板41被用作安装部件。在该例中，金属板41由金属Cu构成。其它结构与实施方式1相同。
半导体元件接合体2按照与实施方式1同样的方法制造。因而，在制造半导体元件接合体2时，如图15所示，在准备作为安装部件的金属板41之后，如图16所示，将按压用夹具21的按压面21a压到金属板41的设定搭载区域S，从而对金属板41进行按压加工。对金属板41进行按压加工时的条件与实施方式1相同。由此，如图17所示，在金属板41的设定搭载区域S形成凹部10，制造出设置有凹部10的金属板41(凹部形成工序)。
之后，与实施方式1同样地，将设置有金属膜12的半导体元件6嵌合于凹部10。此时，在将金属膜12与凹部10的底面重叠的状态下将半导体元件6配置于凹部10(装配工序)。
之后，在大气中对金属板41以及半导体元件6进行加热以及加压，从而将金属膜12与金属板41相互直接接合。将金属膜12与金属板41相互接合时的条件与实施方式1相同(接合工序)。由此，如图18所示，半导体元件接合体2完成。
这样，即使将金属板41用作安装部件，也能够得到与实施方式1同样的效果。
此外，在上述例中，对金属板41进行按压加工，从而将凹部10形成于金属板41，但也可以与实施方式2同样地，对金属板41进行蚀刻，从而将凹部10形成于金属板41。
另外，在各上述实施方式中，将构成按压用夹具21的材料设为作为钢材的SKD11，但不限定于此，只要是比基板5或者金属板41的设置凹部10的部分的材料硬且能够充分地加压的材料，就能够将除了SKD11以外的材料用作按压用夹具21的材料。另外，只要凹部10的底面的平坦度为(λ/8.7)[μm]以上且(λ/1.2)[μm]以下，按压用夹具21的按压面21a的平坦度以及平滑度就也不限定于各实施方式中的值。
另外，在各上述实施方式中，设置于半导体元件6的金属膜12由金属Au构成，但也可以由包含金属扩散系数高的Pt、Pd、Ag以及Cu中的至少任意一个的金属构成金属膜12。通过使用这样的由金属扩散系数高的金属构成的金属膜12，能够以低温且短时间牢固地进行基板5或者金属板41与金属膜12的固相扩散接合，能够与Au同样地提高接合的可靠性。
另外，在各上述实施方式中，也可以将对基板5或者金属板41实施包含Pt、Pd、Ag以及Cu中的至少任意一个的金属镀敷后的基板或者金属板作为安装部件。由此，构成安装部件的凹部10的部分的材料为包含Pt、Pd、Ag以及Cu中的至少任意一个的金属，能够以低温且短时间牢固地进行金属膜12与安装部件的固相扩散接合。
另外，在各上述实施方式中，在接合工序中，以温度300[℃]以及加压力30[MPa]将金属膜12与基板5相互接合，但不限定于此，在接合工序中，只要为200[℃]以上且小于350[℃]的温度、以及1[MPa]以上且小于50[MPa]的加压力，就能够将基板5或者金属板41与金属膜12相互接合。只要接合工序中的温度以及加压力为该范围，接合工序中的加热所致的热损伤以及加压所致的机械损伤就不会在接合工序之后残留于半导体元件6。

Claims (6)

1.一种半导体元件接合体，具备：
安装部件，设置有凹部；以及
半导体元件，在配置于所述凹部的状态下搭载于所述安装部件，
所述安装部件的设置有所述凹部的部分由金属构成，
形成于所述凹部的外周部的台阶的高度为20[μm]以上且小于50[μm]，
当设为激光的波长λ＝632.8[nm]时，所述凹部的底面的平坦度为λ/8.7[μm]以上且λ/1.2[μm]以下，
金属膜设置于所述半导体元件，
所述凹部的底面与所述金属膜相互直接接合。
2.根据权利要求1所述的半导体元件接合体，其中，
在构成所述金属膜的材料中包含Au、Ag、Cu、Pt以及Pd中的至少任意一种金属。
3.根据权利要求1所述的半导体元件接合体，其中，
在构成所述金属膜的材料中包含Au，
在构成所述安装部件的设置有所述凹部的部分的金属中包含Cu，
在所述凹部的底面与所述金属膜的界面存在平均空孔直径为0.1[μm]以上且小于0.4[μm]的空孔。
4.一种半导体装置，具备：
权利要求1～3中的任意一项所述的半导体元件接合体；以及
散热板，经由接合材料接合于所述安装部件。
5.一种半导体元件接合体的制造方法，是制造权利要求1～3中的任意一项所述的半导体元件接合体的方法，其中，所述制造方法具备：
凹部形成工序，制造设置有所述凹部的所述安装部件；
装配工序，在所述凹部形成工序之后，在将设置于所述半导体元件的所述金属膜与所述凹部的底面重叠的状态下将所述半导体元件配置于所述凹部；以及
接合工序，在所述装配工序之后，用200[℃]以上且小于350[℃]的温度、以及1[MPa]以上且小于50[MPa]的加压力将所述金属膜与所述安装部件相互接合。
6.根据权利要求5所述的半导体元件接合体的制造方法，其中，
在所述凹部形成工序中，用80[MPa]以上且120[MPa]以下的按压压力对所述安装部件进行按压加工，从而将所述凹部形成于所述安装部件。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101261964A (zh) * 2007-03-06 2008-09-10 日立金属株式会社 功能元件封装
JP2014053384A (ja) * 2012-09-05 2014-03-20 Toshiba Corp 半導体装置およびその製造方法
JP2015037094A (ja) * 2013-08-12 2015-02-23 アイシン・エィ・ダブリュ株式会社 電子部品モジュール
CN104718615A (zh) * 2012-10-04 2015-06-17 株式会社东芝 半导体电路板及其制造方法和使用其的半导体装置
JP2016115865A (ja) * 2014-12-17 2016-06-23 三菱電機株式会社 電力用半導体装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008205265A (ja) 2007-02-21 2008-09-04 Kyocera Corp 電子部品搭載用基板
JPWO2010095201A1 (ja) * 2009-02-20 2012-08-16 パナソニック株式会社 半導体装置及び半導体装置の製造方法
JP5463205B2 (ja) * 2010-05-27 2014-04-09 日本メクトロン株式会社 フレキシブル回路基板
JP5664028B2 (ja) 2010-08-31 2015-02-04 富士通株式会社 電子装置の製造方法
JP2013187418A (ja) 2012-03-08 2013-09-19 Toshiba Corp 半導体装置およびその製造方法、並びに実装部材
JP5642317B2 (ja) * 2012-03-19 2014-12-17 三菱電機株式会社 半導体装置の製造方法
CN106660120A (zh) * 2014-06-12 2017-05-10 阿尔法金属公司 烧结材料和使用其的固定方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101261964A (zh) * 2007-03-06 2008-09-10 日立金属株式会社 功能元件封装
JP2014053384A (ja) * 2012-09-05 2014-03-20 Toshiba Corp 半導体装置およびその製造方法
CN104718615A (zh) * 2012-10-04 2015-06-17 株式会社东芝 半导体电路板及其制造方法和使用其的半导体装置
JP2015037094A (ja) * 2013-08-12 2015-02-23 アイシン・エィ・ダブリュ株式会社 電子部品モジュール
JP2016115865A (ja) * 2014-12-17 2016-06-23 三菱電機株式会社 電力用半導体装置

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