JP6437162B1 - 半導体素子接合体、半導体装置、及び半導体素子接合体の製造方法 - Google Patents
半導体素子接合体、半導体装置、及び半導体素子接合体の製造方法 Download PDFInfo
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- JP6437162B1 JP6437162B1 JP2018519506A JP2018519506A JP6437162B1 JP 6437162 B1 JP6437162 B1 JP 6437162B1 JP 2018519506 A JP2018519506 A JP 2018519506A JP 2018519506 A JP2018519506 A JP 2018519506A JP 6437162 B1 JP6437162 B1 JP 6437162B1
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Abstract
Description
実施の形態1.
図1は、この発明による半導体装置を示す断面図である。図において、半導体装置1は、半導体素子接合体2と、半導体素子接合体2に接合材3を介して接合されている放熱板4とを有している。
実施の形態1では、凹部形成工程において基板5に対するプレス加工により基板5に凹部10を形成しているが、これに限定されず、凹部形成工程において基板5に対するエッチングにより基板5に凹部10を形成してもよい。
図13は、この発明の実施の形態3による半導体素子接合体の第1の表面層7を示す断面図である。また、図14は、図13の第1の表面層7に凹部10が設けられている状態を示す断面図である。本実施の形態では、図13及び図14に示すように、凹部形成工程において、中間層9から外れた単独の第1の表面層7に対してプレス加工を行うことにより第1の表面層7の設定搭載領域Sに凹部10を形成する。第1の表面層7に対するプレス加工は、実施の形態1と同様のプレス用ジグ21を第1の表面層7に押し付けて行う。
図15〜図18は、この発明の実施の形態4による半導体素子接合体の製造時の状態を示す断面図であり、図15は金属板41を示す断面図、図16は金属板41に対するプレス加工が行われている状態を示す断面図、図17は金属板41に凹部10が形成されている状態を示す断面図、図18は金属板41に半導体素子6が接合されている状態を示す断面図である。
Claims (6)
- 凹部が設けられている実装部材、及び
前記凹部に配置された状態で前記実装部材に搭載されている半導体素子
を備え、
前記実装部材の前記凹部が設けられている部分は、金属で構成されており、
前記凹部の外周部に形成されている段差の高さは、20[μm]以上、50[μm]未満になっており、
レーザの波長λ=632.8[nm]とすると、前記レーザの照射によって形成される干渉縞に基づいて測定される前記凹部の底面の平坦度は、λ/8.7[μm]以上、λ/1.2[μm]以下であり、
前記半導体素子には、金属膜が設けられ、
前記凹部の底面と前記金属膜とは、互いに直接接合されている半導体素子接合体。 - 前記金属膜を構成する材料には、Au、Ag、Cu、Pt及びPdの少なくともいずれかの金属が含まれている請求項1に記載の半導体素子接合体。
- 前記金属膜を構成する材料には、Auが含まれ、
前記実装部材の前記凹部が設けられている部分を構成する金属には、Cuが含まれ、
前記凹部の底面と前記金属膜との界面には、平均空孔径が0.1[μm]以上、0.4[μm]未満の空孔が存在している請求項1に記載の半導体素子接合体。 - 請求項1〜請求項3のいずれか一項に記載の半導体素子接合体、及び
前記実装部材に接合材を介して接合されている放熱板
を備えている半導体装置。 - 請求項1〜請求項3のいずれか一項に記載の半導体素子接合体を製造する方法であって、
前記凹部が設けられている前記実装部材を製造する凹部形成工程、
前記凹部形成工程の後、前記半導体素子に設けられている前記金属膜を前記凹部の底面に重ねた状態で前記半導体素子を前記凹部に配置するマウント工程、及び
前記マウント工程の後、200[℃]以上、350[℃]未満の温度、及び1[MPa]以上、50[MPa]未満の加圧力で、前記金属膜と前記実装部材とを互いに接合する接合工程
を備えている半導体素子接合体の製造方法。 - 前記凹部形成工程では、80[MPa]以上、120[MPa]以下のプレス圧力で前記実装部材に対してプレス加工を行うことにより前記実装部材に前記凹部を形成する請求項5に記載の半導体素子接合体の製造方法。
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WO2013141149A1 (ja) * | 2012-03-19 | 2013-09-26 | 三菱電機株式会社 | 半導体装置の製造方法 |
JP2014053384A (ja) * | 2012-09-05 | 2014-03-20 | Toshiba Corp | 半導体装置およびその製造方法 |
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