JP6665664B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000004020 conductor Substances 0.000 claims description 100
- 239000000758 substrate Substances 0.000 claims description 55
- 238000005304 joining Methods 0.000 claims description 23
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical group Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 230000017525 heat dissipation Effects 0.000 claims description 12
- 239000013078 crystal Substances 0.000 claims description 11
- 239000007790 solid phase Substances 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 description 8
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000005855 radiation Effects 0.000 description 5
- 238000003466 welding Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000005219 brazing Methods 0.000 description 2
- 238000002149 energy-dispersive X-ray emission spectroscopy Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Condensed Matter Physics & Semiconductors (AREA)
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- Materials Engineering (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
本発明の実施の形態に係る半導体装置は、図1(a)及び図1(b)に示すように、放熱ベース2と、放熱ベース2の上面に配置された絶縁回路基板1と、絶縁回路基板1の上面に配置された電極端子3とを備える。図示を省略するが、絶縁回路基板1上には、IGBTやMOSFET等の単体の電力用半導体素子、又はインバータやコンバータ等の回路の少なくとも一部を構成する複数の電力用半導体素子が搭載される。
次に、図6(a)〜図6(c)を参照しながら、本発明の実施の形態に係る半導体装置の製造方法の一例を説明する。
第1の実施例として、50℃、75℃、100℃、125℃で加熱した状態で、第2の導体層12と電極端子3とを超音波接合した試料を作製した。比較例として、熱処理なし(25℃)で超音波接合した試料と、150℃で加熱した状態で超音波接合した試料を作製した。そして、試料毎に、複数の位置においてシェア強度を測定した。測定結果を図7に示す。図7から、加熱温度が高いほどシェア強度は強くなる傾向が読み取れるが、150℃で加熱した試料ではシェア強度のばらつきが急激に大きくなることが分かる。したがって、125℃以下で加熱すれば、接合強度のばらつきの増大を抑制することができる。
第2の実施例として、100℃、125℃で加熱した状態で、第2の導体層12と電極端子3とを超音波接合した試料を作製した。比較例として、熱処理なし(25℃)で超音波接合した試料と、150℃で加熱した状態で超音波接合した試料を作製した。これらの試料について、昇温後で且つ超音波接合前に、エネルギー分散型X線分析(EDX)により酸素(O)の深さ方向のプロファイルを測定した。そして、測定した深さ方向のプロファイルにおいて、Oの検出変化量が1/2になった地点(時間)を酸化膜とCuの界面と規定し、Cuのエッチングレート(SiO2換算にて10.923nm/min)を用い、酸化膜厚として算出した。
第3の実施例として、第2の導体層12の端部と絶縁基板10の端部との距離D3を共通の0.8mmとし、第2の導体層12と電極端子3の距離D1を0.5mm、1.0mmと異ならせて、75℃で加熱した状態で、第2の導体層12と電極端子3とを超音波接合した試料を作製した。比較例として、第2の導体層12と電極端子3の距離D1を0mm、0.2mmとした点が異なる試料を作製した。そして、各試料について、電極端子3直下の絶縁基板10が絶縁破壊されているか否かを測定した。
上記のように、本発明は実施の形態によって記載したが、この開示の一部をなす論述及び図面は本発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかとなろう。
2…放熱ベース
3…電極端子
3a…接合端部
4…接合部材
5…超音波ホーン
10…絶縁基板
11…第1の導体層
12…第2の導体層
Claims (10)
- 放熱ベースと、
前記放熱ベースの上面に接合された第1の導体層と、
前記第1の導体層の上面に接合された窒化アルミニウムからなる絶縁基板と、
前記絶縁基板の上面に接合された第2の導体層と、
一端が折れ曲がって接合端部をなし、前記第2の導体層の上面に対峙した前記接合端部の下面が、固相流動で前記第2の導体層の上面の一部に接合された電極端子
とを備え、前記第2の導体層と前記電極端子との接合界面における結晶粒径が1μm以下であり、前記接合端部の上面に超音波ホーンの加圧痕が残存していることを特徴とする半導体装置。 - 前記第2の導体層及び前記電極端子のそれぞれが銅からなることを特徴とする請求項1に記載の半導体装置。
- 前記絶縁基板の厚さが0.2mm以上1.0mm以下であることを特徴とする請求項1又は2に記載の半導体装置。
- 前記絶縁基板の端部から前記第2の導体層が0.8mm離間し、
前記電極端子が前記第2の導体層の端部から0.5mm以上離間することを特徴とする請求項1〜3のいずれか1項に記載の半導体装置。 - 前記第1の導体層が前記絶縁基板の下面全面を覆うことを特徴とする請求項1〜4のいずれか1項に記載の半導体装置。
- 第1の導体層と、前記第1の導体層の上面に接合された窒化アルミニウムからなる絶縁基板と、前記絶縁基板の上面に接合された第2の導体層とを有する絶縁回路基板を用意する工程と、
前記第1の導体層を放熱ベースに接合する工程と、
一端が折れ曲がって接合端部をなす電極端子を用意し、前記第2の導体層の上面と前記接合端部の下面とを対峙させる工程と
50℃以上125℃以下の範囲で加熱した状態において、超音波で固相流動を生じさせて前記第2の導体層の上面の一部と前記接合端部の下面とを接合する工程
とを含むことを特徴とする半導体装置の製造方法。 - 前記第2の導体層と前記電極端子とを接合する工程により、前記第2の導体層と前記電極端子との接合界面における結晶粒径が1μm以下となることを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記第2の導体層及び前記電極端子のそれぞれが銅からなることを特徴とする請求項6又は7に記載の半導体装置の製造方法。
- 前記絶縁基板の端部から前記第2の導体層が0.8mm離間し、
前記第2の導体層と前記接合端部とを接合する工程は、前記電極端子が前記第2の導体層の端部から0.5mm以上離間するように前記第2の導体層と前記電極端子とを接合することを特徴とする請求項6〜8のいずれか1項に記載の半導体装置の製造方法。 - 前記絶縁回路基板を用意する工程は、前記絶縁基板の下面全面を覆うように前記第1の導体層を形成することを含むことを特徴とする請求項6〜9のいずれか1項に記載の半導体装置の製造方法。
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JP2016089818A JP6665664B2 (ja) | 2016-04-27 | 2016-04-27 | 半導体装置及びその製造方法 |
US15/453,032 US10090223B2 (en) | 2016-04-27 | 2017-03-08 | Semiconductor device and method of manufacturing same |
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JP5672707B2 (ja) * | 2010-02-01 | 2015-02-18 | 富士電機株式会社 | 半導体装置の製造方法 |
JP5082081B2 (ja) | 2010-07-20 | 2012-11-28 | 株式会社アドウェルズ | 超音波振動接合装置 |
JP2013051366A (ja) * | 2011-08-31 | 2013-03-14 | Hitachi Ltd | パワーモジュール及びその製造方法 |
US8563364B2 (en) * | 2011-09-29 | 2013-10-22 | Infineon Technologies Ag | Method for producing a power semiconductor arrangement |
CN105190858B (zh) * | 2013-04-25 | 2018-11-06 | 富士电机株式会社 | 半导体装置及半导体装置的制造方法 |
DE102013211405B4 (de) * | 2013-06-18 | 2020-06-04 | Infineon Technologies Ag | Verfahren zur herstellung eines halbleitermoduls |
JP6116452B2 (ja) * | 2013-09-10 | 2017-04-19 | 三菱電機株式会社 | 電力用半導体装置の製造方法、電力用半導体装置および電力変換装置 |
JP2015069982A (ja) | 2013-09-26 | 2015-04-13 | 株式会社日立製作所 | パワーモジュール |
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