CN110277314A - 蚀刻SiGe前的预处理组合物和制造半导体器件的方法 - Google Patents

蚀刻SiGe前的预处理组合物和制造半导体器件的方法 Download PDF

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CN110277314A
CN110277314A CN201910127992.7A CN201910127992A CN110277314A CN 110277314 A CN110277314 A CN 110277314A CN 201910127992 A CN201910127992 A CN 201910127992A CN 110277314 A CN110277314 A CN 110277314A
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acid
alkyl
aryl
sige
pattern
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CN110277314B (zh
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金秀珍
李孝善
吴政玟
李晓山
金东铉
金学秀
吴政宰
李明护
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Samsung Electronics Co Ltd
ENF Technology CO Ltd
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Abstract

提供了蚀刻SiGe前使用的预处理组合物,该组合物包括:酸;醇;具有化学式R‑Si(R1)n(OR2)3‑n的硅烷化合物,其中,R是(C3‑C20)烷基、(C6‑C12)芳基、(C6‑C12)芳基(C3‑C20)烷基或(C3‑C20)烷基(C6‑C12)芳基,R1是氢、羟基、卤素、(C1‑C20)烷基、卤代(C1‑C20)烷基、(C6‑C12)芳基、(C6‑C12)芳基(C1‑C20)烷基或(C1‑C20)烷基(C6‑C12)芳基,R2是氢、(C1‑C20)烷基、卤代(C1‑C20)烷基、(C6‑C12)芳基、(C6‑C12)芳基(C1‑C20)烷基或(C1‑C20)烷基(C6‑C12)芳基。

Description

蚀刻SiGe前的预处理组合物和制造半导体器件的方法
于2018年3月15日在韩国知识产权局提交的发明名称为“蚀刻SiGe前的预处理组合物和使用其制造半导体器件的方法”的第10-2018-0030385号韩国专利申请通过引用全部包含于此。
技术领域
实施例涉及在蚀刻SiGe之前使用的预处理组合物和使用该组合物制造半导体器件的方法。
背景技术
随着器件不断按比例缩小以实现更高的集成度,因为传统的MOS架构会正在接近实际的缩小限制,所以正在考虑新的结构和工艺。
发明内容
实施例涉及在蚀刻SiGe之前使用的预处理组合物,该组合物包括酸、醇和下面式1的硅烷化合物:
<式1>
R-Si(R1)n(OR2)3-n
在式1中,R是(C3-C20)烷基、(C6-C12)芳基、(C6-C12)芳基(C3-C20)烷基或(C3-C20)烷基(C6-C12)芳基,R1是氢、羟基、卤素、(C1-C20)烷基、卤代(C1-C20)烷基、(C6-C12)芳基、(C6-C12)芳基(C1-C20)烷基或(C1-C20)烷基(C6-C12)芳基,R2是氢、(C1-C20)烷基、卤代(C1-C20)烷基、(C6-C12)芳基、(C6-C12)芳基(C1-C20)烷基或(C1-C20)烷基(C6-C12)芳基,n是0至2的整数,R中的烷基、芳基、芳基烷基或烷基芳基和R1中的烷基、卤代烷基、芳基、芳基烷基或烷基芳基可以进一步取代有选自于卤素、羟基、-N(R11)(R12)和-S(R13)中的一个或更多个取代基,其中,R11、R12和R13中的每个独立地为氢或(C1-C20)烷基。
实施例还涉及一种制造半导体器件的方法,所述方法包括:在半导体基底上形成绝缘图案、硅图案和SiGe图案;供应根据实施例的预处理组合物,以在绝缘图案上形成钝化层;使用SiGe蚀刻组合物蚀刻SiGe图案。
附图说明
通过参照附图详细描述示例实施例,特征对于本领域技术人员而言将变得明显,在附图中:
图1和图3示出了根据示例实施例的制造半导体器件的工艺中的阶段的剖视图;
图2示出了示出根据示例实施例的预处理组合物对氧化硅层的表面的作用原理的图;
图4A至图17A示出了示出根据示例实施例的按顺序制造半导体器件的工艺中的阶段的透视图;以及
图4B至图17B分别示出了沿图4A至图17A的线A-A'和B-B'截取的剖视图。
具体实施方式
在下文中,将参照附图详细说明示例实施例。
图1和图3示出了根据示例实施例的按顺序制造半导体器件的工艺中的阶段的剖视图。图2示出了根据示例实施例的预处理组合物对氧化硅层的表面的作用原理的图。
参照图1,可以在半导体基底100上形成绝缘图案102、硅图案104和硅锗(SiGe)图案106。可以通过沉积工艺、蚀刻工艺等形成绝缘图案102、硅图案104和SiGe图案106。绝缘图案102可以是氧化硅层、氮化硅层、氮氧化硅层和金属氧化物层中的至少一种。例如,绝缘图案102可以形成为氧化硅层。
根据示例实施例,可以将预处理组合物供应到半导体基底100上,以在绝缘图案102上形成钝化层108a和108b。由于预处理组合物与绝缘图案102的表面之间的化学反应,钝化层108a和108b可以仅形成在绝缘图案102上,并且可以不形成在硅图案104和SiGe图案106的表面上。
根据本示例实施例,预处理组合物可以包括酸、醇和下面式1的硅烷化合物。
<式1>
R-Si(R1)n(OR2)3-n
在式1中,R可以是(C3-C20)烷基、(C6-C12)芳基、(C6-C12)芳基(C3-C20)烷基或(C3-C20)烷基(C6-C12)芳基,R1可以是氢、羟基、卤素、(C1-C20)烷基、卤代(C1-C20)烷基、(C6-C12)芳基、(C6-C12)芳基(C1-C20)烷基或(C1-C20)烷基(C6-C12)芳基,R2可以是氢、(C1-C20)烷基、卤代(C1-C20)烷基、(C6-C12)芳基、(C6-C12)芳基(C1-C20)烷基或(C1-C20)烷基(C6-C12)芳基,n可以是0至2的整数,R中的烷基、芳基、芳基烷基或烷基芳基以及R1中的烷基、卤代烷基、芳基、芳基烷基或烷基芳基可以进一步取代有选自于卤素、羟基、-N(R11)(R12)和-S(R13)中的一个或更多个取代基,其中,R11、R12和R13中的每个可以独立地为氢或(C1-C20)烷基。
在预处理组合物中,可以包括约0.01wt%至约20wt%的量的酸,可以包括约1wt%至约90wt%的量的醇,并且可以包括约0.01wt%至约5wt%的量的硅烷化合物。预处理组合物还可以包括0wt%至约98.98wt%的量的去离子水。例如,在预处理组合物中,可以包括约0.01wt%至约10wt%的量的酸,可以包括约10wt%至约70wt%的量的醇,并且可以包括约0.01wt%至约3wt%的量的硅烷化合物。可以包括约17wt%至约89.98wt%的量的去离子水。例如,在预处理组合物中,可以包括约0.01wt%至约5wt%的量的酸,可以包括约30wt%至约70wt%的量的醇,并且可以包括约0.05wt%至约1wt%的量的硅烷化合物。可以包括约24wt%至约69.94wt%的量的去离子水。
例如,在式1中,R可以是(C3-C20)烷基、卤代(C3-C20)烷基或(C6-C12)芳基,R1和R2中的每个可以独立地为氢、(C1-C20)烷基或(C6-C12)芳基。
例如,在式1中,R2可以是(C1-C20)烷基,并且n可以是0。
硅烷化合物可以包括由下面的式(1-1)至式(1-7)中的一个来表示的化合物。
在说明书中,“烷基”、“烷氧基”和包括“烷基”部分的其它取代基可以包括直链型和支链型两者,并且可以具有1-20个碳原子,例如,1-15个碳原子,例如,1-10个碳原子。
在说明书中,“芳基”是从其去除一个氢原子的芳烃的有机官能团,并且可以具有适当地包括4-7个成环碳原子的单环或稠环结构,例如,每个环中5个或6个成环碳原子。此外,说明书中的“芳基”可以包括其中芳基基团经由单键连接的结构,但不限于此。
在说明书中,“芳基烷基”可以是其中一个或更多个氢原子被芳基基团取代(具体地,被苄基基团取代,但不限于此)的烷基。在说明书中,“烷基芳基”可以指其中一个或更多个氢原子被烷基基团取代的芳基。在说明书中,“卤代烷基”可以指其中一个或更多个氢原子被卤素基团取代(具体地,被三氟甲基基团取代,但不限于此)的烷基。
酸可以是无机酸、有机酸或其混合物。例如,酸可以包括氢氟酸、盐酸、硼酸、硫酸、硝酸、磷酸、过氧化氢、乙酸、丙酸、二乙酸、甲酸、丁酸、柠檬酸、乙醇酸、草酸、丙二酸、戊酸、酒石酸、葡萄糖酸、琥珀酸、亚氨基二乙酸、甲磺酸、乙磺酸、乳酸、抗坏血酸、缬草酸、丁基乙酸(butyl acetic acid)、庚酸、癸酸、苹果酸、马来酸、戊二酸、己二酸、D-葡萄糖酸、衣康酸、柠康酸、中康酸、2-氧代戊二酸、偏苯三酸、茵多酸、谷氨酸和甲基琥珀酸中的一种或更多种。例如,酸可以是硫酸或乙酸。
醇可以是伯醇、仲醇、叔醇或其混合物。例如,醇可以包括甲醇、乙醇、丙醇、异丙醇、丁醇、异丁醇、叔丁醇、2-甲氧基乙醇、1-甲氧基-2-丙醇、3-甲氧基-1-丁醇、戊醇、己醇、2-乙基-1-己醇、庚醇、辛醇、乙二醇、丙二醇、丁二醇、己二醇、四氢糠醇、1,2-丁二醇和1,4-丁二醇中的一种或更多种。例如,醇可以是甲醇、乙醇、丙醇、异丙醇、丁醇和异丁醇中的一种或更多种。
在不受理论束缚的情况下,参照图2,在使用氧化硅层形成绝缘图案102的情况下,在氧化硅层的表面上可以存在-OH基团,并且-OH基团之间可以存在脱水位点。在这种情况下,如果将预处理组合物供应到半导体基底100上,则预处理组合物中包括的酸可以为脱水位点提供氢原子以进行羟基化。预处理组合物中包括的醇可以有助于预处理组合物中的硅烷化合物彻底溶解。如此溶解的硅烷化合物可以经由氢键与羟基化的氧化硅层的氢结合。因此,硅烷化合物可以形成第一钝化层108a。
为了增强硅烷化合物与氧化硅层之间的结合力,可以针对第一钝化层108a另外地执行加热或光照射。可以在例如约70℃至约200℃的温度下执行加热工艺约0.1分钟至约30分钟,例如,在约80℃至约120℃的温度下执行加热工艺约0.5分钟至约3分钟。可以用具有约100nm至约400nm的波长的光执行光照射约0.1分钟至约30分钟,例如,用具有约200nm至约400nm的波长的光执行光照射约0.5分钟至约3分钟。可以使用用于光照射的合适光源。例如,可以使用紫外光。
在执行加热或光照射的情况下,形成第一钝化层108a的硅烷化合物的-OH基团和氧化硅层的表面上的-OH基团的氢原子可以在缩合反应中结合以形成水(H2O),处于脱羟基状态的硅烷化合物可以通过共价键与氧化硅层表面上的氧原子结合。处于这种状态的硅烷化合物可以形成第二钝化层108b。第一钝化层108a的表面和第二钝化层108b的表面可以是疏水的。
参照图3,在形成了第一钝化层108a或第二钝化层108b的状态下,可以通过供应SiGe蚀刻组合物来蚀刻SiGe图案106。然后,可以完全去除SiGe图案106,并且可以暴露半导体基底100的表面和硅图案104的侧壁。可以同时去除第一钝化层108a和/或第二钝化层108b。
SiGe蚀刻组合物可以包括例如酸、氧化剂和去离子水。SiGe蚀刻组合物还可以包括表面活性剂。
例如,SiGe蚀刻组合物中包括的酸可以包括氢氟酸和乙酸。氧化剂可以包括例如过乙酸(PAA)和硝酸中的至少一种。表面活性剂可以包括例如月桂醇环氧乙烷(laurylalcohol ethylene oxide,月桂醇聚氧乙烯醚)。
在不受理论束缚的情况下,当供应这样的SiGe蚀刻组合物时,其中包括的氧化剂可以键合到SiGe的锗原子以形成氧化锗,并且SiGe蚀刻组合物中包括的氢氟酸可以与氧化锗(GeOx)反应,以形成氟化锗(例如,GeF4)。通过该过程,可以从SiGe中去除锗原子。可以从SiGe中去除锗原子并且可以保留硅原子,并且保留的硅原子可以与氧化剂结合以形成氧化硅。类似地,氧化硅可以与氢氟酸结合以形成氟化硅(SiF4)和二氢氟化硅(H2SiF6)或六氟硅酸。通过这些过程,可以蚀刻SiGe图案106。SiGe蚀刻组合物中包括的酸、氧化剂和去离子水是亲水的。因此,可以减少与第一钝化层108a或第二钝化层108b的疏水的表面的反应性。因此,由于第一钝化层108a和/或第二钝化层108b,SiGe蚀刻组合物可以不太可能与绝缘图案102接触,并且可以减少绝缘图案102的蚀刻。
提供下面的示例和对比示例,以突出一个或更多个实施例的特性,但将理解的是,示例和对比示例不应解释为限制实施例的范围,对比示例也不应被解释为在实施例的范围之外。此外,将理解的是,实施例不限于示例和对比示例中描述的具体细节。
<实验示例1至实验示例6和对比示例1至对比示例3>
按照下面执行实验。首先,制备示例和对比示例的预处理组合物,以具有如表1中所示的各种组分。在约25℃下制备预处理组合物。
在表1中,IPA表示异丙醇,EtOH表示乙醇。
硅烷化合物1-4、1-6和1-7的种类对应于上面说明的化学结构,即对应于:
通过使用在蚀刻SiGe之前使用的预处理组合物执行预处理来检验蚀刻结果的变化。首先,在裸晶圆上形成多晶硅(p-Si)薄膜、氧化硅(SiO2)薄膜和硅锗(SiGe)薄膜中的每个以制备样品。通过使用椭圆偏振计(J.A.WOLLOLLAM Co.,M-2000U)来测量制备的样品的薄膜的厚度。
使用测量了其厚度的样品,如下执行实验示例和对比示例。在实验示例1至实验示例6中,使用预处理组合物预处理样品约1分钟,用氮气干燥,使用SiGe蚀刻组合物处理约1分钟,用超纯水洗涤,并用氮气干燥。然后,通过使用椭圆偏振计测量每个薄膜的厚度,并计算蚀刻速率。在对比示例1至对比示例3中,在不使用预处理组合物进行预处理的情况下使用SiGe蚀刻组合物处理样品约1分钟,用超纯水洗涤,并用氮气干燥。然后,使用椭圆偏振计测量每个薄膜的厚度,并计算蚀刻速率。详情示于表1中。
制备三种SiGe蚀刻组合物:
SiGe蚀刻组合物1包括体积比为1.5:30:30:30的HF、PAA、乙酸和去离子水。
通过向SiGe蚀刻组合物1中添加约0.1vol%的月桂醇环氧乙烷作为非离子表面活性剂来获得SiGe蚀刻组合物2。
SiGe蚀刻组合物3包括约41.3wt%的硝酸、约0.6wt%的氢氟酸、约2.1wt%的乙酸和约56wt%的去离子水。
表1中示出了蚀刻速率的实验结果。
[表1]
参照表1,发现与对比示例相比,实验示例1至实验示例6显示出对于氧化硅明显低的蚀刻速率。另一方面,发现对于对比示例和实验示例,对于多晶硅(p-Si)的蚀刻速率或对于硅锗(SiGe)的蚀刻速率几乎相同或相似。因此,如果在使用根据示例实施例的预处理组合物执行预处理工艺之后蚀刻SiGe,则可以选择性地去除SiGe,同时使氧化硅层和硅的蚀刻损坏最小化。
<实验示例7至实验示例9>
在这些实验中,检验在具有第一钝化层108a的图2的状态下伴随着加热或光照射的效果。在这些实验中,使用与实验示例1中使用的预处理组合物1和SiGe蚀刻组合物1相同的预处理组合物1和SiGe蚀刻组合物1,并且在供应SiGe蚀刻组合物之前使用预处理组合物1执行预处理工艺之后执行加热或光照射工艺。使用加热板执行加热,并使用紫外灯执行光照射。表2中示出了结果。
[表2]
参照表2,发现相对于实验示例1,实验示例7至实验示例9(其中,另外执行加热或光照射)中的对于氧化硅层的蚀刻速率降低了。结果,在不受理论束缚的情况下,认为图2的第二钝化层108b与氧化硅层的表面之间的结合力变得比第一钝化层108a与氧化硅层的表面之间的结合力强。此外,发现如果在使用根据示例实施例的预处理组合物执行预处理工艺之后蚀刻SiGe,则可以选择性地去除SiGe,同时使氧化硅层和硅的蚀刻损坏最小化。
在下面的实验示例中,制备相对于上述实验示例的具有各种范围的各种组分的预处理组合物,并检验通过应用这些组合物获得的结果。
首先,如表3中另外地制备预处理组合物。在表3中,硅烷化合物1-1对应于:
[表3]
在实验示例10至实验示例20中,在供应如用于实验示例7的预处理组合物之后,使用加热板在100℃/60秒的条件下执行加热,并且使用SiGe蚀刻组合物1执行蚀刻处理约1分钟,然后获得蚀刻速率。
参照表3,通过应用根据示例的预处理组合物获得的结果显示出比对比示例1至对比示例3明显低的对于氧化硅层的蚀刻速率。此外,当与对比示例比较时,从实验示例1至实验示例20,发现如果使用根据示例实施例的具有约0.01wt%至约20wt%的酸、约1wt%至约90wt%的醇和约0.01wt%至约5wt%的硅烷化合物的预处理组合物执行预处理工艺,则获得了优异的效果。
现在,将描述通过使用根据示例实施例的预处理组合物制造具有多桥沟道(MBC)MOSFET结构的半导体器件的方法。
图4A至图17A示出了根据示例实施例的按顺序制造半导体器件的工艺中的阶段的透视图。
图4B至图17B分别示出了沿图4A至图17A的线A-A'和线B-B'截取的剖视图。
参照图4A和图4B,准备半导体基底1。可以使用硅单晶形成半导体基底1,或者半导体基底1可以是绝缘体上硅(SOI)基底。可以在半导体基底1中形成掺杂有第一导电类型杂质的阱区。可以在与半导体基底1的表面相邻的区域中形成沟道停止区3。可以通过例如离子注入工艺来形成沟道停止区3。沟道停止区3可以掺杂有例如第一导电类型杂质。沟道停止区3中的杂质浓度可以高于阱区。可以在半导体基底1上交替地堆叠SiGe层5和硅层7。可以通过沉积工艺形成SiGe层5和硅层7。
参照图5A和图5B,可以使硅层7和SiGe层5顺序地图案化以形成暴露半导体基底1的第一沟槽9。也可以使沟道停止区3图案化并且可以使沟道停止区3暴露于第一沟槽9的侧壁。可以通过各向异性蚀刻工艺来执行使硅层7和SiGe层5顺序地图案化的工艺。
参照图6A和图6B,可以堆叠绝缘层以填充第一沟槽9,并且可以执行平坦化工艺以暴露硅层7中的最上面的硅层7并且同时在第一沟槽9中形成器件隔离层11。器件隔离层11可以包括例如氧化硅层。尽管未示出,但是可以在器件隔离层11与第一沟槽9的侧壁和底表面之间插入绝缘层衬里。绝缘层衬里可以包括例如氮化硅层。
参照图7A和图7B,可以形成第一掩模图案13以沿第二方向(Y)跨过器件隔离层11和硅层7。第一掩模图案13可以在第二方向(Y)上是长的。第一掩模图案13可以由具有彼此不同的蚀刻速率的层组成。例如,第一掩模图案13可以包括氮化硅层、氧化硅层、旋涂硬掩模(SOH)、旋涂碳(SOC)、非晶碳层(ACL)和光致抗蚀剂图案中的至少一种。可以使硅层7的在第一掩模图案13的(在第一方向(X)上)两侧处的顶部暴露。
参照图8A和图8B,可以使用第一掩模图案13作为蚀刻掩模顺序地蚀刻第一掩模图案13的两侧处的硅层7和SiGe层5,以形成第二沟槽15。也可以使沟道停止区3图案化。由此,可以使半导体基底1的顶部部分地凹陷。通过该工艺,可以形成交替堆叠的SiGe图案5a和硅图案7a。可以通过第二沟槽15暴露器件隔离层11的侧壁。
参照图9A和图9B,可以执行选择性外延生长(SEG)工艺以在第二沟槽15的内侧壁和底部上形成硅外延层17。可以在SiGe图案5a的侧壁和硅图案7a的侧壁上以及半导体基底1的凹陷表面上形成硅外延层17。硅外延层17可以覆盖沟道停止区3的侧壁。可以不区分硅外延层17和硅图案7a之间的边界。硅外延层17可以不形成在器件隔离层11上。
参照图10A和图10B,可以在半导体基底1上堆叠多晶硅层以填充第二沟槽15,并且可以执行各向异性蚀刻以在第二沟槽15中形成源极/漏极图案19。可以将源极/漏极图案19形成为掺有杂质的多晶硅层。可以通过在各向异性蚀刻工艺之后执行离子注入工艺来注入掺杂到源极/漏极图案19中的杂质,或者可以在多晶硅层堆叠期间原位供应掺杂到源极/漏极图案19中的杂质。
参照图11A和图11B,可以在半导体基底1上堆叠掩模层,并且可以执行平坦化工艺以暴露第一掩模图案13的顶部并且同时在第一掩模图案13的两侧处形成第二掩模图案21。可以使用具有与第一掩模图案13的蚀刻选择性不同的蚀刻选择性的材料来形成第二掩模图案21。此外,可以使用具有与器件隔离层11的蚀刻选择性不同的蚀刻选择性的材料来形成第二掩模图案21。例如,可以使用氧化硅层形成第一掩模图案13,并且可以使用氮化硅层形成第二掩模图案21。
参照图12A和图12B,可以去除第一掩模图案13以暴露硅图案7a和器件隔离层11的位于第二掩模图案21之间的顶部。如上所述,可以通过自对准方法形成第二掩模图案21,可以避免第二掩模图案21的未对准问题。
另一方面,在不具有图11A和图11B的工艺的情况下,可以在形成第二掩模图案21之前去除第一掩模图案13,然后,可以通过光刻工艺和蚀刻工艺来形成第二掩模图案21。
参照图13A和图13B,可以蚀刻在第二掩模图案21之间暴露的器件隔离层11以形成开口23。在开口23中,可以在第二方向(Y)上暴露硅图案7a和SiGe图案5a的侧壁。可以暴露半导体基底1的其上设置有沟道停止区3的侧壁。在开口23的底部上,可以保留器件隔离层11。
参照图14A和图14B,可以供应参照图1至图3说明的预处理组合物,以在器件隔离层11的表面上形成钝化层25。为了增加钝化层25与器件隔离层11的表面之间的结合力,可以另外执行加热或光照射工艺。钝化层25可以不形成在硅图案7a和SiGe图案5a的表面上。根据示例实施例的图1和图2的工艺可以对应于图14A和图14B。
参照图15A和图15B,可以供应SiGe蚀刻组合物以蚀刻且去除SiGe图案5a并暴露硅图案7a的表面和半导体基底1的表面。因此,可以在硅图案7a之间形成空的空间27。也可以去除钝化层25。根据示例实施例的图3的工艺可以对应于图15A和图15B。
参照图16A和图16B,可以通过执行热氧化工艺或沉积工艺在硅图案7a的表面和半导体基底1的表面上形成栅极绝缘层30。栅极绝缘层30可以包括氧化硅层、氮化硅层和金属氧化物层中的至少一种。在半导体基底1的整个表面上,可以堆叠导电层,并且可以执行回蚀工艺或化学机械抛光(CMP)工艺以暴露第二掩模图案21的顶部并同时形成填充第二掩模图案21之间的空间、开口23以及硅图案7a之间的空的空间27的栅电极32。栅电极32可以包括掺杂杂质的多晶硅、金属硅化物和金属层中的至少一种。金属层可以是例如钴、铜、铝和钨中的至少一种。金属硅化物可以是例如硅化钴。
参照图17A和图17B,可以去除第二掩模图案21以暴露器件隔离层11的顶部和源极/漏极图案19的顶部。因此,可以制造具有MBC MOSFET结构的半导体器件。在说明书中,可以通过使用预处理组合物的预处理工艺来防止器件隔离层11的损坏。因此,可以制造具有改善的可靠性的半导体器件。
通过总结和回顾,对于尺寸减小到小于约20nm,半导体器件会变得更难以通过MOS形成。因此,正在考虑不是通过按比例缩小而是通过改变结构等来改善性能的方法。例如,已经考虑了多桥沟道(MBC)MOSFET,其中,设置多个薄硅桥以形成堆叠结构并且栅电极具有包裹硅桥的结构。由于这样的结构特性,MBC MOSFET可以获得具有平面MOSFET的驱动电流约4.6倍的驱动电流,并且可以确保接近理想值的电特性。
如上所述,实施例可以提供在蚀刻SiGe之前使用的用于使氧化硅层钝化的预处理组合物。
实施例还可以提供制造可以减少或防止缺陷的半导体器件的方法。
根据示例实施例的在蚀刻SiGe之前使用的预处理组合物可以使氧化硅层钝化以防止或减少在执行随后的SiGe蚀刻工艺时氧化硅层的损坏。
在根据示例实施例的制造半导体器件的方法中,可以使用在蚀刻SiGe之前使用的预处理组合物来执行用于使氧化硅层钝化的预处理工艺,并且可以防止或减少氧化硅层的损坏,并且可以减少缺陷,因此,可以制造具有改善的可靠性的半导体器件。
这里已经公开了示例实施例,并且虽然采用了特定术语,但是它们仅以一般性和描述性意义来使用和解释,而不是出于限制的目的。在一些情况下,除非另外特别指出,否则如本领域普通技术人员在提交本申请时将是明显的,结合特定实施例描述的特征、特性和/或元件可以单独使用或与结合其它实施例描述的特征、特性和/或元件组合使用。因此,本领域技术人员将理解的是,在不脱离权利要求中阐述的本发明的精神和范围的情况下,可以在形式和细节上进行各种改变。

Claims (19)

1.一种在蚀刻硅锗之前使用的预处理组合物,所述预处理组合物包括:
酸;
醇;以及
下面式1的硅烷化合物:
<式1>
R-Si(R1)n(OR2)3-n
其中,在式1中,
R是(C3-C20)烷基、(C6-C12)芳基、(C6-C12)芳基(C3-C20)烷基或(C3-C20)烷基(C6-C12)芳基,
R1是氢、羟基、卤素、(C1-C20)烷基、卤代(C1-C20)烷基、(C6-C12)芳基、(C6-C12)芳基(C1-C20)烷基或(C1-C20)烷基(C6-C12)芳基,
R2是氢、(C1-C20)烷基、卤代(C1-C20)烷基、(C6-C12)芳基、(C6-C12)芳基(C1-C20)烷基或(C1-C20)烷基(C6-C12)芳基,
n是0至2的整数,并且
R中的烷基、芳基、芳基烷基或烷基芳基以及R1中的烷基、卤代烷基、芳基、芳基烷基或烷基芳基可选择地进一步取代有选自于卤素、羟基、-N(R11)(R12)和-S(R13)中的一个或更多个取代基,其中,R11、R12和R13中的每个独立地为氢或(C1-C20)烷基。
2.根据权利要求1所述的预处理组合物,其中:
酸以0.01wt%至20wt%的量存在,
醇以1wt%至90wt%的量存在,
硅烷化合物以0.01wt%至5wt%的量存在,并且
还以0wt%至98.98wt%的量存在有去离子水。
3.根据权利要求1所述的预处理组合物,其中,在式1中,
R是(C3-C20)烷基、卤代(C3-C20)烷基或(C6-C12)芳基,
R2是(C1-C20)烷基,并且
n是0。
4.根据权利要求1所述的预处理组合物,其中,硅烷化合物包括由下面的式(1-1)至式(1-7)中的一个表示的化合物:
5.根据权利要求1所述的预处理组合物,其中,酸包括氢氟酸、盐酸、硼酸、硫酸、硝酸、磷酸、过氧化氢、乙酸、丙酸、二乙酸、甲酸、丁酸、柠檬酸、乙醇酸、草酸、丙二酸、戊酸、酒石酸、葡萄糖酸、琥珀酸、亚氨基二乙酸、甲磺酸、乙磺酸、乳酸、抗坏血酸、缬草酸、丁基乙酸、庚酸、癸酸、苹果酸、马来酸、戊二酸、己二酸、D-葡萄糖酸、衣康酸、柠康酸、中康酸、2-氧代戊二酸、偏苯三酸、茵多酸、谷氨酸和甲基琥珀酸中的一种或更多种。
6.根据权利要求1所述的预处理组合物,其中,醇包括甲醇、乙醇、丙醇、异丙醇、丁醇、异丁醇、叔丁醇、2-甲氧基乙醇、1-甲氧基-2-丙醇、3-甲氧基-1-丁醇、戊醇、己醇、2-乙基-1-己醇、庚醇、辛醇、乙二醇、丙二醇、丁二醇、己二醇、四氢糠醇、1,2-丁二醇和1,4-丁二醇中的一种或更多种。
7.一种制造半导体器件的方法,所述方法包括:
在半导体基底上形成绝缘图案、硅图案和硅锗图案;
供应预处理组合物以在绝缘图案上形成钝化层;以及
使用硅锗蚀刻组合物蚀刻硅锗图案,
其中,预处理组合物包括酸、醇和下面式1的硅烷化合物:
<式1>
R-Si(R1)n(OR2)3-n
其中,在式1中,
R是(C3-C20)烷基、(C6-C12)芳基、(C6-C12)芳基(C3-C20)烷基或(C3-C20)烷基(C6-C12)芳基,
R1是氢、羟基、卤素、(C1-C20)烷基、卤代(C1-C20)烷基、(C6-C12)芳基、(C6-C12)芳基(C1-C20)烷基或(C1-C20)烷基(C6-C12)芳基,
R2是氢、(C1-C20)烷基、卤代(C1-C20)烷基、(C6-C12)芳基、(C6-C12)芳基(C1-C20)烷基或(C1-C20)烷基(C6-C12)芳基,
n是0至2的整数,并且
R中的烷基、芳基、芳基烷基或烷基芳基以及R1中的烷基、卤代烷基、芳基、芳基烷基或烷基芳基进一步取代有选自于卤素、羟基、-N(R11)(R12)和-S(R13)中的一个或更多个取代基,其中,R11、R12和R13中的每个独立地为氢或(C1-C20)烷基。
8.根据权利要求7所述的方法,所述方法还包括对钝化层执行加热或光照射,以增大钝化层与绝缘图案之间的结合力。
9.根据权利要求7所述的方法,所述方法还包括在70℃至200℃的温度下执行钝化层的加热0.1分钟至30分钟以增大钝化层与绝缘图案之间的结合力,或者用具有100nm至400nm的波长的光对钝化层执行光照射0.1分钟至30分钟以增大钝化层与绝缘图案之间的结合力。
10.根据权利要求7所述的方法,其中,硅锗蚀刻组合物去除钝化层。
11.根据权利要求7所述的方法,其中,硅锗蚀刻组合物包括酸、氧化剂和去离子水。
12.根据权利要求11所述的方法,其中,硅锗蚀刻组合物还包括表面活性剂。
13.根据权利要求7所述的方法,其中,在半导体基底上形成绝缘图案、硅图案和硅锗图案的步骤包括:
在半导体基底上顺序地堆叠硅锗层和硅层;
使硅层和硅锗层图案化,以形成暴露半导体基底的沟槽,并形成硅图案和硅锗图案;以及
形成用于部分地填充沟槽并暴露硅图案的侧壁和硅锗图案的侧壁的绝缘图案,并且
蚀刻硅锗图案的步骤包括去除硅锗图案以暴露硅图案的底表面和半导体基底的顶表面。
14.根据权利要求13所述的方法,其中,绝缘图案包括氧化硅。
15.根据权利要求7所述的方法,其中,在预处理组合物中:
酸以0.01wt%至20wt%的量存在;
醇以1wt%至90wt%的量存在;并且
硅烷化合物以0.01wt%至5wt%的量存在。
16.根据权利要求15所述的方法,其中,预处理组合物还包括0wt%至98.98wt%的去离子水。
17.根据权利要求7所述的方法,其中,硅烷化合物包括由下面的式(1-1)至式(1-7)中的一个表示的化合物:
18.根据权利要求7所述的方法,其中,酸包括氢氟酸、盐酸、硼酸、硫酸、硝酸、磷酸、过氧化氢、乙酸、丙酸、二乙酸、甲酸、丁酸、柠檬酸、乙醇酸、草酸、丙二酸、戊酸、酒石酸、葡萄糖酸、琥珀酸、亚氨基二乙酸、甲磺酸、乙磺酸、乳酸、抗坏血酸、缬草酸、丁基乙酸、庚酸、癸酸、苹果酸、马来酸、戊二酸、己二酸、D-葡萄糖酸、衣康酸、柠康酸、中康酸、2-氧代戊二酸、偏苯三酸、茵多酸、谷氨酸和甲基琥珀酸中的一种或更多种。
19.根据权利要求7所述的方法,其中,醇包括甲醇、乙醇、丙醇、异丙醇、丁醇、异丁醇、叔丁醇、2-甲氧基乙醇、1-甲氧基-2-丙醇、3-甲氧基-1-丁醇、戊醇、己醇、2-乙基-1-己醇、庚醇、辛醇、乙二醇、丙二醇、丁二醇、己二醇、四氢糠醇、1,2-丁二醇和1,4-丁二醇中的一种或更多种。
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Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06342787A (ja) * 1993-11-17 1994-12-13 Matsushita Electric Ind Co Ltd 保護膜の製造方法
US6361871B1 (en) * 1999-02-03 2002-03-26 Degussa Ag Composition of organofluorine-functional silanes and/or siloxanes, process for preparing it and its use
US20050132748A1 (en) * 2003-06-26 2005-06-23 Central Glass Company, Limited Organic-inorganic hybrid glassy materials and their production processes
CN1649096A (zh) * 2004-01-29 2005-08-03 株式会社半导体能源研究所 接触空穴、半导体器件、液晶显示器及el显示器的制法
JP2005327757A (ja) * 2004-05-12 2005-11-24 Catalysts & Chem Ind Co Ltd 低誘電率非晶質シリカ系被膜の形成方法および該方法より得られる低誘電率非晶質シリカ系被膜
CN101479830A (zh) * 2006-06-27 2009-07-08 朗姆研究公司 蚀刻损坏的低k电介质材料的修复和强度恢复
CN101490621A (zh) * 2006-11-21 2009-07-22 第一毛织株式会社 用于加工抗蚀剂下层膜的硬掩模组合物、使用该硬掩模组合物来生产半导体集成电路器件的方法、以及通过该方法生产的半导体集成电路器件
CN102332395A (zh) * 2011-09-23 2012-01-25 复旦大学 一种选择性淀积栅氧和栅电极的方法
JP2013251379A (ja) * 2012-05-31 2013-12-12 Tokyo Electron Ltd エッチング方法、エッチング装置及び記憶媒体
CN104126228A (zh) * 2011-12-23 2014-10-29 英特尔公司 非平面栅极全包围器件及其制造方法
US20160280955A1 (en) * 2015-03-27 2016-09-29 Ppg Industries Ohio, Inc. Durable anti-fingerprint polymers and coating compositions

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19624032A1 (de) * 1996-06-17 1997-12-18 Huels Chemische Werke Ag Oligomerengemisch kondensierter Alkylalkoxysilane
JP2004519090A (ja) 2000-08-07 2004-06-24 アンバーウェーブ システムズ コーポレイション 歪み表面チャネル及び歪み埋め込みチャネルmosfet素子のゲート技術
KR100420049B1 (ko) * 2001-04-16 2004-02-25 삼성에스디아이 주식회사 투명 도전막의 보호막 형성용 조성물 및 이를 이용하여 제조되는 보호막의 제조방법
KR100481209B1 (ko) 2002-10-01 2005-04-08 삼성전자주식회사 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법
US20040242015A1 (en) 2003-03-04 2004-12-02 Kyoung-Chul Kim Etching compositions for silicon germanium and etching methods using the same
US7176041B2 (en) 2003-07-01 2007-02-13 Samsung Electronics Co., Ltd. PAA-based etchant, methods of using same, and resultant structures
JP4308050B2 (ja) * 2004-03-18 2009-08-05 三洋電機株式会社 光導波路
JP4756128B2 (ja) 2004-10-20 2011-08-24 日揮触媒化成株式会社 半導体加工用保護膜形成用塗布液、その調製方法およびこれより得られる半導体加工用保護膜
JP2007165677A (ja) 2005-12-15 2007-06-28 Seiko Epson Corp 半導体基板の製造方法及び半導体装置
US7776745B2 (en) 2006-02-10 2010-08-17 Stmicroelectronics S.A. Method for etching silicon-germanium in the presence of silicon
WO2008080096A2 (en) 2006-12-21 2008-07-03 Advanced Technology Materials, Inc. Compositions and methods for the selective removal of silicon nitride
US20100009188A1 (en) * 2008-07-11 2010-01-14 John Haozhong Xin Nano-structured surface and an in situ method for forming the same
CN107416764A (zh) * 2010-10-27 2017-12-01 皮瑟莱根特科技有限责任公司 纳米晶体的合成、盖帽和分散
JP5991846B2 (ja) 2012-04-24 2016-09-14 東京応化工業株式会社 膜形成用組成物、拡散剤組成物、膜形成用組成物の製造方法、及び拡散剤組成物の製造方法
US8883252B2 (en) * 2012-06-28 2014-11-11 Intermolecular, Inc. Antireflective coatings with self-cleaning, moisture resistance and antimicrobial properties
US8748940B1 (en) 2012-12-17 2014-06-10 Intel Corporation Semiconductor devices with germanium-rich active layers and doped transition layers
US9968930B2 (en) * 2013-04-04 2018-05-15 Surnetics, Llc Microfluidic products with controlled fluid flow
GB201410550D0 (en) 2014-06-13 2014-07-30 Scott Lionel Data transmission
US9607990B2 (en) 2015-08-28 2017-03-28 International Business Machines Corporation Method to form strained nFET and strained pFET nanowires on a same substrate
DE102015115004A1 (de) * 2015-09-07 2017-03-09 Leibniz-Institut Für Neue Materialien Gemeinnützige Gmbh Verfahren zur Herstellung von strukturierten Oberflächen
KR102457249B1 (ko) 2015-09-18 2022-10-21 주식회사 이엔에프테크놀로지 식각 조성물
KR102514008B1 (ko) 2015-11-18 2023-03-27 솔브레인 주식회사 실리콘계 화합물 증착막의 데미지 저감을 위한 식각 조성물 및 이를 이용한 반도체 소자의 제조 방법
KR20170130665A (ko) * 2016-05-18 2017-11-29 오씨아이 주식회사 실리콘 기판의 전처리제 및 이를 이용한 실리콘 기판의 식각 방법
KR101778893B1 (ko) 2016-10-13 2017-09-15 오씨아이 주식회사 실리콘 기판 식각 용액
WO2018066515A1 (ja) 2016-10-04 2018-04-12 日産化学工業株式会社 パターン反転のための被覆組成物
KR102710507B1 (ko) 2016-12-14 2024-09-25 삼성전자주식회사 식각용 조성물 및 이를 이용한 반도체 장치 제조 방법

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06342787A (ja) * 1993-11-17 1994-12-13 Matsushita Electric Ind Co Ltd 保護膜の製造方法
US6361871B1 (en) * 1999-02-03 2002-03-26 Degussa Ag Composition of organofluorine-functional silanes and/or siloxanes, process for preparing it and its use
US20050132748A1 (en) * 2003-06-26 2005-06-23 Central Glass Company, Limited Organic-inorganic hybrid glassy materials and their production processes
CN1649096A (zh) * 2004-01-29 2005-08-03 株式会社半导体能源研究所 接触空穴、半导体器件、液晶显示器及el显示器的制法
JP2005327757A (ja) * 2004-05-12 2005-11-24 Catalysts & Chem Ind Co Ltd 低誘電率非晶質シリカ系被膜の形成方法および該方法より得られる低誘電率非晶質シリカ系被膜
CN101479830A (zh) * 2006-06-27 2009-07-08 朗姆研究公司 蚀刻损坏的低k电介质材料的修复和强度恢复
CN101490621A (zh) * 2006-11-21 2009-07-22 第一毛织株式会社 用于加工抗蚀剂下层膜的硬掩模组合物、使用该硬掩模组合物来生产半导体集成电路器件的方法、以及通过该方法生产的半导体集成电路器件
CN102332395A (zh) * 2011-09-23 2012-01-25 复旦大学 一种选择性淀积栅氧和栅电极的方法
CN104126228A (zh) * 2011-12-23 2014-10-29 英特尔公司 非平面栅极全包围器件及其制造方法
JP2013251379A (ja) * 2012-05-31 2013-12-12 Tokyo Electron Ltd エッチング方法、エッチング装置及び記憶媒体
US20160280955A1 (en) * 2015-03-27 2016-09-29 Ppg Industries Ohio, Inc. Durable anti-fingerprint polymers and coating compositions

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