CN102332395A - 一种选择性淀积栅氧和栅电极的方法 - Google Patents

一种选择性淀积栅氧和栅电极的方法 Download PDF

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CN102332395A
CN102332395A CN201110285019A CN201110285019A CN102332395A CN 102332395 A CN102332395 A CN 102332395A CN 201110285019 A CN201110285019 A CN 201110285019A CN 201110285019 A CN201110285019 A CN 201110285019A CN 102332395 A CN102332395 A CN 102332395A
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CN102332395B (zh
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孙清清
李叶
房润辰
王鹏飞
张卫
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Fudan University
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Abstract

本发明属于半导体集成电路制造技术领域，具体涉及一种选择性淀积栅氧和栅电极的方法。本发明利用十八烷基三乙氧基硅烷（ODTS）易于吸附在Si-OH界面而不易吸附在Si-H界面的特性，有选择性的淀积栅氧和栅电极材料，避免了不必要的材料浪费，节约了成本。本发明同时将对栅氧和栅电极的刻蚀转化为对SiO2的刻蚀，降低了刻蚀工艺的难度，提高了生产效率。

Description

一种选择性淀积栅氧和栅电极的方法
技术领域
本发明涉及一种栅氧和栅电极的制备方法，具体涉及一种选择性淀积栅氧和栅电极的方法，属于半导体集成电路制造技术领域。
背景技术
随着金属-氧化物-半导体场效应晶体管(MOSFET)特征尺寸的不断缩小, 绝缘栅介质层也按照等比例缩小的原则变得越来越薄，当栅介质层薄到一定程度后,其可靠性问题,尤其是与时间相关的击穿及栅电极中的杂质向衬底的扩散等问题,将严重影响器件的稳定性和可靠性。现在，SiO2作为栅介质已经达到其物理极限，会由于量子直接隧穿效应而导致栅极漏电流显著增加，使器件功耗变大，同时可靠性变坏。用高k栅介质取代SiO2栅介质，可以在保持等效氧化层厚度(EOT)不变的情况下大大增加其物理厚度，从而减小栅极漏电流。
高k栅介质材料因为解决了SiO2接近物理厚度极限引发的诸多问题，而成为了代替SiO2的热门材料。然而，由于多晶硅与HfO2等高k栅介质材料结合会出现许多问题,如多晶硅栅耗尽效应、费米能级的钉扎、过高的栅电阻、严重的硼穿透等现象。因此,采用金属栅替代多晶硅栅电极成为发展的必然趋势。传统工艺中栅极的形成过程是先淀积栅氧和栅电极，然后对栅氧和栅电极进行光刻、刻蚀出栅极，其刻蚀工艺难度较大，良率偏低。
原子层淀积是一种在经过表面活性处理的衬底上利用表面饱和反应，对温度和反应物通量不太敏感的淀积方法。在原子层淀积过程中，新一层原子膜的化学反应是直接与前一层相关联的，这种方式使每次反应只淀积一层原子。相对于传统的淀积工艺而言，原子层淀积方法能精确地控制薄膜的厚度和化学组分，而且淀积的薄膜具有很好的均匀性和保形性，被认为是未来集成电路中制备薄膜最具有前景的技术。所谓选择性淀积是指利用化学试剂如十八烷基三乙氧基硅烷（ODTS）对集成电路衬底的不同表面进行化学修饰来实现薄膜的淀积在某些特定表面的生长，可以减少材料的浪费。
发明内容
有鉴于此，本发明的目的在于提出一种利用选择性淀积技术来制备栅极的方法，以减少材料的浪费，同时可以减小栅氧和栅电极的刻蚀难度，提高生产良率。
为达到本发明的上述目的，本发明提出了一种选择性淀积栅氧和栅电极的方法，具体步骤包括：
提供一个半导体衬底并清洗；
进行场氧区隔离；
生长一层二氧化硅；
淀积光刻胶；
光刻、刻蚀定义出栅极位置；
剥除光刻胶；
对二氧化硅进行表面处理；
在二氧化硅上吸附一层十八烷基三乙氧基硅烷（ODTS）； 
淀积高k栅介质；
淀积金属电极；
去除ODTS和二氧化硅。
进一步地，所述的二氧化硅的厚度为50-200纳米。所述的高k栅介质为Pr2O3、TiO2、HfO2、Al2O3或ZrO2等材料，其厚度范围为2-20纳米。所述的金属电极由TiN、TaN、Ru或W等金属栅材料形成
更进一步地，所述的对二氧化硅进行表面处理的过程为：先用piranha solution（浓度为95-98%的H2SO4与H2O2的体积比为7：3）在室温下处理15--25分钟，之后在浓度为2%的HF酸溶液中浸泡1-3分钟，最后用去离子水冲洗干净。
本发明所提出的选择性淀积栅氧和栅电极的方法的优点是：
1、利用ODTS易于吸附在Si-OH界面而不易吸附在Si-H界面的特性，有选择性的淀积栅氧和栅电极材料，避免了不必要的材料浪费，节约了成本。
2、将对栅氧和栅电极的刻蚀转化为对SiO2的刻蚀，降低了刻蚀工艺的难度，提高了生产效率。
3、采用原子层淀积的方法生长高k栅介质和金属栅的主体部分，保证了高k栅介质层的质量以及与金属栅良好的接触。
附图说明
图1为本发明所提供的选择性淀积栅氧和栅电极的方法的流程图。
图2至图8为利用本发明提供的选择性淀积栅氧和栅电极的方法来制备栅极的一个实施例的工艺流程图。
具体实施方式
图1为本发明所提供的选择性淀积栅氧和栅电极的方法的流程图，具体包括：提供一个半导体衬底并经RCA清洗工艺清洗；进行场氧区隔离；生长一层二氧化硅；光刻、刻蚀定义出栅极位置；对二氧化硅进行表面处理；在二氧化硅上吸附一层十八烷基三乙氧基硅烷（ODTS）； 淀积高k栅介质；淀积金属电极；去除ODTS和二氧化硅。
下面结合附图与具体实施方式对本发明作进一步详细的说明，在图中，为了方便说明，放大或缩小了层和区域的厚度，所示大小并不代表实际尺寸。尽管这些图并不能完全准确的反映出器件的实际尺寸，但是它们还是完整的反映了区域和组成结构之间的相互位置，特别是组成结构之间的上下和相邻关系。图中的表示是示意性的，但这不应该被认为是限制本发明的范围。同时在下面的描述中，所使用的术语衬底可以理解为包括正在工艺加工中的半导体衬底，可能包括在其上所制备的其它薄膜层。
本发明所提出的选择性淀积栅氧和栅电极的方法可以适用于不同MOS器件的栅极的制备，以下所叙述的是利用本发明所提出的方法来制备NMOSFET器件的栅极的实施例。
首先，提供一个P型的Si衬底201，并用传统的RCA清洗工艺清洗Si衬底，之后在浓度为2%的HF酸中浸泡1-3分钟以去除Si表面的氧化层，然后用N2将Si衬底吹干。接着利用LOCOS的方法进行场区隔离，具体工艺为：先生长缓冲层氧化层并利用LPCVD 工艺淀积Si3N4，然后光刻、刻蚀形成场氧区202，如图2所示。
接下来，生长一层厚度为100纳米左右的二氧化硅203，接着淀积一层光刻胶，然后光刻、刻蚀定义出栅极位置204，剥除光刻胶后的结构如图3所示。
接下来，将二氧化硅203用piranha solution（浓度为95-98%的H2SO4与H2O2的体积比为7：3）在室温下处理20分钟，之后在浓度为2%的HF酸溶液中浸泡2分钟，最后用去离子水冲洗，得到如图4所示的结果，在二氧化硅203表面形成Si-OH界面，在Si衬底201的表面形成Si-OH界面。
接下来，将基片在10mM的ODTS溶液中浸泡48小时，然后用甲苯、丙酮、氯仿清洗，再用N2吹干。这样，利用ODTS易于吸附在Si-OH界面而不易吸附在Si-H界面的特性，可以在只在二氧化硅203的表面形成一层ODTS 205，如图5所示。
接下来，利用原子层淀积（ALD）技术生长高 k栅介质层206，如图6所示。高k栅介质比如采用Al2O3或者HfO2，反应温度分别为200℃和300℃，速率分别为0.1nm/cycle和0.09nm/cycle。
接下来，淀积栅电极207，如图7所示，栅电极比如采用W、TiN、Ru、TaN材料,其具体工艺过程可以为：首先用ALD技术淀积栅电极的成核层，之后再用化学气相淀积（CVD）技术淀积其主体部分。
最后，去除ODTS 205和二氧化硅203，如图8所示。
如上所述，在不偏离本发明精神和范围的情况下，还可以构成许多有很大差别的实施例。应当理解，除了如所附的权利要求所限定的，本发明不限于在说明书中所述的具体实例。

Claims (5)

1.一种选择性淀积栅氧和栅电极的方法，其特征在于具体步骤为：
提供一个半导体衬底并清洗；
进行场氧区隔离；
生长一层二氧化硅；
光刻、刻蚀定义出栅极位置；
对二氧化硅进行表面处理；
在二氧化硅上吸附一层十八烷基三乙氧基硅烷； 
淀积高k栅介质；
淀积金属电极；
去除ODTS和二氧化硅。
2.根据权利要求1所述的选择性淀积栅氧和栅电极的方法，其特征在于，所述的二氧化硅的厚度为50-200纳米。
3.根据权利要求1所述的选择性淀积栅氧和栅电极的方法，其特征在于，所述的对二氧化硅进行表面处理的过程为：先用piranha solution在室温下处理15--25分钟，之后在浓度为2%的HF酸溶液中浸泡1-3分钟，最后用去离子水冲洗干净。
4.根据权利要求1所述的选择性淀积栅氧和栅电极的方法，其特征在于，所述的高k栅介质材料为Pr2O3、TiO2、HfO2、Al2O3或ZrO2，其厚度范围为2-20纳米。
5.根据权利要求1所述的选择性淀积栅氧和栅电极的方法，其特征在于，所述的金属电极由TiN、TaN、Ru或W金属栅材料形成。
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