CN110119178A - 基准电压产生装置 - Google Patents

基准电压产生装置 Download PDF

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CN110119178A
CN110119178A CN201910003748.XA CN201910003748A CN110119178A CN 110119178 A CN110119178 A CN 110119178A CN 201910003748 A CN201910003748 A CN 201910003748A CN 110119178 A CN110119178 A CN 110119178A
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吉野英生
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Abstract

本发明提供基准电压产生装置，抑制了相对于温度变动的基准电压的变动。基准电压产生装置具有：恒定电流电路，其包含具有第一沟道尺寸的第一MOS晶体管，该第一MOS晶体管具有第一导电型的栅电极、源区、漏区和第一沟道杂质区；以及电压生成电路，其包含具有与第一沟道尺寸不同的第二沟道尺寸的第二MOS晶体管，该第二MOS晶体管具有第二导电型的栅电极、与第一导电型的源区、漏区和与第一沟道杂质区不同的杂质浓度的第二沟道杂质区。

Description

基准电压产生装置
技术领域
本发明涉及基准电压产生装置。
背景技术
伴随今后的IoT的普及，可预想到IC的工作温度范围随着在各种各样的产品中搭载IC而扩大。因此，在具有基准电压产生装置的IC中，为了抑制由于温度变化引起的误动作，期望基准电压产生装置输出的基准电压相对于温度变化的变化较小。
将恒定电流电路输出的恒定电流输入到电压生成电路并产生基于该恒定电流值的恒定的基准电压的结构的基准电压产生装置在IC中一般经常被使用。在这样的结构的基准电压产生装置中，通过采用使恒定电流电路和电压生成电路的相对于温度变化的特性的变动(以下，称作温度变动)一致并抵消这些温度变动的电路结构，抑制基准电压的温度变动。
在专利文献1中示出了组合输出恒定电流的耗尽型MOS晶体管和生成恒定电压的增强型MOS晶体管并调整耗尽型MOS晶体管的构造以在规格温度范围内抑制基准电压的温度变动的技术。
此外，在专利文献2中示出了如下技术：由沟道的杂质条件相同且栅电极的极性分别为N型和P型的耗尽型MOS晶体管和增强型MOS晶体管构成基准电压产生装置，通过调整基于各个晶体管的沟道长度和沟道宽度的沟道尺寸之比，抑制基准电压的温度变动。
专利文献1：日本特开2003-31678号公报
专利文献2：日本特开2007-206972号公报
如专利文献1所示，在组合耗尽型MOS晶体管和增强型MOS晶体管而构成的基准电压产生装置输出的基准电压Vref中，能够在规格温度范围内减少如图4的Ⅴref1的基准电压的温度变动中的直线成分的斜率，该耗尽型MOS晶体管在比半导体表面深的部分形成沟道的(以下，称作掩埋沟道)，该增强型MOS晶体管在半导体衬底表面形成沟道(以下，称作表面沟道)。但是，难以减少如ΔVref1这样的与基准电压Vref的直线成分Vref1的偏差(以下，称作直线成分偏差)。这主要因为，存在如图3的ΔVTE1或ΔVTD1这样的、增强型MOS晶体管、耗尽型MOS晶体管的阈值电压VTE1、VTD1的温度变动中的直线成分偏差。通常认为这样的阈值电压的温度变动中的直线成分偏差与各个MOS晶体管的耗尽层的伸长、费米能级的温度变动相关联。
此外，专利文献2的增强型MOS晶体管和耗尽型MOS晶体管采用相同的掩埋沟道，因此，能够使阈值电压的温度变动中的直线成分偏差一致。但是，与平带电压相关联的阈值电压的温度变动的直线成分的斜率由于两者的栅电极的极性的不同而不一致。而且，当变更沟道尺寸比以使该直线成分的斜率一致时，会产生基于两者的阈值电压的温度变动中的直线成分偏差的基准电压的直线成分偏差。因此，虽然能够抑制基准电压产生装置输出的基准电压的温度变动的直线成分的斜率，但难以减少该直线成分偏差。
发明内容
鉴于上述内容，本发明的目的在于提供一种组合恒定电流电路和电压生成电路并抑制相对于温度变动的直线成分的斜率和直线成分偏差而能够减少基准电压的温度变动的基准电压产生装置。
为了解决上述课题，本发明采用如下这样的基准电压产生装置。
即，一种基准电压产生装置，其具有：恒定电流电路，其针对输入电压输出恒定电流；以及电压生成电路，其生成基于所述恒定电流的电压，该基准电压产生装置的特征在于，所述恒定电流电路包含具有第一沟道尺寸的第一MOS晶体管，该第一MOS晶体管具有第一导电型的第一栅电极、第一导电型的第一源区、第一导电型的第一漏区和第一导电型的第一沟道杂质区，所述电压生成电路包含具有第二沟道尺寸的第二MOS晶体管，该第二MOS晶体管具有第二导电型的第二栅电极、第一导电型的第二源区、第一导电型的第二漏区和第一导电型的第二沟道杂质区，所述第一沟道尺寸与所述第二沟道尺寸不同，所述第一沟道杂质区的杂质浓度与所述第二沟道杂质区的杂质浓度不同。
根据本发明，通过调整增强型MOS晶体管的沟道尺寸与耗尽型MOS晶体管的沟道尺寸之比，抑制基准电压产生装置输出的基准电压的温度变动中的直线成分的斜率。此外，通过调整增强型MOS晶体管的沟道杂质区的杂质浓度与耗尽型MOS晶体管的沟道杂质区的杂质浓度之比，抑制基准电压的温度变动中的直线成分偏差。通过进行这样的调整，能够实现输出减少了温度变动的基准电压的基准电压产生装置。
附图说明
图1是示出本发明实施方式的基准电压产生装置的电路图。
图2是示出本发明实施方式的基准电压产生装置的剖视图。
图3是示出MOS晶体管的阈值电压的温度特性的图。
图4是示出现有的基准电压产生装置输出的基准电压的温度特性的图。
图5是示出本发明实施方式的增强型NMOS晶体管的阈值电压的温度特性的图。
图6是示出本发明实施方式的基准电压产生装置中的基准电压相对于沟道杂质区的杂质浓度比的温度变动的图。
图7是示出本发明实施方式的基准电压产生装置的另一电路图。
标号说明
1：电源端子；2：接地端子；3：基准电压端子；4：半导体衬底；10：耗尽型NMOS晶体管；11、21：P型阱区；12、22：栅绝缘膜；13、23：漏区；14、24：源区；15、25：栅电极；16、26：沟道杂质区；20：增强型NMOS晶体管；30、40：PMOS晶体管；101、201：恒定电流电路；102、202：电压生成电路；203：电流镜电路。
具体实施方式
下面，参照附图对本发明的实施方式详细地进行说明。为了容易理解本发明的特征，在以下的说明所使用的附图中，有时部分省略地示出，有时与实际不同。
图1是示出本发明实施方式的基准电压产生装置100的电路图。
本实施方式的基准电压产生装置100具有恒定电流电路101和电压生成电路102。与电源端子1连接并供给电源电压VDD的恒定电流电路101向电压生成电路102输出不依赖于电源电压VDD的恒定电流。输入了从恒定电流电路101输出的恒定电流的电压生成电路102从基准电压端子3输出基于该恒定电流的值的基准电压Vref。
在本实施方式中，恒定电流电路101由耗尽型N沟道MOS(以下，称作NMOS)晶体管10构成，该耗尽型N沟道MOS晶体管10具有规定的沟道尺寸SD，阈值电压小于0V。这里，在设沟道宽度为WD、沟道长度为LD时，沟道尺寸SD为用WD/LD表示的值。该耗尽型NMOS晶体管10的栅极、源极和背栅与基准电压端子3连接，漏极与电源端子1连接。
此外，电压生成电路102由增强型NMOS晶体管20构成，该增强型NMOS晶体管20具有规定的沟道尺寸SE，阈值电压为0V以上。这里，在设沟道宽度为WE、沟道长度为LE时，沟道尺寸SE为用WE/LE表示的值。该增强型NMOS晶体管20的栅极和漏极与基准电压端子3连接，源极和背栅与接地端子2连接。
接着，对图1的基准电压产生装置100的电路动作进行说明。构成恒定电流电路101的耗尽型NMOS晶体管10具有第一阈值电压VTD和第一互导gmD(非饱和动作时)。该耗尽型NMOS晶体管10的漏极电流ID表示下式(1)的电压/电流特性。如图1所示，耗尽型NMOS晶体管10的栅极与源极被接线，因此，在下式(1)中，栅极与源极间电压VG为0V。因此，漏极电流ID成为依赖于第一阈值电压VTD且不依赖于漏极电压的饱和漏极电流。即，该饱和漏极电流成为恒定电流电路101的输出电流。该漏极电流ID能够用式(1)的gmD中包含的沟道尺寸SD(WD/LD)来调整。
ID＝1/2·gmD·(VG-VTD)2
＝1/2·gmD·(|VTD|)2……(1)
构成电压生成电路102的增强型NMOS晶体管20具有第二阈值电压VTE和第二互导gmE(非饱和动作时)。该增强型NMOS晶体管20的漏极电流IE表示下式(2)的电压/电流特性。如图1所示，增强型NMOS晶体管20的栅极和漏极被接线，并与基准电压端子3连接，因此，在式(2)中，栅极与源极间电压VG成为基准电压Vref。因此，增强型NMOS晶体管20的漏极电流IE依赖于第二阈值电压VTE和基准电压Vref，相对于基准电压Vref成为与二极管的正向特性类似的电流。该漏极电流IE能够用式(2)的gmE中包含的沟道尺寸SE(WE/LE)来调整。
IE＝1/2·gmE·(VG-VTE)2
＝1/2·gmE·(Vref-VTE)2……(2)
综上所述，基准电压Vref以式(1)的ID与式(2)的IE相等的方式导出，成为下式(3)。
Vref≒VTE+(gmD/gmE)1/2·|VTD|……(3)
根据该式(3)可知，基准电压Vref的温度变动依赖于VTE和VTD各自的温度变动。这里，式(3)中的gmD/gmE包含作为增强型NMOS晶体管20的沟道尺寸SD与耗尽型NMOS晶体管10的沟道尺寸SE之比的SD/SE。这具体为(WD/LD)/(WE/LE)，通过调整不依赖于这些温度的尺寸，能够控制基准电压Vref的温度变动。
图2是示出构成图1中的恒定电流电路101的耗尽型NMOS晶体管10和构成电压生成电路102的增强型NMOS晶体管20的构造的示意剖视图。省略了各晶体管的端子的接线。
耗尽型NMOS晶体管10由以下部分构成：N型的漏区13及N型的源区14，它们形成在N型的半导体衬底4内的P型阱区11内；N型的沟道杂质区16，其形成在漏区13与源区14之间，具有杂质浓度ND；栅绝缘膜12，其形成在沟道杂质区16上；以及栅电极15，其形成在栅绝缘膜12上。
源区14和漏区13包含1×1019/cm3以上的高浓度的N型(以下，称作N+型)的杂质，分别与源极端子S1、漏极端子D1连接。栅电极15的极性是N+型，与栅极端子G1连接。沟道杂质区16的极性是杂质浓度ND为5×1016～1×1018/cm3的低浓度的N型(以下，称作N-型)，因此，即使栅极端子G1的电位为0V，也相对于漏极电压的施加而从漏极端子D1向源极端子S1经由沟道杂质区16流过漏极电流。背栅端子B1经由包含高浓度的P型杂质在内的区域(未图示)与P型阱区11连接。在本实施方式中，该背栅端子B1与源极端子S1连接。
增强型NMOS晶体管20由以下部件构成：N型的漏区23及N型的源区24，它们形成在N型的半导体衬底4内的P型阱区21内；N型的沟道杂质区26，其形成在漏区23与源区24之间，具有杂质浓度NE；栅绝缘膜22，其形成在沟道杂质区26上；以及栅电极25，其形成在栅绝缘膜22上。
源区24和漏区23包含N+型的杂质，分别与源极端子S2、漏极端子D2连接。栅电极25的极性是包含1×1019/cm3以上的高浓度的杂质在内的P型(以下，称作P+型)，与栅极端子G2连接。增强型NMOS晶体管20的沟道杂质区26的极性是与沟道杂质区16相同的N-型，沟道杂质区26的杂质浓度NE高于沟道杂质区16的杂质浓度ND。在栅极端子G2的电位为0V的情况下，该N-型的沟道杂质区26基于P+型的栅电极25之间的功函数差而耗尽，成为阈值电压为0V以上的值。因此，在栅极端子G2的电位为0V的情况下，相对于漏极电压的施加而从漏极端子D2向源极端子S2不会流过漏极电流。背栅端子B2经由包含高浓度的P型杂质在内的区域(未图示)与P型阱区21连接。在本实施方式中，该背栅端子B2与源极端子S2连接。
图3是示意性地示出耗尽型NMOS晶体管的阈值电压VTD和增强型NMOS晶体管的阈值电压VTE针对温度的动作的图。这样，由于阈值电压VTD、VTE中包含的平带电压、耗尽层的伸长、费米能级等的温度特性的影响，如实线所示，任何晶体管都具有各自的阈值电压相对于温度的上升而下降的趋势。
耗尽型NMOS晶体管的阈值电压VTD的温度变动由阈值电压以一定的斜率相对于温度的上升呈直线地下降的虚线的直线成分VTD1、和作为与该直线成分的偏差的用虚线箭头所示的直线成分偏差ΔVTD1构成。此外，增强型NMOS晶体管的阈值电压VTE的温度变动由阈值电压以一定的斜率相对于温度的上升呈直线地下降的虚线的直线成分VTE1、和作为与该直线成分的偏差的用虚线箭头表示的直线成分偏差ΔVTE1构成。如果任意一个晶体管的阈值电压针对温度的动作完全相同，则基于式(3)，在gmD/gmE＝1的情况下，可抵消两者的温度变动，不产生基准电压产生装置100输出的基准电压Vref的温度变动。
耗尽型NMOS晶体管10和增强型NMOS晶体管20的沟道杂质区16、26均为N型的极性，在两者为相同的杂质浓度的情况下，对于形成在该区域上的耗尽层的伸长、费米能级的温度变动而言，直线成分、直线成分偏差均表示相同的倾向。另一方面，N+型的栅电极15和P+型的栅电极25为彼此相反的极性，因此，构成耗尽型NMOS晶体管10的第一阈值电压VTD和增强型NMOS晶体管20的第二阈值电压VTE的各个平带电压Vfbn、Vfbp的温度变动倾向相反。由此，图3中的耗尽型NMOS晶体管的温度变动的直线成分VTD1的斜率小于增强型NMOS晶体管的温度变动的直线成分VTE1的斜率。因此，即使组合除了栅电极以外都为相同条件的耗尽型NMOS晶体管和增强型NMOS晶体管而构成基准电压产生装置，基于这样的平带电压的温度变动，式(3)的基准电压Vref也表示相对于温度上升而下降的温度变动。
在本实施方式中，首先，第一，为了抑制相对于这样的基准电压Vref的温度变动中的温度变动的直线成分的斜率，调整式(3)的gmD/gmE中包含的沟道尺寸比(SD/SE)。虽然也基于N+型的栅电极15和P+型的栅电极25中分别包含的杂质的浓度，但通过用大于1且3以下之间的值调整该沟道尺寸比，增加式(3)的右边第二项的温度变动成分，抑制基准电压Vref的温度变动中的直线成分的斜率。例如，通过设耗尽型NMOS晶体管10的沟道长度为100μm、增强型NMOS晶体管20的沟道长度为200μm、使两者的沟道宽度相同，使沟道尺寸比(SD/SE)成为2。
另一方面，当增加该沟道尺寸比(SD/SE)时，基准电压Vref的温度变动中的直线成分偏差增大。这是因为，通过增加沟道尺寸比，式(3)的右边第二项的相对于温度变动的直线成分偏差ΔVTD1被增大。这时，例如，如表示现有的温度变动的图4所示，基准电压Vref的温度特性具有在-40℃到150℃的范围内被校正并减少了斜率的直线成分Vref1、和通过沟道尺寸比的调整而增大的直线成分偏差ΔVref1。
本发明人发现了通过变更增强型NMOS晶体管的沟道杂质区的杂质浓度NE，能够控制这样的直线成分偏差ΔVref1。图5示出了变更具有P+型的栅电极的增强型NMOS晶体管20的N型的沟道杂质区26的杂质浓度NE时的、阈值电压的温度变动的情形。当针对实线的特性使N型的沟道杂质区的杂质浓度NE增加时，如虚线所示，阈值电压下降，并且，温度变动中的直线成分偏差增加。当使N型的沟道杂质区的杂质浓度NE进一步增加时，如单点划线所示，阈值电压进一步下降，并且，该直线成分偏差进一步增加。
因此，在本实施方式中，在沟道尺寸比(SD/SE)的变更之后，接着，第二，使具有P+型的栅电极的增强型NMOS晶体管20的沟道杂质区26的杂质浓度NE相对于杂质浓度ND增加，由此，增大式(3)的右边第一项的温度变动中的直线成分偏差。然后，通过之前叙述的式(3)的右边第一项的直线成分偏差的增加而抵消由于沟道尺寸比(SD/SE)的调整而产生的式(3)的右边第二项的温度变动中的直线成分偏差的增加。由此，能够抑制基准电压Vref的温度变动中的直线成分偏差ΔVref1，能够实现减小了基准电压Vref的温度变动中的直线成分Vref1的斜率的同时抑制了基准电压的温度变动的基准电压产生装置。
图6是示出基准电压Vref相对于杂质浓度比(NE/ND)的温度变动中的直线成分偏差ΔVref1的曲线图。在曲线图上的各点处，预先调整沟道尺寸比(SD/SE)，使基准电压Vref的温度变动中的直线成分Vref1的斜率成为最小。如该图所示，通过控制两者的沟道杂质区的杂质浓度之比，能够抑制基准电压Vref的温度变动中的直线成分偏差ΔVref1。为了充分抑制该直线成分偏差ΔVref1，也基于栅绝缘膜12、22的厚度或栅电极15、25的杂质浓度等，但优选使该沟道杂质区的杂质浓度比(NE/ND)成为大于1且3以下之间的值。在图6的例子中，通过设该杂质浓度比(NE/ND)为大于1且2.3以下之间的值，与杂质浓度比为1的现有结构相比，能够减少基准电压Vref的温度变动中的直线成分偏差ΔVref1。
如上所述，通过结合沟道尺寸比(SD/SE)的调整和沟道杂质区的杂质浓度比(NE/ND)的调整，能够抑制基准电压产生装置100输出的基准电压Vref的温度变动中的直线成分Vref1的斜率和直线成分偏差ΔVref1。
用于变更基准电压Vref的温度变动中的直线成分Vref1的斜率的沟道尺寸比(SD/SE)的调整量与用于变更直线成分偏差的沟道杂质区的杂质浓度比(NE/ND)的调整量成为接近的值。如在将该沟道尺寸比设定为大于1的值时沟道杂质区的杂质浓度比也成为大于1的值那样，两者处于相关的关系，是实质上相同的值。
当变更了沟道杂质区的杂质浓度时，根据该杂质浓度确定的费米能级的温度依赖性发生变化，但在杂质浓度在半导体衬底内恒定的情况下，温度变动中的直线成分偏差较小。但是，在通过离子注入法等而形成的沟道杂质区中，杂质浓度不恒定，该沟道杂质区内的浓度变化较大。而且，杂质注入量越大，该杂质浓度的变化程度越显著。通常认为通过增大杂质浓度，借助电压的施加而形成的耗尽层内的杂质浓度的浓度变化变大，相对于温度的耗尽层的伸长方式成为非线性。此外，认为同时根据杂质浓度确定的费米能级的温度变动的非直线成分也增大。
专利文献1所示的表面沟道的增强型MOS晶体管具有与P型阱区相同极性的P型的沟道杂质区。但是，该沟道杂质区的杂质浓度比掩埋沟道的耗尽型MOS晶体管低1位数左右。这是因为，掩埋沟道的耗尽型MOS晶体管需要预先提高杂质浓度，以在P型阱区上稳定地形成相反极性的N型的沟道杂质区。因此，相对于温度变动的表面沟道的增强型MOS晶体管的阈值电压的直线成分偏差远小于掩埋沟道的耗尽型MOS晶体管的阈值电压的直线成分偏差。因此，在这样的结构中，难以减少基准电压的温度变动中的直线成分偏差。
本发明不限定于上述实施方式，当然能够在不脱离本发明的宗旨的范围内进行各种变更。
例如，在上述实施方式中，使构成图1的基准电压产生装置100的恒定电流电路101采用对栅极与源极进行接线且使栅极与源极间电压VG为0V的耗尽型NMOS晶体管10，但栅极与源极间电压VG无需为0V。即，也可以是采用了栅极输入恒定的电压并输出恒定电流的MOS晶体管的恒定电流电路的结构。
此外，在图2中构成为将上述实施方式的耗尽型NMOS晶体管10和增强型NMOS晶体管20形成在N型的半导体衬底4内的各个P型阱区11、21上，但也可以构成为形成在同一P型阱区内或P型的半导体衬底内。
此外，只要是向电压生成电路输入恒定电流电路输出的恒定电流并产生基于该恒定电流值的恒定的基准电压的结构的基准电压产生装置，恒定电流电路和电压生成电路可以分别不是耗尽型NMOS晶体管和增强型NMOS晶体管，例如也可以利用P沟道的MOS(称作PMOS)晶体管。此外，也可以是，耗尽型MOS晶体管和增强型MOS晶体管中的一方是NMOS，另一方是PMOS。
并且，如图7的基准电压产生装置200所示，也可以采用经由电流镜电路203向电压生成电路202输出恒定电流电路201输出的恒定电流的电路结构，该电流镜电路203是组合2个PMOS晶体管30、40而构成的。

Claims (4)

1.一种基准电压产生装置，其具有：恒定电流电路，其针对输入电压输出恒定电流；以及电压生成电路，其生成基于所述恒定电流的电压，该基准电压产生装置的特征在于，
所述恒定电流电路包含具有第一沟道尺寸的第一MOS晶体管，该第一MOS晶体管具有第一导电型的第一栅电极、第一导电型的第一源区、第一导电型的第一漏区和第一导电型的第一沟道杂质区，
所述电压生成电路包含具有第二沟道尺寸的第二MOS晶体管，该第二MOS晶体管具有第二导电型的第二栅电极、第一导电型的第二源区、第一导电型的第二漏区和第一导电型的第二沟道杂质区，
所述第一沟道尺寸与所述第二沟道尺寸不同，所述第一沟道杂质区的杂质浓度与所述第二沟道杂质区的杂质浓度不同。
2.根据权利要求1所述的基准电压产生装置，其特征在于，
所述第一MOS晶体管为耗尽型MOS晶体管，所述第二MOS晶体管为增强型MOS晶体管。
3.根据权利要求1或2所述的基准电压产生装置，其特征在于，
所述第二沟道杂质区的杂质浓度NE与所述第一沟道杂质区的杂质浓度ND的第一比NE/ND是实质上和所述第一沟道尺寸SD与所述第二沟道尺寸SE的第二比SD/SE相同的值。
4.根据权利要求1至3中的任意一项所述的基准电压产生装置，其特征在于，
所述第二沟道杂质区的杂质浓度NE与所述第一沟道杂质区的杂质浓度ND的第一比NE/ND以及所述第一沟道尺寸SD与所述第二沟道尺寸SE的第二比SD/SE均大于1且为3以下。
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US10886267B2 (en) 2021-01-05
US20190244956A1 (en) 2019-08-08
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