CN109923642A - 用于自对准图案化的方法 - Google Patents
用于自对准图案化的方法 Download PDFInfo
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- CN109923642A CN109923642A CN201780069211.2A CN201780069211A CN109923642A CN 109923642 A CN109923642 A CN 109923642A CN 201780069211 A CN201780069211 A CN 201780069211A CN 109923642 A CN109923642 A CN 109923642A
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- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
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Classifications
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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Abstract
处理方法包括在基板表面上和在表面特征中沉积膜,通过化学平面化从所述基板表面移除所述膜,而留下在所述特征中的所述膜。使柱从所述膜生长,使得所述柱垂直于基板表面生长。
Description
技术领域
本公开内容大体涉及沉积和蚀刻薄膜的方法。特别地,本公开内容涉及用于形成自对准图案化的工艺。
背景技术
半导体产业正快速开发具有越来越小的晶体管尺寸的芯片,以获得每单位面积更多的功能。随着装置的尺寸持续缩小,装置之间的间隙/空间也持续缩小,从而增加将装置彼此物理隔离的难度。使用现有方法来实施以高品质电介质材料填充在装置之间通常为不规则形状的高深宽比沟槽/空间/间隙越来越具有挑战性,所述现有方法包含间隙填充、硬模和间隔件应用。
在基板表面上产生复杂图案化材料层的工艺使得可能制成集成电路。在基板上产生图案化材料需要用于移除暴露的材料的受控方法。出于各种目的使用化学蚀刻,所述目的包含将光刻胶中的图案转移到下层中,减薄层或减薄已经存在于表面上的特征的横向尺寸。经常期望具有比另一种材料更快速地蚀刻一种材料的蚀刻工艺,而有助于例如图案转移工艺。认为这样的蚀刻过程对第一种材料有选择性。由于材料、电路和工艺的多样性,已开发了选择性移除广泛的材料中的一种或多种材料的蚀刻工艺。
通常使用干式蚀刻工艺从半导体基板选择性地移除材料。干式蚀刻工艺能够以最小的物理干扰从微型结构温和地移除材料。干式蚀刻工艺还允许通过移除气相试剂来使蚀刻速率突然停止。一些干式蚀刻工艺涉及使基板暴露于由一或多种前驱物形成的远程等离子体副产物。近来已开发了许多干式蚀刻工艺以相对于彼此选择性地移除各种电介质。然而,开发来选择性地移除含金属材料的干式蚀刻工艺相对较少。需要将工艺程序扩展到各种含金属材料的方法。
随着电路和半导体装置的特征尺寸为了电子部件的更高集成密度而不断缩小,自对准接触(contact)变得越来越有吸引力,并且高度需要自对准接触以解决日益出现的图案化困难。通常,制作自对准接触需要自底向上的柱(pillar),然而所述柱非常难形成,特别是当材料、形状、特征尺寸、方向等受到高度限制时。通常,自对准柱的形成采用使用不同工具的多步骤工艺,从而增加制造成本并且产生更多困难且生产率低。目前为止,针对自对准接触开发的大多数自底向上的柱是竖直对准的导电金属,所述导电金属具有亚微米特征尺寸和不可控的形状。
因此,本领域需要用于自对准图案化工艺的新方法。
发明内容
本公开内容的一个或多个实施方式针对处理方法,所述方法包括提供具有基板表面的基板,所述基板表面具有从所述基板表面延伸进入所述基板的至少一个特征。所述特征具有底部和侧壁。在基板表面上沉积第一膜,使得所述第一膜覆盖所述基板表面并且填充所述特征。通过依序地氧化第一膜的顶部以在所述第一膜的顶部上形成氧化的第一膜并且蚀刻所述氧化的第一膜以移除所述氧化的第一膜,使所述基板表面化学平面化。重复依序的氧化和蚀刻以从所述基板表面移除第一膜而留下在特征中的第一膜。使第一膜膨胀以使第一柱在特征中生长,所述第一柱从所述特征垂直于基板表面延伸。
本公开内容的另外的实施方式针对处理方法,所述方法包括提供具有基板表面的基板,所述基板表面具有从所述基板表面延伸进入所述基板的至少一个特征。所述特征具有底部和侧壁。在基板表面上沉积包括金属的第一膜,使得所述第一膜覆盖所述基板表面并且填充特征。通过依序地氧化第一膜的顶部以在所述第一膜的顶部上形成氧化的第一膜并且蚀刻所述氧化的第一膜以移除所述氧化的第一膜,使基板表面化学平面化。重复依序的氧化和蚀刻以从基板表面移除第一膜而留下特征中的第一膜。使第一膜膨胀以使第一柱在特征中生长,所述第一柱从所述特征垂直于基板表面延伸。
本公开内容另外的实施方式针对处理方法,所述处理方法包括提供具有基板表面的基板,所述基板表面具有从所述基板表面延伸进入所述基板的至少一个特征。所述特征具有底部和侧壁。通过依序地暴露于金属前驱物和反应物来在基板表面上沉积第一膜以形成覆盖所述基板表面并且填充所述特征的所述第一膜。第一膜包括钨金属并且金属前驱物包括卤化钨。通过依序地氧化第一膜的顶部以在所述第一膜的顶部上形成氧化的第一膜并且通过暴露于与金属前驱物相同的卤化钨化合物来蚀刻所述氧化的第一膜以移除所述氧化的第一膜,使基板表面化学平面化。重复依序的氧化和蚀刻以从基板表面移除第一膜而留下特征中的第一膜。通过氧化第一膜或氮化第一膜中的一种或多种方式,使所述第一膜膨胀,以使第一柱在特征中生长,所述第一柱从所述特征垂直于基板表面延伸。沉积第一膜的步骤和使基板表面化学平面化的步骤在相同的处理腔室中发生。
附图简要说明
可通过参照实施方式而得到以上简要概述的本发明的更特定描述,如此可详细理解本发明的上述特征的方式,在附图中图示实施方式中的一些。然而,应注意到,附图仅图示本发明的典型实施方式,因此不应视为限制本发明的范围,因为本发明可容许其他同等有效的实施方式。
图1A~图1F示出根据本公开内容的一个或多个实施方式的工艺程序的横截面图。
具体实施方式
在描述本发明的若干示例性实施方式之前,应当理解,本发明不限于以下描述中记载的构造或工艺步骤的细节。本发明能够具有其他实施方式并且能够以各种方式来实施或进行。
本文使用的“基板”表示任何基板或在基板上形成的材料表面(在制造工艺期间在所述基板或在基板上形成的材料表面上进行膜处理)。举例而言,取决于应用,基板表面(可在所述基板表面上进行处理)包含例如硅、氧化硅、应变硅、绝缘体上硅(SOI)、掺杂碳的硅氧化物、非晶硅、掺杂硅、锗、砷化镓、玻璃、蓝宝石的材料,和例如金属、金属氮化物、金属合金和其他导电材料的任何其他材料。基板包含但不限于半导体晶片。可使基板暴露于预处理工艺以抛光、蚀刻、还原、氧化、羟基化、退火、UV固化、电子束固化和/或烘烤基板表面。除了直接在基板本身的表面上进行膜处理之外,在本发明中,如以下更详细公开的,也可在基板上形成的下层上进行所公开的任何膜处理步骤,并且术语“基板表面”意在包含如上下文所指出的这样的下层。因此举例而言,在已将膜/层或部分的膜/层沉积到基板表面上的情况下,新沉积的膜/层的暴露表面成为基板表面。
本公开内容的一些实施方式通过氧化间隙填充的金属膜提供自组装的金属氧化物(例如,氧化钨)柱。一般而言,本公开内容的实施方式通过ALD或CVD将金属沉积于孔和沟槽的结构(或特征)上并且氧化金属膜以形成金属氧化物。氧化膜造成金属氧化物体积膨胀,从而使柱从所述特征生长。一般而言,为了形成分离的柱,在金属沉积之后移除沉积于结构的顶表面上的金属。移除可通过蚀刻或化学机械平面化(CMP)来完成。通过将晶片移出处理腔室至另一个工具来进行任一工艺,从而减少工艺的整体产量。
本公开内容的一个或多个实施方式针对在不破坏真空的情况下在一个工艺腔室中形成自组装柱的方法。首先,具有特征结构的基板在ALD腔室中沉积有金属膜(例如,钨)。随后在相同腔室中将金属薄膜部分氧化,用热的方法或者通过等离子体增强来氧化。在氧化之后,金属卤化物前驱物(例如,WCl5、WCl6等)流入腔室以蚀刻除去金属氧化物。发明人已观察到,对金属膜具有非常高的蚀刻选择性。可通过使用氟自由基(例如,流动NF3、C4F6)——使用或不使用CCP或ICP等离子体——来蚀刻除去金属氧化物。这可在相同腔室中完成而不会破坏真空。经由氧化和蚀刻的多次循环,沉积于结构的顶表面上的金属膜将被完全移除。进一步氧化将造成单独的柱生长。
在一些实施方式中,在不破坏真空的情况下在单一工艺腔室中进行金属沉积、氧化和化学蚀刻工艺。此单一腔室工艺可增加产量并减少每晶片成本。
在一些集成方案中,相对于电介质膜和金属膜(例如,未氧化的钨)选择性地蚀刻氧化物膜(例如,氧化钨)。本公开内容的实施方式提供使用金属卤化物来对金属和电介质膜具有选择性地完全蚀刻氧化物的方法。在某些情况下,被蚀刻的氧化物膜粘附在基板的表面上方。在一些实施方式中,被蚀刻的氧化物膜粘附在电介质的表面上方。在一个或多个实施方式中,被蚀刻的氧化物被掩模环绕。
本公开内容的一个或多个实施方式针对沉积用于任何保形和/或低至高深宽比间隙/沟槽/空隙填充应用的金属氧化物膜的方法。本公开内容的实施方式有利地提供在具有小尺寸的高深宽比(AR)结构中沉积膜(例如,金属氧化物膜)的方法。本公开内容的一些实施方式有利地提供填充间隙而不在间隙中形成缝的方法。本公开内容的一个或多个实施方式有利地提供形成自对准过孔(via)的方法。
图1示出根据本公开内容的一个或多个实施方式的处理方法。参照图1A,提供具有基板表面105的基板100。基板100具有从基板表面105延伸进入基板100某深度的至少一个特征110。特征110具有底部102和侧壁104。由侧壁和底部形成的开放区域也称为间隙或沟槽。
出于说明的目的,图示出具有三个特征110的基板;然而,本领域技术人员将理解,可具有多于一个的特征。特征110的形状可以是任何合适的形状,包含但不限于沟槽和圆柱形过孔。这样使用时术语“特征”意指任何有意的表面不规则性。特征的合适实例包含但不限于具有顶部、两个侧壁和底部的沟槽,具有顶部和从表面向上延伸的两个侧壁的峰,和具有从带有开放底部的表面向下延伸的侧壁的过孔。特征可具有任何合适的深宽比(特征深度对特征宽度的比)。在一些实施方式中,深宽比大于或等于约5:1、10:1、15:1、20:1、25:1、30:1、35:1或40:1。
如图1B所示,在基板表面105上沉积或形成第一膜120,使得第一膜120覆盖基板表面105并且填充特征110。膜120可为由任何合适的工艺形成的任何合适的膜,所述工艺包含但不限于,化学气相沉积、等离子体增强化学气相沉积、原子层沉积、等离子体增强原子层沉积和/或物理气相沉积。在一些实施方式中,膜120通过原子层沉积或等离子体增强原子层沉积形成。
在一些实施方式中,膜120为金属膜或含金属膜。合适的金属膜包含但不限于包含Co、Mo、W、Ta、Ti、Ru、Rh、Cu、Fe、Mn、V、Nb、Hf、Zr、Y、Al、Sn、Cr和/或La中的一种或多种的膜。在一些实施方式中,金属膜包括钨。在一些实施方式中,膜基本上由指定的金属组成。举例而言,基本上由钨组成的膜意指膜的组成在原子基础上为大于或等于约95%、98%或99%的钨原子。
在一些实施方式中,膜120为连续膜。如本文所使用的,术语“连续”表示覆盖整个暴露表面的层,而没有露出所沉积的层下方的材料的间隙或裸露点。连续层可具有表面积小于膜的总表面积的约1%的间隙或裸露点。
在一些实施方式中,膜120大体上无缝地形成于特征110内。在一些实施方式中,可在特征110的宽度W内形成缝(未示出)。缝可为在特征110的侧壁104之间形成的任何间隙、空间或空隙。
在一些实施方式中,通过原子层沉积(ALD)工艺形成第一膜120。一些实施方式的ALD工艺包括将基板表面依序暴露于金属前驱物和反应物以沉积金属膜。在一些实施方式中,金属前驱物包括金属卤化物化合物。卤素可为任何适合的卤素原子并且可为相同的卤素或不同的卤素。举例而言,金属前驱物可为金属氯化物、金属氟化物、金属溴化物、金属碘化物或与氟、氯、溴或碘原子混合的金属原子。在一个或多个实施方式中,金属卤化物前驱物包括卤化钨。在一些实施方式中,卤化钨包括WCl5或WCl6中的一种或多种。ALD工艺可为时域(time-domain)工艺或空间(spatial)工艺,时域工艺中前驱物与反应物物种不同时存在于处理腔室中,空间工艺中提供前驱物和反应物至处理腔室的不同部分,以气幕(gascurtain)将前驱物与反应物分隔以防止气相反应。在空间ALD工艺中,将基板从具有金属前驱物的第一工艺区域移动至具有反应物的第二工艺区域。
在一些实施方式中,在氧化之前以掺杂剂掺杂膜120。可在形成膜120的同时将掺杂剂并入膜120中,或与膜沉积依序地在单独工艺中将掺杂剂并入膜120中。举例而言,沉积膜可在单独工艺中发生在以掺杂剂掺杂所述膜之前,在相同的工艺腔室中或者在不同的工艺腔室中。在一些实施方式中,膜的沉积与掺杂发生在单一工艺中。举例而言,可将膜前驱物和掺杂剂共同流入处理腔室中以形成膜。
一些实施方式包含任选的处理(treatment)工艺。处理工艺处理膜130以改进膜的某些参数。在一些实施方式中,处理工艺包括使膜退火。在一些实施方式中,可通过在用于沉积和/或还原的相同工艺腔室中原位退火来进行处理。合适的退火工艺包含但不限于快速热处理(RTP)或快速热退火(RTA)、尖峰退火(spike anneal)或UV固化,或电子束固化和/或激光退火。退火温度可在约500℃至约900℃的范围中。退火期间环境的成分可包含H2、Ar、He、N2、NH3、SiH4等中的一种或多种。退火期间的压力可在约100毫托至约1大气压(760托)的范围中。
在形成膜之后,如图1C所示,将基板表面105化学平面化。如以此方式使用的术语“化学平面化”和类似者意指降低对象膜的高度以移除所述膜的至少一部分。在一些实施方式中,将基板表面化学平面化意指大体上无机械平面化处理。
将基板表面105化学平面化可通过依序地氧化和蚀刻第一膜120的顶部125来实现。重复依序的氧化/蚀刻工艺直到已移除第一膜的预定量。在一些实施方式中,第一膜120的顶部125被氧化以在第一膜130的顶部上形成氧化的第一膜130。蚀刻从第一膜120的顶部移除氧化的第一膜130。在氧化/蚀刻的任何循环期间移除的第一膜130的量将取决于例如第一膜130和所使用的氧化剂和蚀刻剂的成分而变化。
如图1D所示,基板表面105的顶部上的第一膜120的高度或厚度随着氧化/蚀刻的每个循环而降低。重复氧化/蚀刻工艺直到从基板表面105移除第一膜120,使得暴露特征110中的第一膜120和基板表面105,如图1E所示。
在一些实施方式中,沉积第一膜130和将基板表面105化学平面化发生在相同的处理腔室中。举例而言,空间ALD处理腔室可具有金属前驱物和反应物的交替区域以沉积第一膜120,随后可将气体供应改变为用于平面化工艺的氧化剂和蚀刻剂。
在一些实施方式中,蚀刻第一膜120包括将第一膜102暴露于金属卤化物化合物。在一个或多个实施方式中,用于蚀刻的金属卤化物化合物与用于膜沉积的金属卤化物前驱物为相同的化合物。在一些实施方式中,蚀刻化合物与金属前驱物具有不同的金属。在一些实施方式中,蚀刻化合物与金属前驱物具有相同的金属而具有不同的取代基(substituentgroup)。
可通过任何合适的技术来完成蚀刻。在一些实施方式中,蚀刻包括将氧化的第一膜130暴露于金属卤化物化合物。在一些实施方式中,金属卤化物化合物具有与第一膜不同的金属。
在一些实施方式中,蚀刻包括暴露于含金属和卤素的前驱物(例如,WCl6)(也称为金属卤化物前驱物)。金属卤化物前驱物可与氧化的第一膜130反应。
在一些实施方式中,暴露于金属卤化物前驱物引起与氧化的第一膜130的放热反应,并且在基板处理区域中不存在等离子体。根据一个或多个实施方式,在进入基板处理区域之前没有等离子体激发金属卤化物前驱物。
在示例性非限制工艺中,第一膜120包括钨并且通过与氧反应而膨胀以形成氧化的第一膜130氧化钨,氧化钨可采用WO3的形式。不受任何特定操作理论的局限,相信将WO3暴露于WCl6(或可能的WCl5)形成挥发性WOCl4和/或WO2Cl2,挥发性WOCl4和/或WO2Cl2离开表面直到所有的氧化钨被移除。一旦氧化钨部分(或通常的金属氧化物部分)被移除,反应可自发地停止。可重复所述工艺整数个循环。每个循环可移除原始钨膜的可选择量(例如,1个或2个单层)。
在一些实施方式中,金属卤化物前驱物包含两种或更多种或仅两种不同元素,包含金属元素和卤素元素。金属卤化物前驱物可包含金属元素的仅单个原子但包含相同卤素元素的多个原子(如WCl6和WCl5的情况)。在实施方式中,金属卤化物的金属元素可包含钛、铪、锆、钒、铌、钽、铬、钼、钨、锰、铼、锝、铁、铝和镓中的一种或多种。在一些实施方式中,金属卤化物的金属元素的原子序数为22、23、24、40、41、42、72、73或74。在一个或多个实施方式中,金属元素包括元素周期表的第4族、第5族或第6族的元素或可为过渡金属。根据一个或多个实施方式,卤素元素可为F和Cl中的一种。在一些实施方式中,卤素元素可为F、Cl、Br和/或I中的一种或多种。在一些实施方式中,含金属和卤素的前驱物不含氟。合适的金属卤化物前驱物的一些实例包含但不限于五卤化钒、五卤化钽、六卤化铬、五卤化钼、六卤化钼、五卤化铌、五卤化钨、六卤化钨和四卤化锰。在一些实施方式中,金属卤化物前驱物包含但不限于钒卤化物、钽卤化物、铬卤化物、钼卤化物、铌卤化物、钨卤化物和/或锰卤化物,其中金属元素的氧化态可为任何合适的氧化态。
在一些实施方式中,在蚀刻工艺中使用很少或不使用局部等离子体来使蚀刻工艺更具选择性、更为精细和更为各向同性。本文将使用术语“无等离子体”来描述在对基板处理区域无等离子体功率或基本上无等离子体功率的应用期间的基板处理区域。所描述的蚀刻剂(含金属和卤素的前驱物)具有能量上有利的蚀刻反应路径,所述蚀刻反应路径使得在蚀刻本文的含金属材料的操作期间基板处理区域能够无等离子体。换句话说,根据一个或多个实施方式,基板处理区域中电子温度可小于0.5eV、小于0.45eV、小于0.4eV或小于0.35eV。此外,在实施方式中,在进入基板处理区域之前,含金属和卤素的前驱物可以未在任何远程等离子体中激发。举例而言,如果远程等离子体区域或单独的腔室区域存在并且用于将含卤素的前驱物导向基板处理区域,那么单独的腔室区域或远程等离子体区域可以是如本文所定义的无等离子体的。
根据一个或多个实施方式,基板处理区域和含金属和卤素的前驱物所通过的任何远程区域可为“无氢的”。在实施方式中,氢和-OH基团可将材料添加至金属和金属氮化物而使得蚀刻工艺受到阻碍。金属膜或金属氮化物膜可变得更厚而不是更薄。在基板处理区域中氢的存在可降低有效的蚀刻选择性。
在一些实施方式中,使用载气来用以下的流率供应含金属和卤素的前驱物(例如,WCl6):于大约5sccm至500sccm的范围中、于大约10sccm至300sccm的范围中、于大约25sccm至200sccm的范围中、于大约50sccm至150sccm的范围中或于大约75sccm至125sccm的范围中。
根据一个或多个实施方式,反应可仅由基板本身的温度激发而以热的方式进行。在使用基板的温度来发生蚀刻反应的实施方式中,术语“无等离子体”在本文中可用于描述在不使用或基本上不使用等离子体功率的应用期间的基板处理区域。也可将等离子体功率保持低于小临界值的量,以使适当的反应能够进行。施加至基板处理区域的等离子体功率可低于100瓦、低于50瓦、低于30瓦、低于10瓦,并且在各种实施方式中可为0瓦。在实施方式中,基板处理区域内的压力可以在大约0.1托和50托的范围中、在大约0.2托和30托的范围中、在大约0.5托和20托的范围中、在大约1托和10托的范围中。
在基板表面105已被化学平面化之后,如图1F所示,使留在特征110中的第一膜120膨胀以使第一柱在所述特征中生长,所述第一柱从特征110垂直于基板表面105延伸。一些实施方式的使第一膜120膨胀包括氧化或氮化所述第一膜。举例而言,第一膜可通过暴露于氧化剂或氧化条件而被氧化,以将金属或含金属膜转化为金属氧化物膜。氧化转化造成原始膜的体积膨胀。膜的膨胀可在约10%至约1000%的范围中,或在约50%至约800%的范围中,或在约100%至约700%的范围中。在一些实施方式中,第一膜120膨胀大于或等于约150%、200%、250%、300%或350%的量。在一些实施方式中,第一膜120膨胀在约300%至约400%的范围中的量。
氧化剂可为任何适合的氧化剂,包含但不限于,O2、O3、N2O、H2O、H2O2、CO、CO2、NH3、N2/Ar、N2/He、N2/Ar/He和上述氧化剂的组合。在一些实施方式中,氧化条件包括热氧化、等离子体增强氧化、远程等离子体氧化、微波和射频(例如,ICP、CCP)。
通过膜的氧化引起的体积膨胀可在任何合适的温度下发生,所述温度取决于举例而言膜和氧化剂的成分。在一些实施方式中,氧化于约25℃至约1100℃的范围中的温度下发生。在一些实施方式中,氧化在大于或等于约250℃、300℃、350℃、400℃、450℃、500℃或550℃的温度下发生。
在膨胀期间,在特征的顶部上维持特征形状的保真度,使得膜从特征110直向上生长而形成柱140。这样使用时,“直向上”意指膜形成邻近特征侧壁114的表面,所述表面与侧壁114大体上共面。当在侧壁114与表面的接合处所形成的角度为±10°时表面与侧壁114共面。换句话说,膨胀的侧壁与基板表面105形成在约80°至约100°的范围中的角度。
根据一个或多个实施方式,基板在形成层之前和/或之后被处理。此处理可在相同的腔室中或在一个或多个分开的处理腔室中进行。在一些实施方式中,将基板从第一腔室移动至分开的第二腔室以进一步处理。可将基板从第一腔室直接移动至分开的处理腔室,或可将基板从第一腔室移动至一个或多个传送腔室,随后将基板移动至分开的处理腔室。因此,处理设备可包括与传送站连通的多个腔室。可以将此类设备称为“群集工具”或“群集系统”等。
一般而言,群集工具是包括多个腔室的模块化系统,多个腔室执行各种功能,包含基板中心寻找和定向、脱气、退火、沉积和/或蚀刻。根据一个或多个实施方式,群集工具包含至少第一腔室和中心传送腔室。中心传送腔室可容纳机械手,所述机械手能够在处理腔室与装载锁定(load lock)腔室之间往复移动基板。通常将传送腔室维持于真空状态,并且提供用于将基板从一个腔室往复移动至另一个腔室和/或位于群集工具前端的装载锁定腔室的中间阶段。可适用于本发明的两种熟知的群集工具是皆可从加利福尼亚州圣克拉拉市的应用材料公司获得的和然而,为了执行如本文所述的工艺的特定步骤,可改变腔室的确切排列和组合。可使用的其他处理腔室包含但不限于,循环层沉积(CLD)、原子层沉积(ALD)、化学气相沉积(CVD)、物理气相沉积(PVD)、蚀刻、预清洁、化学清洁、热处理(例如RTP)、等离子体氮化、脱气、定向、羟基化和其他基板工艺。通过在群集工具上的腔室中执行工艺,在沉积后续膜之前无氧化的情况下可避免大气杂质对基板表面的污染。
根据一个或多个实施方式,基板持续处于真空或“装载锁定(load lock)”状态,并且当从一个腔室移动至下一个腔室时不暴露于周围空气。因此传送腔室处于真空下并在真空压力下“降压(pump down)”。惰性气体可存在于处理腔室或传送腔室中。在一些实施方式中,使用惰性气体作为净化气体,以移除一些或全部反应物。根据一个或多个实施方式,在沉积腔室的出口处注入净化气体,以防止反应物从沉积腔室移动至传送腔室和/或另外的处理腔室。因此,惰性气体流在腔室的出口处形成帘幕。
可在单一基板沉积腔室中处理基板,其中在处理另一个基板之前装载、处理和卸载单一基板。类似于传送带系统,也可以用连续方式处理基板,其中多个基板单独地装载至腔室的第一部分中、移动通过腔室并且从腔室的第二部分卸载。腔室和相关的传送带系统的形状可形成直路径或弯曲路径。此外,处理腔室可为旋转式传送带(carousel),其中多个基板围绕中心轴移动并且在整个旋转式传送带路径上暴露于沉积、蚀刻、退火、清洁等工艺。
在处理期间,可将基板加热或冷却。这样的加热或冷却可通过任何合适的手段来完成,所述手段包含但不限于,改变基板支撑件的温度和使加热或冷却的气体流向基板表面。在一些实施方式中,基板支撑件包含加热器/冷却器,可控制所述加热器/冷却器以传导地改变基板温度。在一个或多个实施方式中,将所采用的气体(反应气体或惰性气体)加热或冷却以局部地改变基板温度。在一些实施方式中,加热器/冷却器位于腔室内邻近基板表面,以对流地改变基板温度。
在处理期间基板也可为静止的或旋转的。旋转的基板可连续旋转或以不连续的步骤旋转。举例而言,基板可在整个工艺中旋转,或基板可在暴露于不同的反应气体或净化气体之间少量地旋转。在处理期间(连续地或以步进地)旋转基板可通过使例如气流几何形状中局部变化的影响最小化来帮助产生更均匀的沉积或蚀刻。
本说明书通篇提及的“一个实施方式”、“某实施方式”、“一个或多个实施方式”或“实施方式”意味着结合所述实施方式描述的特定特征、结构、材料或特性包含于本发明的至少一个实施方式中。因此,本说明书通篇各处出现的例如“在一个或多个实施方式中”、“在某实施方式中”、“在一个实施方式中”或“在实施方式中“的短语并非必须表示本发明的相同的实施方式。此外,特定的特征、结构、材料或特性可以任何合适的方式在一个或多个实施方式中组合。
尽管已参照特定实施方式描述本文的发明,但应理解,这些实施方式仅说明本发明的原理和应用。对于本领域技术人员而言显而易见的是,在不脱离本发明的精神和范围的情况下可对本发明的方法和设备作各种修改和变化。因此,本发明欲包含在权利要求和权利要求的等效物的范围内的修改和变化。
Claims (15)
1.一种处理方法,包括以下步骤:
提供基板,所述基板具有基板表面,所述基板表面具有从所述基板表面延伸进入所述基板的至少一个特征,所述特征具有底部和侧壁;
在所述基板表面上沉积第一膜,使得所述第一膜覆盖所述基板表面并且填充所述特征;
通过依序地氧化所述第一膜的顶部以在所述第一膜的顶部上形成氧化的第一膜并且蚀刻所述氧化的第一膜以移除所述氧化的第一膜,使所述基板表面化学平面化,重复依序的氧化和蚀刻以从所述基板表面移除所述第一膜而留下所述特征中的所述第一膜;和
使所述第一膜膨胀以使第一柱在所述特征中生长,所述第一柱从所述特征垂直于所述基板表面延伸。
2.如权利要求1所述的方法,其中所述第一膜包括金属。
3.如权利要求2所述的方法,其中所述金属包括钨。
4.如权利要求1至3中任一项所述的方法,其中沉积所述第一膜和使所述基板表面化学平面化的步骤在相同的处理腔室中发生。
5.如权利要求1至3中任一项所述的方法,其中使所述第一膜膨胀以使所述第一柱生长的步骤包括氧化所述第一膜或氮化所述第一膜的步骤中的一个或多个。
6.如权利要求5所述的方法,其中通过暴露于O2、O3、H2O、H2O2、H2O4或N2O中的一种或多种来使所述第一柱生长。
7.如权利要求1至3中任一项所述的方法,其中移除所述第一膜以暴露所述基板表面的步骤大体上不包括机械平面化。
8.如权利要求1至3中任一项所述的方法,其中蚀刻所述氧化的第一膜的步骤包括以下步骤:将所述第一膜暴露于金属卤化物化合物。
9.如权利要求8所述的方法,其中所述金属卤化物化合物与所述第一膜具有相同的金属。
10.如权利要求1至3中任一项所述的方法,其中沉积所述第一膜的步骤包括原子层沉积工艺。
11.如权利要求10所述的方法,其中沉积所述第一膜的步骤包括依序暴露于金属卤化物前驱物和反应物以沉积金属膜。
12.如权利要求11所述的方法,其中使所述第一膜化学平面化的步骤包括将所述氧化的第一膜暴露于相同的金属卤化物前驱物。
13.如权利要求12所述的方法,其中所述金属卤化物前驱物包括卤化钨。
14.如权利要求13所述的方法,其中所述卤化钨包括WCl5或WCl6中的一种或多种。
15.一种处理方法,包括以下步骤:
提供基板,所述基板具有基板表面,所述基板表面具有从所述基板表面延伸进入所述基板的至少一个特征,所述特征具有底部和侧壁;
通过依序地暴露于金属前驱物和反应物来在所述基板表面上沉积第一膜以形成第一膜,所述第一膜覆盖所述基板表面并且填充所述特征,所述第一膜包括钨金属并且所述金属前驱物包括卤化钨;
通过依序地氧化所述第一膜的顶部以在所述第一膜的顶部上形成氧化的第一膜并且通过暴露于与所述金属前驱物相同的卤化钨化合物来蚀刻所述氧化的第一膜以移除所述氧化的第一膜,使所述基板表面化学平面化,重复依序的氧化和蚀刻以从所述基板表面移除所述第一膜而留下在所述特征中的所述第一膜;和
通过氧化所述第一膜或氮化所述第一膜的步骤中的一个或多个,使所述第一膜膨胀,以使第一柱在所述特征中生长,所述第一柱从所述特征垂直于所述基板表面延伸,
其中沉积所述第一膜的步骤和使所述基板表面化学平面化的步骤在相同的处理腔室中发生。
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