CN109863590A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN109863590A
CN109863590A CN201680090274.1A CN201680090274A CN109863590A CN 109863590 A CN109863590 A CN 109863590A CN 201680090274 A CN201680090274 A CN 201680090274A CN 109863590 A CN109863590 A CN 109863590A
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China
Prior art keywords
substrate
semiconductor device
reflectance coating
heating part
cover substrate
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Granted
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CN201680090274.1A
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English (en)
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CN109863590B (zh
Inventor
西泽弘一郎
山本佳嗣
宫胁胜巳
渡边伸介
志贺俊彦
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

本发明的半导体装置的特征在于，具备：基板；发热部，其形成于基板之上；盖基板，其在基板的上方以在盖基板与基板之间具有中空部的方式形成；以及反射膜，其在发热部的上方对红外线进行反射。反射膜对由于发热部的温度上升而经由中空部向盖基板侧辐射的红外线进行反射，从而具有抑制盖基板侧的温度上升的作用。由于该作用，即使在模塑树脂存在于盖基板之上的情况下，也产生抑制模塑树脂的温度上升的效果。

Description

半导体装置
技术领域
本发明涉及具有中空部的半导体装置。
背景技术
作为将半导体芯片内置的封装件，利用通过模塑树脂进行封装的塑料封装件。塑料封装件与使用陶瓷进行封装的陶瓷封装件相比具有廉价这一优点。但是，模塑树脂与陶瓷相比耐热温度低，因此有时会由于来自半导体芯片内的发热部的发热，与半导体芯片接触的模塑树脂的温度上升到耐热温度附近以上。其结果，存在模塑树脂碳化，从与半导体芯片之间的界面剥离等问题。
为了抑制模塑树脂的温度上升，使用专利文献1～3所例示的具有中空部的封装构造是有效的。这是因为中空部对半导体芯片的发热部分与模塑树脂之间进行隔热。
专利文献1：日本实开平1-145133号公报
专利文献2：日本特开2006-237405号公报
专利文献3：日本特开2011-18671号公报
发明内容
但是，存在以下这样的问题，即，在来自半导体芯片的发热量大的情况下，即使使用具有中空部的封装构造，从发热部辐射的红外线也经由中空部被模塑树脂吸收，模塑树脂的温度变高。因此，对于发热量大的高输出半导体器件等，有时无法采用使用了模塑树脂的塑料封装件，必须使用具有中空部的陶瓷封装件，封装件价格与塑料封装件相比变高。
本发明就是为了解决上述问题而提出的，其目的在于提供抑制了模塑树脂的温度上升的半导体装置。
本发明的半导体装置具备：基板；发热部，其形成于基板之上；盖基板，其在基板的上方以在盖基板与基板之间具有中空部的方式形成；以及反射膜，其在发热部的上方对红外线进行反射。
发明的效果
根据本发明，针对具有中空部的半导体装置，能够抑制模塑树脂的温度上升。
附图说明
图1是表示实施方式1的半导体装置的剖面图。
图2是表示实施方式1的半导体装置的剖面图。
图3是表示实施方式1的半导体装置的俯视图。
图4是表示实施方式1的半导体装置的变形例的剖面图。
图5是表示将实施方式1的半导体装置封装件化后的状态的剖面图。
图6是表示对实施方式1的半导体装置所使用的基板进行加工的工序的剖面图。
图7是表示对实施方式1的半导体装置所使用的盖基板进行加工的工序的剖面图。
图8是表示将实施方式1的半导体装置封装件化的工序的剖面图。
图9是表示仿真所使用的不具有中空部的构造的斜视图。
图10是表示仿真所使用的不具有中空部的构造的剖面图。
图11是表示仿真所使用的具有中空部的构造的剖面图。
图12是表示具有中空部的构造的发热部的温度分布的图表。
图13是表示实施方式2的半导体装置的剖面图。
图14是表示实施方式3的半导体装置的剖面图。
具体实施方式
实施方式1.
[结构]
对实施方式1的半导体装置1的结构进行说明。图1以及图2是半导体装置1的剖面图，分别是图3中的AA剖面以及BB剖面。图3是半导体装置1的俯视图。但是，在图3中省略盖基板3和反射膜9等的图示。
如图1以及图2所示，在基板2之上形成有发热部4。基板2的材料是SiC，厚度为100μm左右。尽管未图示，但在成为镜面的基板2的上表面使用外延生长出的GaN层和AlGaN层而形成有有源元件即HEMT(High Electron Mobility Transistor)，在GaN层与AlGaN层的界面形成有沟道。这里，发热部4是该沟道。在HEMT形成有栅极电极5、源极电极6以及漏极电极7，它们分别与电极焊盘13～15电连接。这些电极的长度是50～100μm左右，宽度是每根栅极电极5为1～5μm左右，源极电极6和漏极电极7均为10～50μm左右。
此外，这里，示出了半导体装置仅包含1个HEMT的情况，但也可以包含大于或等于2个HEMT。另外，基板2并非一定是SiC基板，也可以是GaAs或Si、SiGe、GaN、InP等基板。另外，有源元件也可以是MOSFET(Metal Oxide Semiconductor Field Effect Transistor)或HFET(Heterostructure Field Effect Transistor)、双极晶体管等。另外，也可以包含电阻、电容、电感等无源元件，它们与有源元件构成电路。
在基板2形成有通路孔22。通路孔22与源极电极焊盘14以及背面电极21电连接。在基板2之上以将发热部4包围的方式设置有接合焊盘11，在接合焊盘11之上设置有封装框18。并且，在栅极电极焊盘13、漏极电极焊盘15之上设置有凸块19。
在基板2之上以覆盖发热部4的方式形成有绝缘膜8。这里，绝缘膜8形成于除了凸块19、封装框18以外的整个区域。
在绝缘膜8之上设置有反射膜9。在俯视观察时，反射膜9形成于比绝缘膜8窄的区域。反射膜8具有反射红外线的性质，在俯视观察时，配置为大致与发热部4重叠。
以由封装框18、凸块19支撑的方式设置有盖基板3。盖基板3的材料是Si，厚度为100μm左右。在盖基板3形成有通路孔23。将栅极电极5以及漏极电极7经由凸块19、电极焊盘16而引出至在盖基板3的上表面设置的电极24。在基板2与盖基板3之间存在中空部10，其高度为10μm左右。中空部10由绝缘膜8、封装框18以及盖基板3包围，确保了气密性。
此外，就实施方式1的半导体装置1而言，盖基板3的下表面整个面成为平面，但在无法充分确保封装框18的高度的情况下，也可以如图4所示是通过将盖基板3设为凹入形状而确保中空部10的构造。这里，盖基板3载置于在基板2之上设置的封装材料25之上，封装材料25由树脂形成。
另外，就实施方式1的半导体装置1而言，盖基板3形成为覆盖基板2的整个表面，但盖基板3并非必须覆盖整个面，也可以是在发热部4的上方具有密闭的中空部10的构造。
另外，也可以在盖基板3形成除了配线以外的构件，例如也可以形成包含形成于基板2之上的HEMT在内的电路所用的匹配电路。并且，作为盖基板3的材料，可以使用具有外延生长面的半导体基板，也可以在盖基板3形成晶体管等有源元件、外延电阻，使用它们构成电路。
接下来，对将半导体装置1封装件化后的结构进行说明。图5是表示将半导体装置1封装件化后的状态的剖面图。在背面电极21之下隔着由AuSn焊料等形成的芯片键合材料30而接合有基座26。基座26用于将源极电极6与外部进行电连接。由于基座26还具有作为散热材料的作用，因此应用散热特性好的部件，作为材料使用例如CuW。另外，为了将漏极电极7、源极电极6与外部进行电连接，引线27经由导线28与在盖基板3的上表面形成的电极24电连接。
在半导体装置1的周围形成有封装了半导体装置1的模塑树脂29。通过由模塑树脂29进行封装，从而相对于外部对半导体装置1进行保护。
这里，对设想为100W左右的发热的半导体装置的情况进行叙述。在图3中示出了栅极电极5为2根的情况，但在设想为100W左右的发热的半导体装置的情况下，栅极电极的长度成为500μm左右，栅极电极的根数成为50～100根左右。这样，HEMT的宽度成为2～4mm。
在如上述所示存在100W左右的发热的情况下，发热部的温度有时成为100～300℃左右。根据维恩位移定律，黑体辐射的峰值波长λ(μm)由下式给出，其中将T设为温度(℃)。
λ＝2896/(T+273)
如果使来自发热部4的辐射的峰值波长也近似地遵守该式，则在温度为100～300℃的情况下峰值波长为5.1～7.8μm。该范围的波长被归类为中波长红外线(3～8μm)。
[制造方法]
对实施方式1的半导体装置1的制造方法、以及将半导体装置1通过模塑树脂进行封装的方法进行说明。
按照图6来说明针对基板2的加工。图6是图3中的BB剖面。尽管未图示，但设为在基板2之上已经层叠有GaN层、AlGaN层。首先，如图6(a)所示在基板2上表面形成栅极电极5、源极电极6、漏极电极7、接合焊盘11以及电极焊盘13～15。但是，在图2中，在剖面中未出现电极焊盘13以及15，因此未图示出这些电极焊盘。接合焊盘11、电极焊盘13～15是在封装框18、凸块19相对于基板2密接性差的情况下，在封装框18、凸块19为向基板2进行扩散的材料的情况下，作为其对策而形成的。例如，在封装框18、凸块19的材料为Au的情况下，将与它们的接触面设为Au即可，因此在抗蚀剂图案化之后，通过蒸镀而依次形成Ti、Au，然后通过剥离而形成图案。金属的结构例如设为在形成50nm的Ti之后形成500nm的Au。Ti用于确保与盖基板3之间的密接性和阻挡性，Au用于确保与封装框18、凸块19之间的密接性。这里，在使Au、AuSn作为封装框18、凸块19的材料的情况下进行说明，因此使接合焊盘12、电极焊盘16的表面也为Au，但在使用其它金属作为封装框18、凸块19的材料的情况下，需要与它们相匹配地选择接合焊盘11、电极焊盘13～15的最表面的金属材料。
接下来，如图6(b)所示形成绝缘膜8和反射膜9。为了形成绝缘膜8，首先将感光性的聚酰亚胺材料涂敷至晶片整个面，通过光掩模而曝光、显影，在封装框18以及凸块19的形成部位制作开口。然后，如果在氮气氛中，在200℃～300℃下进行1小时左右的烘烤，则聚酰亚胺材料的溶剂排出，同时通过交联反应而酰亚胺化，形成作为永久膜的绝缘膜8。接下来，将反射膜9形成于发热部4的上方、绝缘膜之上。反射膜9是将Au作为材料，通过蒸镀剥离而形成的。或者，也可以通过以下方法等而形成，即，在通过金属溅射法形成于整个面之后，进行抗蚀剂图案化，通过离子铣削法等而去除不需要的部分。
接下来，如图6(c)所示对基板2的背面侧进行切削而使其薄板化。在对基板2进行磨削之后，通过抛光而将损伤层去除。使基板2的厚度例如是100μm左右。
接下来，如图6(d)所示进行通路孔22和背面电极21的形成。在基板2的薄板化加工后的面进行抗蚀剂图案化，通过湿蚀刻或者干蚀刻而进行通路孔22的形成。然后，在基板2的下表面形成背面电极21。由于难以通过溅射、蒸镀而在通路孔22中得到厚的金属膜，因此例如通过溅射将Ti、Au连续成膜，之后进一步通过电镀而镀敷几μm左右的Au。图案化例如是在镀敷之后通过抗蚀剂而进行图案化，通过湿蚀刻、铣削而去除不需要的部分。
接下来，如图6(e)所示将Au作为材料而同时形成封装框18以及凸块19。但是，在图6(e)中，在剖面之上不存在凸块19，因此凸块19未图示。通过抗蚀剂将封装框18的部位和凸块19的部位排除在外而进行图案化，之后通过溅射将Au形成为300nm的厚度而作为晶种层，进一步再通过1层抗蚀剂将封装框18的部位和凸块19的部位排除在外而进行图案化，将封装框18和凸块19的晶种层露出。针对露出部进行电解Au镀敷，形成相同的高度的封装框18以及凸块19。然后，如果依次进行抗蚀剂去除、铣削、抗蚀剂去除，则完成封装框18以及凸块19。此外，封装框18和凸块19也可以分别形成，这种情况下，封装框18并非必须是导电性的金属，因此也可以由聚酰亚胺等有机材料、玻璃等无机材料制作。另外，形成方法也可以是无电解镀敷，还可以通过印刷法、喷墨法对将金属颗粒等材料混入至溶剂得到的混合物进行图案化。
由此，完成针对基板2的加工。
按照图7说明针对盖基板3的加工。图7是图3中的AA剖面。首先，如图7(a)所示进行接合焊盘12、电极焊盘16的形成。作为形成方法而存在如下方法等，即，在抗蚀剂图案化之后，通过蒸镀剥离来形成的方法，在通过金属溅射法形成于整个面之后，进行抗蚀剂图案化，通过离子铣削法等去除不需要的部分的方法。金属的结构设为例如在形成50nm的Ti之后形成500nm的Au。Ti用于确保与盖基板3之间的密接性和阻挡性，Au用于确保与封装框18、凸块19之间的密接性。这里，在将Au、AuSn作为封装框18、凸块19的材料的情况下进行说明，因此使接合焊盘12、电极焊盘16的表面也为Au，但在使用其它金属作为封装框18、凸块19的材料的情况下，需要与它们相匹配地选择接合焊盘12、电极焊盘16的最表面的金属材料。
接下来，如图7(b)所示对盖基板3的上表面侧进行切削而使其薄板化。在对盖基板3进行磨削之后，通过抛光而将损伤层去除。使盖基板3的厚度例如是100μm左右。
接下来，如图7(c)所示进行通路孔23和电极24的形成。在盖基板3的薄板化加工后的面进行抗蚀剂图案化，通过湿蚀刻或者干蚀刻而进行通路孔23的形成。根据盖基板3的材质，有时不存在与抗蚀剂之间的加工选择比，因此取代抗蚀剂而将Ni等金属材料图案化。然后，在盖基板3的上表面通过溅射而将Ti、Au连续成膜，之后通过电镀进一步镀敷几μm左右的Au，由此形成电极24。
由此，完成针对盖基板3的加工。
将加工完成后的基板2与盖基板3进行对准，之后升温、加压而进行接合。如这里所示的那样在将都以Au为材料的封装框18、凸块19与接合焊盘12、电极焊盘16进行接合的情况下，如果向两者的接合面照射Ar等离子体而对表面进行切削，在得到了活性化的状态下进行接合，则Au彼此的界面消失而成为接合的状态。就接合状态而言，接合面的平坦度越高、接合时的温度越高、接合时的压力越高，则接合状态越好，例如，设为平坦度Ra＝2～3nm，温度是300℃，压力是100MPa等即可。
对以上述方式接合后的基板2和盖基板3进行切割而完成具有中空部10的半导体装置1。
进一步地，按照图8说明将半导体装置1由模塑树脂29进行封装的方法。首先，如图8(a)所示对半导体装置1在由CuW等形成的基座26之上进行芯片键合。然后，在电极24与引线27之间通过导线28进行配线。作为芯片键合材料30，选择耐热性、散热性好的材料即可，使用AuSn焊料、散热性更高的烧结Ag等即可。
接下来，如图8(b)所示将芯片键合后的半导体装置1置于模具31，向模具31之中使模塑树脂29从模塑树脂注入口32流入。模塑树脂29通过在高压下流入，从而能够无间隙地注入至半导体装置1与模具31之间，能够使成型稳定化。
最后，如图8(c)所示取下模具31，完成由模塑树脂29实现的封装。
[效果]
对实施方式1的半导体装置1所应用的技术方案所实现的效果进行说明。中空部10对发热部4与盖基板3、模塑树脂29之间进行隔热。因此，中空部10具有防止来自发热部4的热传导至模塑树脂29的作用，抑制模塑树脂29的温度上升。但是，如上述所示，在来自发热部4的发热量为100W左右的情况下，发热部4的温度达到100～300℃。从温度达到了100～300℃的发热部4辐射的红外线被盖基板3、模塑树脂29吸收，引起模塑树脂29的温度上升。
这里，对仿真进行说明，该仿真确认了通过设置中空部10从而抑制模塑树脂29的温度上升。作为仿真的模型，使用了不具有中空部的构造和具有中空部的构造。
对仿真所使用的不具有中空部的构造进行说明。图9是不具有中空部的构造的斜视图，图10是不具有中空部的构造的剖面图。在不具有中空部的构造中，在固定于85℃的铝块33之上设置有1mm厚的CuW基座26。然后，在基座26之上通过10μm厚的AuSn芯片键合材料30而芯片键合有100μm厚的SiC基板2。在基板2之上形成有GaN HEMT，使该HEMT的沟道为发热部4。此外，使形成有HEMT的层的厚度薄，省略原本在基板2之上形成的外延层，使发热部4形成于基板2上表面的一部分。使HEMT的栅极宽度为50.4mm，栅极叉指数量为120，使工作时的发热量为97W。基座26以及基板2的上部由模塑树脂29覆盖。
对仿真所使用的具有中空部的构造进行说明。图11是具有中空部的构造的剖面图。在该构造中，在基板2的上部夹着10μm厚的中空部10而形成有100μm厚的Si盖基板3。使中空部10充满氮。其它条件与不具有中空部的构造相同。
实施仿真后可知，模塑树脂的最高温度在不具有中空部的构造时是187.97℃，在具有中空部的构造时是143.00℃，具有中空部的构造的该最高温度大幅度降低。但是，相对于通常的模塑树脂的耐热温度即150℃没有余量。因此，需要用于对模塑树脂的温度上升进行抑制的进一步的对策。以下，对由该对策即反射膜的导入实现的效果进行叙述。
如实施方式1的半导体装置1所示，如果具有反射膜9，则从发热部4辐射的红外线被反射，因此红外线被盖基板3、模塑树脂29吸收的比例变小，模塑树脂29的温度上升进一步得到抑制。
通常，发热部4的温度在其中心附近最高，随着移向周边而温度变低。根据斯蒂芬·玻尔兹曼定律，来自黑体的辐射能量与绝对温度(K)的4次方成比例。如果使来自发热部4的辐射能量也近似地与绝对温度的4次方成比例，则可知，来自中心附近的辐射能量最大，随着移向周边而辐射能量变小。因此，优选反射膜9在俯视观察时以覆盖发热部4的中心的方式配置。图12是对具有中空部的构造中的发热部4的温度分布通过仿真进行计算而得到的结果。如果观察该图，则可知，发热部4中的温度高的区域是发热部4的中心的8成左右的长度的区域。如果换算至平面，则温度高的区域是8成×8成＝6.4成左右的面积的区域。即，优选反射膜9在俯视观察时以至少覆盖发热部4的中心部的6成左右的面积的方式配置。进一步地优选至少覆盖发热部4的整个面。
另外，优选反射膜9高效地对红外线进行反射，因此反射膜9的反射率越高越好。另外，就反射率与吸收率的关系而言，如果设为没有透射，则
反射率＝1-吸收率。
并且，根据与辐射相关的基尔霍夫定律，
吸收率＝辐射率。
即，
反射率＝1-辐射率。
通过来自发热部4的热传导，反射膜9的温度也变高，因此在反射膜9使用了辐射率高的材料的情况下，来自反射膜9的红外线辐射的能量变高，引起模塑树脂29的温度上升。因此，为了抑制该温度上升，只要使反射膜9的辐射率小即可。即，只要使反射膜9的反射率大即可。由此，优选中波长红外线区域的反射率大于或等于0.9。并且，适于作为反射膜9的材料的是中波长红外线的反射率高、透射率以及吸收率低的金属等。具体地说，是Al、黄铜、Cu、Au、Ni、Pt、Ag、Zn以及Pd等。另外，作为反射膜9，也可以使用包含反射率高的物质层的多层膜。
另外，在向金属射入了红外线的情况下，红外线几乎不到达从金属的表面算起深度大于或等于0.03μm之处，在使用金属作为反射膜9的材料的情况下，优选使其厚度大于或等于0.03μm。
另外，优选反射膜9的上表面和下表面(与绝缘膜之间的粘接面)的反射率均高，但即使在仅某一个面反射率高的情况下，也能够得到效果。例如在仅下表面反射率高的情况下，从发热部4辐射的红外线被反射，因此能够抑制模塑树脂29的温度上升。另外，在仅上表面反射率高的情况下，即使在反射膜9的上表面的温度变高的情况下，也抑制了来自反射膜9的上表面的红外线辐射的能量，因此能够抑制模塑树脂29的温度上升。反射膜的上表面或者下表面的仅某一个面反射率高的状况是在反射膜的仅某一个面氧化而形成了层这样的情况下实现的。
此外，反射率还依赖于反射膜9的下表面的表面状态，该面被称为光泽面、镜面以及研磨面等，优选是表面粗糙度(Ra)小于或等于几nm～几十nm的面。相反，表面越粗糙，反射率越降低，因此也可以以防止表面氧化为目的，通过中波长红外线易于透射的绝缘膜(SiO等)而对反射膜9的下表面进行覆盖。
另外，中空部10也可以充满例如氮等干燥空气，但更优选使其成为真空状态。氮的热传导率为0.024W/m·K左右，半导体的Si的热传导率为168W/m·K左右，因此氮的热传导率与Si相比低4个数量级。在真空状态下与此相比热传导率变低，从发热部4向模塑树脂29的热传导进一步变少。
基板2的材料优选是热传导率高的材料。来自发热部的散热路径是从基板2的背面经过芯片键合材料30而到达基座26的路径，因此基板2的热传导率越高，散热效率变得越高。半导体基板之中SiC基板的热传导率高，适于作为材料。
优选盖基板3的热传导率比基板2低。由发热部4产生的热的一部分通过热传导和辐射而到达盖基板3，但盖基板3的热传导率比基板2低，因而由发热部4产生的热有可能选择性地从基板2向基座26逸散大量的热，抑制了模塑树脂29的温度上升。
实施方式2.
对实施方式2的半导体装置进行说明。实施方式2的半导体装置与实施方式1的半导体装置的主要差异在于反射膜的形成部位。这里，主要对该差异进行说明。
图13是半导体装置101的剖面图。反射膜9形成于盖基板3的与基板2相对的面之上。因此，如在实施方式1中说明的那样，反射膜9防止从发热部4辐射的红外线抵达盖基板3、模塑树脂29，因此抑制了模塑树脂29的温度上升。这里，省略了实施方式1的绝缘膜8，但即使存在绝缘膜也没关系。
此外，反射膜9也可以是包含反射率高的物质层的大于或等于2层的层叠膜，仅与基板2最近的层具有反射的功能即可。例如，也可以为以下这样的2层构造，即，将与盖基板3之间的密接性好的Ti用作与盖基板3粘接的层的材料，将与Ti之间的密接性好且红外线的反射率也高的Au用作与基板2接近的层的材料。
实施方式3.
对实施方式3的半导体装置进行说明。实施方式3的半导体装置与实施方式1的半导体装置的主要差异在于反射膜的形成部位。这里，主要对该差异进行说明。
图14是半导体装置201的剖面图。反射膜9形成于盖基板3的与基板2相对的面的相反的面之上。因此，如在实施方式1中说明的那样，反射膜9防止从发热部4辐射的红外线抵达模塑树脂29，因此抑制了模塑树脂29的温度上升。这里，省略了实施方式1的绝缘膜8，但即使存在绝缘膜也没有关系。
此外，由于盖基板3由Si形成，因此红外线的吸收少，从发热部4辐射的红外线的大部分进行透射。因此，来自发热部4的红外线的大部分到达反射膜9，朝向基板2侧而被反射。这样，就盖基板3而言，优选红外线的吸收率低，作为材料除了Si以外，也可以是SiC、GaAs、Si、SiGe、GaN、InP等。
另外，反射膜9也可以是包含反射率高的物质层的大于或等于2层的层叠膜，仅与基板2最远的层具有反射的功能即可。例如，也可以为以下这样的2层构造，即，将与盖基板3之间的密接性好的Ti用作与盖基板3粘接的层的材料，将与Ti之间的密接性好且红外线的反射率也高的Au用作远离基板2的层的材料。
[关于实施方式1～3]
此外，分别应用于实施方式1～3的技术方案既可以如上述所示分别单独地使用，也可以将这些技术方案进行组合而使用。
标号的说明
1、101、201半导体装置，2基板，3盖基板，4发热部，5栅极电极，6源极电极，7漏极电极，8绝缘膜，9反射膜，10中空部，11、12接合焊盘，13、14、15、16电极焊盘，18封装框，19凸块，21背面电极，22、23通路孔，24电极，25封装材料，26基座，27引线，28导线，29模塑树脂，30芯片键合材料，31模具，32模塑树脂注入口，33铝块。

Claims (13)

1.一种半导体装置，其具备：
基板；
发热部，其形成于所述基板之上；
盖基板，其在所述基板的上方以在所述盖基板与所述基板之间具有中空部的方式形成；以及
反射膜，其在所述发热部的上方对中波长红外线进行反射。
2.根据权利要求1所述的半导体装置，其特征在于，
具备：绝缘膜，其在所述基板之上以覆盖所述发热部的方式形成，
所述中空部形成于所述绝缘膜与所述盖基板之间，
所述反射膜形成于所述绝缘膜之上。
3.根据权利要求1所述的半导体装置，其特征在于，
所述反射膜形成于所述盖基板的面中的与所述基板相对的相对面之上。
4.根据权利要求1所述的半导体装置，其特征在于，
所述反射膜形成于所述盖基板的面中的与所述基板相对的相对面的相反的面之上。
5.根据权利要求1至4中任一项所述的半导体装置，其特征在于，
所述反射膜在俯视观察时覆盖所述发热部的中心的至少6成的面积。
6.根据权利要求5所述的半导体装置，其特征在于，
所述反射膜在俯视观察时覆盖所述发热部的至少整个面。
7.根据权利要求1至6中任一项所述的半导体装置，其特征在于，
所述反射膜的相对于中波长红外线的反射率大于或等于0.9。
8.根据权利要求7所述的半导体装置，其特征在于，
所述反射膜的相对于波长范围为5.1～7.8μm的红外线的反射率大于或等于0.9。
9.根据权利要求1至8中任一项所述的半导体装置，其特征在于，
所述反射膜包含由金属形成的层。
10.根据权利要求9所述的半导体装置，其特征在于，
所述反射膜包含由Al、黄铜、Cu、Au、Ni、Pt、Ag、Zn、Pd中的任意的金属形成的层。
11.根据权利要求1至10中任一项所述的半导体装置，其特征在于，
所述中空部是真空的。
12.根据权利要求1至11中任一项所述的半导体装置，其特征在于，
所述盖基板的热传导率比所述基板低。
13.根据权利要求1至12中任一项所述的半导体装置，其特征在于，
所述基板由SiC形成。
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Publication number Priority date Publication date Assignee Title
CN110494963B (zh) 2017-03-29 2023-06-13 三菱电机株式会社 中空封装器件及其制造方法
US20220044978A1 (en) * 2019-03-06 2022-02-10 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing the same
CN114964513A (zh) * 2021-02-18 2022-08-30 Tdk株式会社 热敏电阻元件及电磁波传感器

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5021663A (en) * 1988-08-12 1991-06-04 Texas Instruments Incorporated Infrared detector
CN1713214A (zh) * 2004-06-15 2005-12-28 富士通株式会社 图像拾取装置及其生产方法
CN101459165A (zh) * 2007-12-13 2009-06-17 夏普株式会社 电子元件晶片模块、其制造方法以及电子信息设备
EP2595186A2 (en) * 2011-11-16 2013-05-22 Kabushiki Kaisha Toshiba High frequency semiconductor package
CN103117254A (zh) * 2010-11-18 2013-05-22 株式会社东芝 封装
CN103681522A (zh) * 2012-09-18 2014-03-26 三菱电机株式会社 半导体装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01145133A (ja) 1987-11-21 1989-06-07 Mazda Motor Corp 表皮材を有する合成樹脂成形品の製造方法
JPH0741158Y2 (ja) 1988-03-28 1995-09-20 ローム株式会社 半導体装置
JPH0638331U (ja) * 1992-10-23 1994-05-20 株式会社東芝 電子部品装置
JP2006237405A (ja) 2005-02-25 2006-09-07 Toshiba Corp 電子部品装置
JP4830074B2 (ja) * 2006-04-11 2011-12-07 セイコーエプソン株式会社 圧電デバイスおよび電子デバイスの製造方法
WO2009070348A1 (en) 2007-11-30 2009-06-04 Skyworks Solutions, Inc. Wafer level packaging using flip chip mounting
JP4800291B2 (ja) * 2007-12-13 2011-10-26 シャープ株式会社 センサモジュールの製造方法および電子情報機器の製造方法
EP2447705A1 (en) 2009-06-25 2012-05-02 Panasonic Corporation Infrared gas detector and infrared gas measuring device
JP2011018671A (ja) 2009-07-07 2011-01-27 Japan Radio Co Ltd デバイス封止体及びデバイス封止体の製造方法
JP2011203226A (ja) * 2010-03-26 2011-10-13 Panasonic Electric Works Co Ltd 赤外線センサモジュール
TWI466346B (zh) * 2010-10-19 2014-12-21 Advanced Optoelectronic Tech 覆晶式led封裝結構
JP2014035817A (ja) * 2012-08-07 2014-02-24 Panasonic Corp 赤外光源
TW201432860A (zh) * 2013-02-01 2014-08-16 Oriental System Technology Inc 晶片型紅外線發射器封裝件
JP6279857B2 (ja) * 2013-08-29 2018-02-14 京セラ株式会社 電子装置、多数個取り枠体および多数個取り電子装置
US10018788B2 (en) * 2014-10-28 2018-07-10 Hewlett Packard Enterprise Development Lp Photonic interposer with wafer bonded microlenses
GB201509766D0 (en) * 2015-06-05 2015-07-22 Element Six Technologies Ltd Method of fabricating diamond-semiconductor composite substrates
WO2017029822A1 (ja) 2015-08-18 2017-02-23 三菱電機株式会社 半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5021663A (en) * 1988-08-12 1991-06-04 Texas Instruments Incorporated Infrared detector
US5021663B1 (en) * 1988-08-12 1997-07-01 Texas Instruments Inc Infrared detector
CN1713214A (zh) * 2004-06-15 2005-12-28 富士通株式会社 图像拾取装置及其生产方法
CN101459165A (zh) * 2007-12-13 2009-06-17 夏普株式会社 电子元件晶片模块、其制造方法以及电子信息设备
CN103117254A (zh) * 2010-11-18 2013-05-22 株式会社东芝 封装
EP2595186A2 (en) * 2011-11-16 2013-05-22 Kabushiki Kaisha Toshiba High frequency semiconductor package
CN103681522A (zh) * 2012-09-18 2014-03-26 三菱电机株式会社 半导体装置

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