CN109817566A - 具有基本上直的接触轮廓的半导体结构 - Google Patents

具有基本上直的接触轮廓的半导体结构 Download PDF

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CN109817566A
CN109817566A CN201810185273.6A CN201810185273A CN109817566A CN 109817566 A CN109817566 A CN 109817566A CN 201810185273 A CN201810185273 A CN 201810185273A CN 109817566 A CN109817566 A CN 109817566A
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structure according
oxide layer
barrier material
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oxidation
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R·瑙曼
M·青克
R·赛德尔
T·巴彻维茨
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GlobalFoundries Inc
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Abstract

本发明涉及具有基本上直的接触轮廓的半导体结构。本公开涉及半导体结构，更特别地，涉及具有基本直的接触轮廓的半导体结构以及制造方法。该结构包括：阻挡材料，其包括位于与绝缘材料的界面处的上氧化层；以及互连接触结构，其具有穿过所述阻挡材料的所述氧化层的基本上直的轮廓。

Description

具有基本上直的接触轮廓的半导体结构
技术领域
本公开涉及半导体结构，更特别地，涉及具有基本上直的接触轮廓的半导体结构以及制造方法。
背景技术
半导体器件包括许多不同的布线层。这些布线层形成在层间电介质材料中并且可以包括布线结构、互连接触、无源器件和有源器件。互连接触设置在管芯的不同布线层中以连接到不同的结构，例如，不同的布线结构等。
在制造半导体器件时，粘合层典型地形成在布线结构上方的例如体SiCOH材料的层间电介质材料的底表面处。但是，粘合层具有与层间电介质材料不同的蚀刻速率，导致锥形过孔轮廓。换言之，由于层间电介质材料和粘合层的蚀刻速率不同，因此这些材料将以不同的速率蚀刻，导致粘合层内的锥形轮廓。锥形过孔轮廓进而导致具有锥形轮廓的互连接触。互连接触的这种锥形轮廓导致电性能问题，包括例如铜的金属材料中的空隙形成以及依赖于时间的栅极氧化物击穿(TDDB)。
还已知这些不同的材料的蚀刻是难以控制的，因为不可能一致地测量粘合层的厚度。而且，不同厚度的粘合层将产生不同的锥形过孔轮廓。
发明内容
在本公开的方面中，一种结构包括：阻挡材料，其包括位于与绝缘材料的界面处的上氧化层；以及互连接触结构，其具有穿过所述阻挡材料的所述氧化层的基本上直的轮廓。
在本公开的方面中，一种结构包括：形成在绝缘体材料中的布线层；阻挡材料，其包括由氧化材料构成的上表面；直接位于所述上表面上的层间电介质材料；以及延伸到所述布线层、延伸穿过所述阻挡材料、所述氧化材料和所述层间电介质材料的接触，所述接触在所述氧化材料内具有基本上直的轮廓。
在本公开的方面中，一种方法包括：在布线结构之上形成阻挡材料；氧化所述阻挡材料以形成上氧化层；在所述氧化层之上形成层间电介质材料；将过孔蚀刻到所述层间电介质材料、所述氧化层和所述阻挡材料中以暴露所述布线结构，所述过孔具有穿过所述氧化层的基本上直的过孔轮廓；以及在所述过孔内形成接触，所述接触具有穿过所述氧化层的基本上直的轮廓。
附图说明
通过本公开的示例性实施例的非限制性实例并参考所述多个附图，在以下详细描述中描述本公开。
图1示出了根据本公开的方面的结构以及相应的制造工艺。
图2示出了根据本公开的方面的除了其他特征之外的具有基本上直的轮廓的过孔以及相应的制造工艺。
图3示出了根据本公开的方面的除了其他特征之外的具有基本上直的轮廓的互连接触以及相应的制造工艺。
具体实施方式
本公开涉及半导体结构，更特别地，涉及具有基本上直的接触轮廓的半导体结构以及制造方法。更具体地，本公开提供了在层间电介质材料下方的在阻挡层中的氧化膜内的基本上直的或垂直的互连接触轮廓。有利地，通过使用氧化膜，本公开提供了更可控的过孔蚀刻工艺，导致互连接触的电参数值的改善，例如，空隙和依赖于时间的栅极氧化物击穿(TDDB)的减少。
在实施例中，氧处理被提供给例如低k电介质绝缘体材料的BLoK层的上表面。这种氧处理将改善层间电介质材料与BLoK层之间界面处的锥度控制，例如，蚀刻。也就是说，通过提供氧处理，BLoK层的氧化层将具有与层间电介质层类似的蚀刻速率。所得到的过孔轮廓将进而在两种材料之间的界面处具有直的或基本上直的轮廓，例如，相对于水平电介质表面测量的大致90度，因为氧化层和层间电介质层将具有类似的蚀刻速率。另外，通过实施本文所述的工艺，能够消除在蚀刻工艺期间典型地导致锥形过孔轮廓的在层间电介质层的底部处形成的粘合层。
本公开的结构可以使用多种不同的工具以多种方式来制造。一般而言，方法和工具被用于形成具有微米和纳米尺寸的结构。已从集成电路(IC)技术中采用了用于制造本公开的结构的方法，即，技术。例如，该结构可以建立在晶片上，并且以通过光刻工艺被图案化的材料膜来实现。特别地，该结构的制造使用三个基本构建块：(i)将薄膜材料沉积在衬底上，(ii)通过光刻成像在膜的顶部施加图案化的掩模，以及(iii)选择性地将膜蚀刻到掩模。
图1示出了根据本公开的方面的结构以及相应的制造工艺。具体地，结构10包括形成在绝缘体材料14中的布线结构12。在实施例中，绝缘体材料14可以是基于氧化物的材料。金属布线结构12可以例如使用常规的光刻、蚀刻和沉积工艺由铜材料形成。
例如，为了形成布线结构12，将形成在绝缘体材料14上的抗蚀剂暴露于能量(光)以形成图案(开口)。例如反应离子蚀刻(RIE)的具有选择性化学(chemistry)的蚀刻工艺将被用于通过抗蚀剂的开口在绝缘体材料14中形成一个或多个沟槽。然后可以通过常规的氧灰化工艺或其他已知的剥离剂(stripant)来去除抗蚀剂。在去除抗蚀剂之后，可以通过例如电镀工艺的任何常规的沉积工艺来沉积导电材料。可以通过常规的化学机械抛光(CMP)工艺去除绝缘体材料14的表面上的任何残留材料。
仍然参考图1，在绝缘体材料14和布线结构12之上形成阻挡材料16。在实施例中，阻挡材料16是低k电介质层，例如，氮化物材料。在更具体的实施例中，阻挡材料16可以是NBLoK(NBLoK是Applied Materials,Inc.的商标)，其是掺杂氮的碳化硅材料。在实施例中，依赖于技术节点，可以通过例如化学气相沉积(CVD)工艺的任何常规的沉积工艺将阻挡材料16沉积到的特定厚度。通过非限制性示例的方式，阻挡层的厚度和氧化层的厚度应该平衡，使得剩余阻挡厚度仍然足以充当扩散阻挡。
在实施例中，阻挡材料16经历氧处理以形成氧化层18。在实施例中，氧化层18可以位于阻挡材料的上表面处，并且更具体地，依赖于技术节点，可以延伸约5nm至约25nm；尽管在此也提供了其他厚度。在更具体的实施例中，氧化层18可以是阻挡材料16的厚度的约20％至约30％。在一个具体的实施例中，对于35nm厚的阻挡材料16，氧化层18可以为约5nm。
氧处理可以在氧气氛中提供。氧气氛可以是例如在CVD室中的载气中的O2、NO2或CO2。例如，氧处理可以在沉积工艺开始之后使用与沉积工艺相同的CVD室来提供。例如，氧化处理可以在阻挡材料16的沉积工艺开始之后或结束时提供。以这种方式，可以原位提供氧化。可选地，可以在沉积层间电介质材料之前在外部工具中或在沉积室内提供氧处理，例如，在SiCOH沉积之前的氧预处理。作为示例，在沉积工艺之后，可以使用远程等离子体工具来提供氧处理。在实施例中，氧处理不应该影响下方的金属特征，例如，布线结构12。
仍参考图1，层间电介质材料20沉积在阻挡材料16之上，并且在更具体的实施例中，层间电介质材料20可以为使用例如CVD的常规毯式沉积工艺直接沉积在氧化层18上的体SiCOH。因此，在后一种实现中，氧处理工艺将在层间电介质材料20的沉积之前发生。在实施例中，层间电介质材料20和氧化层18的蚀刻速率是类似的，正如本领域的技术人员应当理解的那样。硬掩模22、24的叠层沉积在层间电介质材料20上。在实施例中，作为示例，硬掩模22是ILD硬掩模22并且硬掩模24是TiN硬掩模。
图2示出了形成在图1的结构内的过孔26。在实施例中，过孔26可以通过常规的双镶嵌或单镶嵌工艺形成，如本领域技术人员应该理解的那样，使得在此不需要进一步的解释。由于层间电介质材料20和氧化层18的蚀刻速率具有基本相同的蚀刻速率，因此形成在氧化层18内的过孔的部分将具有基本上直的轮廓28(而不考虑氧化层的厚度)。在实施例中，基本上直的轮廓28是指相对于电介质材料或下方的布线结构12的水平表面测量的大致90度。蚀刻工艺可以使用例如RIE工艺的常规蚀刻循环来执行，其中除了其他层之外，层间电介质材料20和氧化层18一起被蚀刻以暴露下方的布线结构12。
图3示出了除了其他特征之外的形成在过孔26中的具有基本上直的轮廓的互连接触30。在互连材料的沉积之前，可以通过已知的剥离工艺去除硬掩模。作为示例，互连接触30将通过常规沉积工艺在过孔内形成，然后执行化学机械抛光(CMP)。在实施例中，钨的沉积可以是CVD工艺，铝的沉积可以是等离子体气相沉积(PVD)工艺，以及其他金属或金属合金材料可以通过电镀工艺沉积。直的轮廓是由于互连材料沉积在具有直的轮廓28的过孔内的这样的事实。
如上所述的方法用在集成电路芯片的制造中。所得到的集成电路芯片可以由制造商以作为裸芯片的原始晶片形式(即，作为具有多个未封装芯片的单个晶片)或者以封装形式分发。在后一种情况下，芯片被安装在单芯片封装(诸如塑料载体中，其引线固定到母板或其他更高级别的载体)或多芯片封装(诸如陶瓷载体中，其具有表面互连和/或掩埋互连中的一者或两者)中。在任何情况下，芯片然后与其他芯片、分立电路元件和/或其他信号处理设备集成，作为(a)中间产品(诸如母板)或者(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其他低端应用，到具有显示器、键盘或其他输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已为了示例的目的而给出，但并非旨在是穷举性的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的被选择以旨在最好地解释实施例的原理、实际应用或对市场中发现的技术的技术改进，或者使本技术领域的其他普通技术人员能理解本文公开的实施例。

Claims (20)

1.一种结构，包括：
阻挡材料，其包括位于与绝缘材料的界面处的上氧化层；以及
互连接触结构，其具有穿过所述阻挡材料的所述氧化层的基本上直的轮廓。
2.根据权利要求1所述的结构，其中所述互连接触结构延伸穿过所述绝缘材料。
3.根据权利要求2所述的结构，其中所述绝缘材料是由SiCOH构成的电介质材料。
4.根据权利要求1所述的结构，其中所述氧化层为所述阻挡材料的厚度的约20％至30％。
5.根据权利要求1所述的结构，其中所述互连接触结构延伸到下方的布线结构。
6.根据权利要求1所述的结构，其中所述绝缘材料和所述氧化层具有基本相同的蚀刻速率。
7.根据权利要求6所述的结构，其中所述阻挡材料由氮化物材料构成。
8.根据权利要求6所述的结构，其中所述阻挡材料由掺杂氮的碳化硅构成。
9.根据权利要求8所述的结构，其中所述绝缘层是体SiCOH。
10.一种结构，包括：
形成在绝缘体材料中的布线层；
包括由氧化材料构成的上表面的阻挡材料；
直接位于所述上表面上的层间电介质材料；以及
延伸到所述布线层、延伸穿过所述阻挡材料、所述氧化材料和所述层间电介质材料的接触，所述接触在所述氧化材料内具有基本上直的轮廓。
11.根据权利要求10所述的结构，其中所述层间电介质材料由体SiCOH构成。
12.根据权利要求10所述的结构，其中所述氧化材料为所述阻挡材料的厚度的约20％至30％。
13.根据权利要求10所述的结构，其中所述层间电介质材料和所述氧化材料具有基本相同的蚀刻速率。
14.根据权利要求13所述的结构，其中所述阻挡材料由氮化物材料构成。
15.根据权利要求14所述的结构，其中所述阻挡材料由掺杂氮的碳化硅构成。
16.根据权利要求14所述的结构，其中所述氧化材料具有约12nm至25nm的厚度。
17.一种方法，包括：
在布线结构之上形成阻挡材料；
氧化所述阻挡材料以形成上氧化层；
在所述氧化层之上形成层间电介质材料；
将过孔蚀刻到所述层间电介质材料、所述氧化层和所述阻挡材料中以暴露所述布线结构，所述过孔具有穿过所述氧化层的基本上直的过孔轮廓；以及
在所述过孔内形成接触，所述接触具有穿过所述氧化层的基本上直的轮廓。
18.根据权利要求17所述的方法，其中所述层间电介质材料和所述氧化层具有基本相同的蚀刻轮廓。
19.根据权利要求18所述的方法，其中在用于形成所述阻挡材料的沉积室中执行氧化。
20.根据权利要求18所述的方法，其中所述氧化使用等离子体工艺执行。
CN201810185273.6A 2017-11-20 2018-03-07 具有基本上直的接触轮廓的半导体结构 Pending CN109817566A (zh)

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