CN109786381A - 存储器元件及其制作方法 - Google Patents

存储器元件及其制作方法 Download PDF

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CN109786381A
CN109786381A CN201810408560.9A CN201810408560A CN109786381A CN 109786381 A CN109786381 A CN 109786381A CN 201810408560 A CN201810408560 A CN 201810408560A CN 109786381 A CN109786381 A CN 109786381A
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layer
tungsten
memory component
plasma
electrode layer
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CN109786381B (zh
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刘志建
张家隆
蔡函原
吴姿锦
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Abstract

本发明公开一种存储器元件及其制作方法，制作存储器元件的方法的步骤包含提供一具有多个电容的基底，其中该电容具有一下电极层、一绝缘层、一上电极层、以及一上电极板，在该上电极层上形成一钨层，对该钨层进行一等离子体氮化处理以形成一氮化钨层，以及在该氮化钨层上形成一金属沉积前介电层。

Description

存储器元件及其制作方法
技术领域
本发明涉及一种存储器元件及其制作方法，尤其是涉及一种存储器元件及其制作方法，其钨层与金属沉积前介电层(pre-metal dielectric,PMD)之间的粘着性获得改善，得以降低该两者之间的电阻。
背景技术
动态随机存取存储器(dynamic random access memory,DRAM)等类装置的半导体基底主要平面上通常会界定有存储单元区域与周边电路区域。这些存储单元区域会含有多个由晶体管单元和存储节点构成的存储单元(cell)，周边电路区域则可含有多种周边电路用来执行对存储单元区域中存储单元的读取与写入等动作。
过去数年间，DRAM领域在元件尺寸的微缩方面进展显著。为了确保大的电容量，这类DRAM所使用的电容会形成在三维结构中，如圆筒形或圆柱形的电容。相较于那些传统埋洞式的电容而言，这类电容可以提供较大的板电极面积，其构造中会需要支撑结构来强化从基底向上垂直延伸的下电极、电容绝缘膜、上电极层、以及其上所覆盖的上电极板(topplate)等单元部件。
一般电容单元的上电极板较佳都是使用硅锗(SiGe)材料来形成的。在形成金属沉积前介电层(pre-metal dielectric,PMD)之前，硅锗类的上电极板上会形成钨层等导电金属来降低存储单元阵列的电阻。然而，该钨层与硅基的金属沉积前介电层之间的粘着性非常不好，容易使电容结构的侧壁裂开。特别是在封装步骤后，其过程中所产生的大量张力会将金属沉积前介电层从钨层上剥离开来。
发明内容
为了让阅者对本发明的面向有基本的了解，以下段落提出了本发明的简要说明。此概要并非是本发明内容详尽的综览，并未意欲要表明本发明的所有关键或必要元件或是要限定本发明的范畴，其诉求仅在于对后续所将探讨的本发明细节描述先以简化的形式提出其中的某些概念。
为了要解决钨层与金属沉积前介电层之间粘着性不良的问题，本发明的做法是在钨层上形成一层氮化钨层以及/或一层氧化钨层。此钨化合物材质的层结构与硅基的介电层之间会具有较好的粘着性质。
本发明的面向之一在于提出一种存储器元件的制作方法，其步骤包含提供一基底，该基底上形成有多个电容，其中该电容包含一下电极层、一绝缘层、一上电极层、以及一上电极板，在该上电极板上形成一钨层，对该钨层进行一等离子体氮化处理以形成一氮化钨层，以及在该氮化钨层上直接形成一介电层。
本发明的另一面向在于提出一种存储器元件的制作方法，其步骤包含提供一基底，该基底上形成有多个电容，其中该电容包含一下电极层、一绝缘层、一上电极层、以及一上电极板，在该上电极板上形成一钨层，对该钨层进行一等离子体氧化处理以形成一氧化钨层，以及在该氧化钨层上直接形成一介电层。
本发明的又一面向在于提出一种存储器元件，其结构包含一基底、一下电极层，位于该基底上、一绝缘层，位于该下电极层上、一上电极层，位于该绝缘层上、一上电极板，位于该上电极层上、一钨层，位于该上电极板上、一氮化钨层，位于该钨层上、以及一介电层，直接位于该氮化钨层上。
本发明的这类目的与其他目的在阅者读过下文中以多种图形与绘图来描述的优选实施例细节说明后必然可变得更为明了显见。
附图说明
本说明书含有附图并于文中构成了本说明书的一部分，使阅者对本发明实施例有进一步的了解。该些图示描绘了本发明一些实施例并连同本文描述一起说明了其原理。在该些图示中：
图1,图2A,图2B,图3是根据本发明实施例一存储器元件在制作流程期间的截面示意图。
需注意本说明书中的所有图示都为图例性质，为了清楚与方便图示说明之故，图示中的各部件在尺寸与比例上可能会被夸大或缩小地呈现，一般而言，图中相同的参考符号会用来标示修改后或不同实施例中对应或类似的元件特征。
主要元件符号说明
100 基底
101 存储单元区域
102 周边区域
103 隔离结构
104 存储节点接触结构
106 接垫
108 间隔壁
110 电容结构
112 电容单元
114 下电极层
116 绝缘层
118 上电极层
120 支撑结构
122 上电极板
124 钨层
126 氮化钨层
128 氧化钨层
130 金属沉积前介电层
P1 等离子体氮化处理
P2 等离子体氧化处理
S/D 源/漏极
WL 字符线
具体实施方式
阅者在参照下述优选实施例的详细说明与随附图示后将能更了解本发明的特征与优点，然而文中所举的实施例实际上可能是以许多不同的形式来体现，其不应被理解成是仅局限于文中所详述者。这些所提供的实施例中会有完善的揭露说明，能传达完整的施作范例给本领域中的技术人士。故此，这些实施例只会用随附的权利要求来界定。相同的元件符号在通篇说明书中都是用来指称相同的元件。
文中所用的术语仅是用来说明，其非意欲要将本发明局限为特定的实施例。除非内文有清楚地指出，不然文中所用的「一」、「一个」与「该」等词也意欲包含多个的形式。阅者将能进一步了解到，说明书中使用「包含」以及/或「含有」等词是要具体说明其所陈述的特征、整体、步骤、运作、要素以及/或元件的存在，其并未排除其他的特征、整体、步骤、运作、要素、元件以及/或其组合的存在或添加。
根据本发明实施例，现在下文中将参照图1,图2A,图2B,图3来描述本发明存储器元件的制作流程，其中图2A表示出了本发明其中一实施例的步骤，图2B则表示出了本发明另一实施例的步骤。为了图示简明之故以及避免模糊本发明的标的，图中的某些部件的尺寸会被放大、缩小或予以省略。
首先请参照图1。提供一半导体基底100，其上界定有存储单元区域101与周边区域102。基底100可为硅基底、覆硅绝缘(silicon-on-isolator,SOI)基底、或是硅锗基底。基底100中形成有氧化硅、氮化硅、或氮氧化硅等材质的隔离结构103，以界定出存储单元区域101中的主动区域。
字符线WL会预先形成在基底100中作为控制存储器元件开关的栅极。字符线WL两侧的主动区域中会掺入P型或N型等掺质以形成源/漏极S/D。该源/漏极S/D上复会形成存储节点接触结构104来进一步连接接垫106与其上所形成的电容。每个源/漏极S/D、存储节点接触结构104、以及接垫106的堆叠结构都会为间隔壁108所间隔并分别对应到其上的一个电容单元。
存储单元区域101上会形成一电容结构110，其具有多个电容单元112分别连接到下方的接垫106。在实施例中，每个电容单元112都含有一下电极层114、一绝缘层116、一上电极层118。下电极层114与上电极层118的材料可为氮化钛(TiN)。绝缘层116可为氧化锆-氧化铝-氧化锆(ZrO2-Al2O3-ZrO2,ZAZ)的交互叠层结构。电容单元112的周围会形成支撑结构120来提供它们结构强度并使的分隔。
电容结构110的上电极层118表面上会形成一导电性的上电极板(top plate)122。上电极板122的材料可为掺有硼(B)或磷(P)的硅、硅锗(SiGe)、或是硅磷(SiP)等材料。上电极板122上还会形成一钨层124来降低存储单元阵列的电阻。该钨层124可采用等离子体增强式化学气相沉积法或是溅镀法来形成，其厚度约为此外，因为晶片的表面会暴露在室温下存有氧气、水分、湿气的大气环境中，钨层124表面可能会长出一层原生的氧化钨薄膜(未示出)。
请参照图2A。在形成钨层124后，进行一等离子体氮化处理P1来在该钨层124表面形成一氮化钨(WN)层。此等离子体氮化处理P1可为氨等离子体处理，其使用铵离子来氮化该钨层124。或者，此等离子体氮化处理P1可为远程等离子体处理，其使用电中性的铵自由基来氮化该钨层124。请注意在此实施例中，等离子体氮化处理P1可以是一即时(in-situ)的等离子体处理制作工艺，其在形成该钨层124的期间在与其同个制作工艺腔体内形成或是在同个蚀刻配方中进行。在其他实施例中，等离子体氮化处理P1则是可以在后续形成金属沉积前介电层(pre-metal dielectric,PMD)130期间即时地在同个制作工艺腔体或同个蚀刻配方中进行。此处理中所形成的氮化钨层126会具有共形的型态，亦即其在表面上具有相同均匀的厚度。
在另一实施例中，请参照图2B，其会对钨层124进行等离子体氧化处理P2而非等离子体氮化处理P1来在该钨层124表面形成一氧化钨层128。此等离子体氧化处理P2可使用一氧化二氮(N2O)、二氧化碳、或一氧化碳等离子来氧化该钨层124。或者，等离子体氧化处理P2可以是一远程等离子体处理，其使用电中性的一氧化二氮、二氧化碳、或一氧化碳的自由基来氧化该钨层124。请注意在此实施例中，等离子体氧化处理P2可以是一即时(in-situ)的等离子体处理制作工艺，其在形成该钨层124期间在同一制作工艺腔体或同个蚀刻配方中进行。在其他实施例中，等离子体氮化处理P2则可以在后续形成金属沉积前介电层130期间即时地在同一制作工艺腔体或同个蚀刻配方中进行。此处理中所形成的氮化钨层126会是共形的型态，亦即在表面上具有相同均匀的厚度。相较于上述的原生氧化钨层，此处理中所形成的氧化钨层128会是较为致密的层结构，其具有良好的均匀度与同质性，故可在后续制作工艺中提供形成于其上的金属沉积前介电层130较佳的粘着性。
请参照图3。在氮化钨层126或氧化钨层128形成后，金属沉积前介电层130会直接毯覆沉积在整个基底100上。金属沉积前介电层130可使用化学气相沉积制作工艺来形成覆盖在含有整个上电极板结构的存储单元区域101以及周边区域102上。金属沉积前介电层130可为单层的介电层或是多层的介电层，其材料可为氧化硅、氮化硅、氮氧化硅、碳化硅、碳氮化硅、或是其上材料的组合。所沉积的金属沉积前介电层130会经由化学机械抛光制作工艺来加以平坦化。接触孔与接触结构(未示出)之后会在后续制作工艺中形成在周边区域102上的金属沉积前介电层130中，以连接其下如字符线等地半导体元件。
在本发明中，由于氮化钨层126或氧化钨层128都是中介于钨层124与金属沉积前介电层130之间，故现有金属材质为主的钨层124与硅基的金属沉积前介电层130之间粘着度不佳的问题可获得适当的解决。氮化钨层126或氧化钨层128是用来代替钨层124来与金属沉积前介电层130建立较佳的键结，进而达到较佳的粘着性。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (18)

1.一种制作存储器元件的方法，包含：
提供基底，该基底上形成有多个电容，其中该电容包含下电极层、绝缘层、上电极层、以及上电极板；
在该上电极板上形成钨层；
对该钨层进行等离子体氮化处理以形成氮化钨层；以及
在该氮化钨层上直接形成介电层。
2.如权利要求1所述的制作存储器元件的方法，其中该等离子体氮化处理是氨等离子体处理。
3.如权利要求1所述的制作存储器元件的方法，其中该氨等离子体处理是远程等离子体处理。
4.如权利要求1所述的制作存储器元件的方法，其中该钨层是使用等离子体增强式化学气相沉积制作工艺形成。
5.如权利要求4所述的制作存储器元件的方法，其中该等离子体氮化处理是在该等离子体增强式化学气相沉积制作工艺中即时进行的。
6.一种制作存储器元件的方法，包含：
提供基底，该基底上形成有多个电容，其中该电容包含下电极层、绝缘层、上电极层、以及上电极板；
在该上电极板上形成钨层；
对该钨层进行等离子体氧化处理以形成氧化钨层；以及
在该氧化钨层上直接形成一介电层。
7.如权利要求6所述的制作存储器元件的方法，其中该等离子体氧化处理至少使用一氧化二氮、二氧化碳、以及一氧化碳。
8.如权利要求6所述的制作存储器元件的方法，其中该氧等离子体处理是远程等离子体处理。
9.如权利要求6所述的制作存储器元件的方法，其中该钨层是使用等离子体增强式化学气相沉积制作工艺形成。
10.如权利要求9所述的制作存储器元件的方法，其中该等离子体氧化处理是在该等离子体增强式化学气相沉积制作工艺中即时进行的。
11.一种存储器元件，包含：
基底；
下电极层，位于该基底上；
绝缘层，位于该下电极层上；
上电极层，位于该绝缘层上；
上电极板，位于该上电极层上；
钨层，位于该上电极板上；
氮化钨层，位于该钨层上；以及
介电层，直接位于该氮化钨层上。
12.如权利要求11所述的存储器元件，其中该氮化钨层是共形层。
13.如权利要求11所述的存储器元件，其中该上电极板的材料是硅锗。
14.如权利要求11所述的存储器元件，更包含原生的氧化钨层位于该钨层与该氮化钨层之间。
15.如权利要求11所述的存储器元件，其中该下电极层与该上电极层的材料是氮化钛。
16.如权利要求11所述的存储器元件，其中该绝缘层是氧化锆-氧化铝-氧化锆交互叠层结构。
17.如权利要求11所述的存储器元件，其中该介电层包含单一介电层或是多层介电层。
18.如权利要求11所述的存储器元件，其中该介电层的材料包含氧化硅、氮化硅、氮氧化硅、碳化硅、碳氮化硅、或是以上材料的组合。
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