CN109643994A - 包括gan hemt和mosfet的混合开关 - Google Patents

包括gan hemt和mosfet的混合开关 Download PDF

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CN109643994A
CN109643994A CN201780045074.9A CN201780045074A CN109643994A CN 109643994 A CN109643994 A CN 109643994A CN 201780045074 A CN201780045074 A CN 201780045074A CN 109643994 A CN109643994 A CN 109643994A
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drive signal
state
switch
gate driving
gate drive
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CN109643994B (zh
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卢俊诚
H.白
H.滕
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Heila GmbH and Co KG
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Abstract

一种混合开关装置包括产生栅极驱动信号的栅极驱动电路，具有第一栅极、第一漏极和第一源极的GaN高电子迁移率晶体管（HEMT）。硅（Si）MOSEFT具有第二栅极、第二漏极和第二源极。GaN HEMT和Si MOSEFT以并联布置连接，使得（i）第一漏极和第二漏极被电连接并且（ii）第一源极和第二源极被电连接。第二栅极被连接到栅极驱动电路输出以接收栅极驱动信号。延迟块具有连接到栅极驱动电路输出的输入，并且延迟块输出被配置为产生用于驱动GaN HEMT的延迟的栅极驱动信号。

Description

包括GAN HEMT和MOSFET的混合开关
相关申请的交叉引用
本申请要求2016年7月21日提交的美国临时申请号no. 62/365,157（‘157申请）的权益，通过引用将‘157申请合并于此，如完全记载在本文中一样。
技术领域
本公开一般地涉及电力电子（power electronics）系统，并且更特别地涉及包括GaN高电子迁移率晶体管（HEMT）和硅（Si）金属氧化物半导体场效应晶体管（MOSFET）的混合开关。
背景技术
出于仅提供上下文的目的在下面记载了该背景技术描述。因此，该背景技术描述的任何方面在其不具有其他资格作为现有技术的程度上，既不明确地也不隐含地被承认为是针对本公开的现有技术。
在电子电力电路中，可以通过以并联的布置电连接多个半导体开关来提供高电流功率能力，从而允许一起对负载电流进行承担。并联的布置是期望的，因为这种并联的布置可以共同具有与单个开关相比较低得多的传导电阻。减少的传导电阻可以减少传导损耗，这可以增加整体系统效率。已知硅开关（例如，MOSFET）供在电力应用中使用；然而，由于相对高的开关损耗，因此不以很高的开关频率操作此类开关。
诸如碳化硅（SiC）和氮化镓（GaN）器件之类的宽带隙（wide-bandgap）（WBG）器件正在变得更流行，这归因于它们比常规的硅（Si）器件更高的开关频率能力、更低的开关损耗以及更高的热能力。然而，WBG器件仍具有其自己的挑战。
第一，其相比于硅器件的电流能力对于一些应用而言仍然不够高。针对此类高电流应用，需要并联多个WBG开关，这增加了系统成本。第二，特别地针对所谓的GaN高电子迁移率晶体管（HEMT）器件，当开关不是“接通（on）”时，其反向传导损耗比例如硅MOSFET器件高得多。该反向传导损耗特性限制了系统效率。
因此，存在克服本领域中一个或多个问题的需要。
上文的讨论仅旨在说明本领域并且不应当被视为对权利要求范围的否定。
发明内容
使用硅开关器件（例如，MOSFET）的当前方法由于相对高的开关损耗而通常不以很高的开关频率被操作，而使用GaN HEMT的当前方法具有相对更大的正向/反向传导损耗。根据本教导的装置在零电压开关（ZVS）接通应用（turn-on application）使宽带隙器件（例如，GaN HEMT）与硅开关（例如，Si MOSFET）并联。通常地，由于例如GaN HEMT的关断损耗是基本上可忽略的，因此装置的开关频率将比针对仅硅开关系统高得多。另外，传导损耗在大部分上是由例如Si MOSFET开关承担的。在替代实施例中，其他Si MOSFET开关可以被并联在一起，以便进一步降低传导损耗，并且将不显著地增加系统成本。根据本教导的实施例提供了经济的解决方案而不牺牲GaN HEMT器件的高频率开关性能以及促进对高效率、高功率密度和低成本电力电子系统的设计。
根据本公开的装置包括具有被配置为在其上产生栅极驱动信号的至少一个栅极驱动输出的栅极驱动电路；宽带隙开关器件，例如，高电子迁移率晶体管（HEMT），其中HEMT具有第一栅极、第一漏极和第一源极。所述装置还包括具有第二栅极、第二漏极和第二源极的半导体开关。HEMT和半导体开关以并联布置被连接，其中（i）第一漏极和第二漏极被电连接，并且（ii）第一源极和第二源极被电连接。第二栅极被连接到栅极驱动电路输出，以接收栅极驱动信号。所述装置还包括具有被连接到栅极驱动电路输出的输入和被配置为产生延迟的栅极驱动信号的输出的延迟块。HEMT的第一栅极被连接到延迟块输出，以接收延迟的栅极驱动信号。
还提出了一种操作的方法。
从阅读以下描述和权利要求书以及从回顾附图，本公开的上述及其他的方面、特征、细节、利用和优势将是清楚的。
附图说明
图1是根据本公开的实施例的具有并联的晶体管的装置的图解示意图和框图。
图2是使用图1的布置的复制的替代实施例的示意图。
图3图示了反映图2的实施例的操作的栅极驱动信号和延迟的栅极驱动信号的简化时序图。
图4-7是示出了操作的不同模式的图2的实施例的示意图。
具体实施方式
本文中将各种实施例描述为各种装置、系统和/或方法。记载了许多具体细节以提供对如在说明书中被描述以及在附图中被图示的实施例的整体结构、功能、制造以及使用的透彻理解。然而，本领域中的技术人员将理解：可以在不具有此类具体细节的情况下实践实施例。在其他实例中，没有详细地描述公知的操作、部件和元件以便不模糊在说明书中描述的实施例。本领域中的普通技术人员将理解：本文中描述和示出的实施例是非限制性示例，并且因此可以理解，本文中公开的具体结构和功能细节可以是代表性的，并且不一定限制实施例的范围、其范围仅由所附权利要求书限定。
遍及说明书对“各种实施例”、“一些实施例”、“一个实施例”或“实施例”或诸如此类的引用意味着结合实施例描述的特定的特征、结构或特性被包括在至少一个实施例中。因此，在遍及说明书的位置中的短语“在各种实施例中”、“在一些实施例中”、“在一个实施例中”或“在实施例中”或诸如此类的出现不一定都指代相同的实施例。而且，特定的特征、结构或特性可以以任何合适的方式被组合在一个或多个实施例中。因此，可以没有限制地将结合一个实施例图示或描述的特定的特征、结构或特性整体或部分地与一个或多个其他实施例的特征、结构或特性组合，只要这种组合不是不合逻辑的或不起作用的。
开关损耗。如上面描述的那样，硅开关（例如，MOSFET）当例如其被切断时通常经历开关损耗。如在下面将更详细地描述的那样，在GaN HEMT仍接通时，Si MOSFET将被切断—由于被插入到相应的栅极驱动信号中的时间延迟。因此，对于Si MOSFET而言不存在开关损耗。
反向传导损耗。上面描述了GaN HEMT器件的所谓的反向传导损耗。通过解释的方式，GaN HEMT器件由于体二极管的不存在将具有与Si MOSFET不同的反向传导模式。特别地，当比反向阈值电压高时，GaN HEMT的二维电子气（2DEG）以如等式（1）中所示的电压降来传导电流。
（1）。
为了防止桥电路中的潜在击穿（shoot through），负总是优选地关断GaNHEMT开关，然而，这增加了死区损耗（dead-band loss）。例如，对于由GaN Systems Inc提供的而言，。当来关断GaN HEMT开关时，这对于Si或SiC MOSFET而言通常是正常的，GaN HEMT的反向电压降将至少是7V（例如，根据等式（1））。为了解决过度的反向传导损耗的此类问题，选项可以包括将减少到零，或者替代地收缩死区（即，缩短GaN HEMT开关是关断（OFF）的时间）。这些选项两者都可以损害系统的适当操作。
为了更完全地利用GaN HEMT开关的优点并且避免其相对大的反向传导损耗，根据本申请的教导，提供了一种使用与Si MOSFET开关并联的GaN HEMT开关的混合开关。如将在下面描述的那样，这种混合开关装置当在零电压开关（ZVS）接通应用中被使用时，克服了GaN HEMT开关中的反向传导损耗，同时也克服了Si MOSFET开关中的开关损耗。
现在参考附图，其中相同的附图标记被用于标识在各种视图中的相同或类似的部件，图1是混合开关装置10的实施例的图解视图。装置10包括适合于在电力电子系统中使用的并联的开关布置。图1的实施例可以被视为单个开关布置，所述单个开关布置可以被复制用于以本领域中已知的多种方式关于（一个或多个）负载和/或电源连接的较大的构造中使用，较大的构造（constructs）诸如在桥的应用中在图2中示出的。
在图示的实施例中，装置10包括具有至少一个栅极驱动电路输出14的栅极驱动电路12。栅极驱动电路12可以包括半导体芯片并且进一步被配置为对多种输入信号（例如，电压和/或电流输入）进行响应，以便除了其他之外在栅极驱动电路输出14处输出栅极驱动信号16（最佳地在图3中示出）。特别地，栅极驱动电路12可以根据预定的控制方法产生栅极驱动信号16。所述技术充满了示例性控制策略并且取决于特定的应用。替代地，可以由如在下面更详细地描述的电子控制单元（ECU）执行产生栅极驱动信号所需要的处理。
如图3中所示，栅极驱动信号16包括至少接通（ON）状态18和关断状态20。在实施例中，接通状态18当由栅极驱动电路12认定时被配置为接通目标开关，而关断状态20当被认定时，相反地被配置为关断目标开关。
在实施例中，栅极驱动电路12可以包括本领域中可商用的常规装置，例如，已知的MOSFET/GaN栅极驱动集成电路（“芯片”）。在图示的实施例中，对于GaN HEMT器件，栅极驱动电路12可以包括可从Texas Instruments，Dallas，Texas，U.S.A商业可获得的型号为LM5113的用于增强模式GaN FET栅极驱动电路的半桥栅极驱动器（例如，如图2中）。在实施例中，在本文中有时也被指定为的栅极驱动信号16可以具有其输出电压，其在针对接通状态18的大约+7V到针对关断状态20的-5V之间变动。
虽然图1示出了可以是特定控制器件的栅极驱动电路12，但是装置10可以附加地包括或者可以具有作为栅极驱动电路12的替代物的电子控制单元（ECU）100，其被配置为实现针对混合开关装置10的操作的期望的控制策略。ECU 100包括处理器102和存储器104。处理器102可以包括处理能力以及输入/输出（I/O）接口，通过所述输入/输出（I/O）接口，处理器102可以接收多个输入信号（提供（一个或多个）输入信号108的输入块106）并且生成多个输出信号（例如，实施例中的（一个或多个）栅极驱动信号）。提供存储器104用于数据以及用于处理器102的指令或代码（例如，软件）的存储。
存储器104可以包括各种形式的非易失性（即，非暂时性）存储器和/或易失性存储器，所述非易失性（即，非暂时性）存储器包括闪存或包括各种形式的可编程只读存储器（例如，PROM、EPROM、EEPROM）的只读存储器（ROM）；所述易失性存储器包括包含静态随机存取存储器（SRAM）、动态随机存取存储器（DRAM）和同步动态随机存取存储器（SDRAM）的随机存取存储器（RAM）。
在实施例中，用于开关器件接通控制的一个方法可以是采用零电压开关（ZVS）策略。如所示的那样，可以按照操作控制逻辑110实现用于关断控制和接通控制（包括ZVS控制）的控制策略，所述操作控制逻辑110包括可以被存储在存储器104中并且被配置为由处理器102执行的处理器指令。替代地，用于对混合开关装置10的操作（即，关断和接通控制）进行控制的操作控制逻辑可以被实现在硬件中。如所示的那样，ECU 100可以产生控制栅极驱动电路12以认定和解除认定栅极驱动信号16（时序图参见图3）的控制信号112。所述技术充满了用于实现零电压开关（ZVS）控制策略的教导。通常地，为了维持用于开关接通的零电压开关，在接通动作之前，电流应当反向流动，这使得开关电压降到零。因此，在开关接通期间，开关仅承担电流改变，而跨其间届时（then-prevailing）的电压始终接近于零，这继而消除了接通损耗，从而到达了ZVS接通。可以通过参考标题为“GATE DRIVE CIRCUIT”的2015年6月19日提交的美国申请no. 14/744,988（‘988申请）来查看其他的信息。通过引用将所述‘988申请合并于此，如完全记载在本文中一样。
通过继续参考图1，混合开关装置10还包括宽带隙开关，所述宽带隙开关诸如是包括第一栅极28、第一漏极30和第一源极32的GaN高电子迁移率晶体管（HEMT）26。在实施例中，GaN HEMT开关26可以包括商用部件，例如，在来自GaN Systems Corp., Ann Arbor,Michigan,USA的贸易名称和/或零件编号GS66516T之下提供的增强模式GaN晶体管。
混合开关装置10还包括诸如硅（Si）金属氧化物半导体场效应晶体管（MOSFET）34之类的一个或多个硅开关，其包括第二栅极36、第二漏极38和第二源极40的。在实施例中，MOSFET 34可以包括商用部件，例如，在来自STMicroelectronics，Coppell，Texas，USA的贸易名称和/或零件编号STY139N65M5之下提供的N-沟道功率MOSFET。
GaN HEMT 26和Si MOSFET 34以并联布置电连接到彼此，其中（i）第一漏极30和第二漏极38被电连接，并且（ii）第一源极32和第二源极40也被电连接。如图1中所示，第二栅极36被电连接到栅极驱动电路输出14，以便接收栅极驱动信号16。
混合开关装置10还进一步包括具有被连接到栅极驱动电路输出14的输入的延迟块22，所述输入被配置为接收栅极驱动信号16。延迟块22还包括被配置为产生被指定为的延迟的栅极驱动信号的输出。GaN HEMT 26的第一栅极28被电连接到延迟块22的输出，以便接收延迟的栅极驱动信号。如提到的那样，延迟块22操作以在两个开关26、34的栅极信号之间插入时间延迟。在实施例中，延迟块22可以包括常规设计的电阻器-电容器（RC）电路。在实施例中，延迟块22可以被配置为插入不大于大约100纳秒（ns）的时间延迟。
图2示出了混合开关装置10可以如何被用作桥电路（参见外部电路42）的部分。应当理解，混合开关装置10可以被用在其他的应用中，诸如例如半桥、H-桥、三相逆变器以及诸如此类。就这一点而言，如所示的那样，图1的装置10中的混合开关布置被复制，其中“上”开关包含与其附图标记包括下标“1”的图1的实施例中相同的部件，而“下”开关包含与其附图标记包括下标“2”的图1的实施例中相同的部件。“上”开关的源极终端，即源极终端321和401在公共节点44处被电连接到“下”开关的漏极终端，即漏极终端302和382。如进一步所示，电子控制单元100被配置为生成控制信号1121和1122，以便分别地控制“上”和“下”混合开关装置的操作。
图3是适用于图2的实施例的栅极驱动信号和延迟的栅极驱动信号的时序图。特别地，栅极驱动信号161、162的时间序列（也被示出为信号和）以及对应的延迟的栅极驱动信号241、242（也被示出为信号和）被示出在公共的时间线上。
现在参考图4-图7，现在将记载根据图3中所示的信号时序的对图2的实施例的操作的描述。具体地，图2的实施例的操作可以被分解为六个单独的时间段或模式。
模式1： 。在时间、之间的时间段期间，所有的开关都关断（即，开关261、341、262、342）。这是因为所有的栅极驱动信号都被解除认定且处于关断状态中。在示例性零电压开关（ZVS）应用中，图2中示出的电流将被视为是正的—这在图4中被示出。因此，电流将流过包括GaN HEMT 261和Si MOSFET 341的“上”开关。然而，由于GaN HEMT 261展现了大致7V降—如在上面关于等式（1）描述的那样—与Si MOSFET 341的体二极管的仅大致1～2V电压降相比较，因此电流将流过Si MOSFET 341的体二极管，如图4中所示。
模式2： 。在时间、之间的时间段期间，上Si MOSFET 341是接通的，而其他的开关维持关断（即，其他的开关261、262、342维持关断）。这是因为（i）尽管栅极驱动信号161 的认定，但是延迟块22已经将栅极驱动信号241 的对应认定进行了时间延迟；并且（ii）栅极驱动信号162、242 两者也都处于关断状态中。ZVS应用意味着，图2中示出的电流是正的—如也在图4中示出的那样。因此，电流将流过上Si MOSFET 341沟道。由于GaN HEMT 261在该示例中展现了大致7V降（参见关于等式（1）的上文）—与跨Si MOSFET 341的沟道的小得多的电压降相比较（即，由于是的小电阻，MOSFET沟道电压降小得多），因此电流将流过Si MOSFET 341沟道。
模式3： 。在时间、之间的时间段期间，上GaN HEMT 261和Si MOSFET341两者是接通的，而下开关维持关断（即，下开关262、342维持关断）。这是因为由延迟块22插入的接通延迟已经过去，并且因此上栅极驱动信号和上延迟的栅极驱动信号161、241 两者都被认定且处于接通状态中，而下栅极驱动信号和下延迟的栅极驱动信号162、242 被解除认定且处于关断状态中。在实施例中，通过并联其他Si MOSFET（未示出），这是相对可负担的，可以使MOSFET沟道电阻比GaN HEMT的沟道电阻小得多。因此，如图5中所示，大多数的电流将仍流过Si MOSFET 341沟道，尽管电流的较小部分将流过GaN HEMT 261。因而，在模式1-3操作中，因此避免了如果单独使用GaNHEMT 261则可能已经发生的通过GaN HEMT 261的反向传导损耗。
模式4：。在时间、之间的时间段期间，上GaN HEMT 261是接通的并且上Si MOSFET 341是关断的，而下开关还维持关断（即，下开关262、342维持关断）。这是因为（i）尽管栅极驱动信号161 的解除认定将“上”Si MOSFET 关断，但是延迟块22已经将控制上GaN HEMT 261的栅极驱动信号241 的对应解除认定时间延迟。而且，栅极驱动信号162、242 两者都被解除认定并且因此处于关断状态中。总之，除了上GaN HEMT 261之外，所有的开关是关断的。为了实现针对下混合开关布置的ZVS，在该时段期间，应当反转电流的极性，在图6中示出。应当理解，当通过GaN HEMT 261仍接通的栅极驱动信号161 的解除认定而将上Si MOSFET 341关断时，由于通过延迟块22插入的时间延迟。结果，因此，Si MOSFET 341是ZVS关断的。不存在针对上Si MOSFET 341的开关关断损耗。
另外，虽然上GaN HEMT 261在处是硬关断的，但是实验结果显示出，GaN HEMT261关断是可忽略的。更具体地，相比于硬接通损耗，上述的硬关断损耗小得多。因此，与本公开的教导相一致的实施例能够以高得多的开关频率运行，因为Si MOSFET的开关损耗是零。
模式5： 。在时间、之间的时间段期间，所有的开关是关断的（即，开关261、341、262、342）。这是因为所有的栅极驱动信号被解除认定且处于关断状态中。再次，类似于模式1，由于下Si MOSFET 342的体二极管展现了比GaN HEMT 262的电压降低得多的电压降，因此电流将替代地通过下MOSFET 342的体二极管，这展现了仅大约1～2V电压降。
模式6： 。在时间、之间的时间段期间，下Si MOSFET 342是接通的，而其他的开关维持关断（即，其他的开关261、262、341维持关断）。这是因为（i）尽管栅极驱动信号162 的认定，但是延迟块22已经将栅极驱动信号242 的对应认定进行了时间延迟；并且（ii）栅极驱动信号161、241 两者也都处于关断状态中。类似于上面的模式2，如图7中所示的那样，电流将流过下Si MOSFET 342沟道。由于GaNHEMT 262在该示例中展现了大致7V降（参见结合等式（1）的上文）—与跨Si MOSFET 342的沟道的小得多的电压降相比较（即，由于是的小电阻，MOSFET沟道电压降小得多），所以电流将流过下Si MOSFET 342沟道。总之，下Si MOSFET是接通的，这使得所有电流通过其沟道。在时间处，下GaN HEMT 162是ZVS 接通的—这在由延迟块插入的时间延迟已经过去之后发生。
因此，总之，可以描述混合开关装置的以下特征。第一，当所有的开关是关断的时，不存在通过GaN HEMT的电流。因此，可以为GaN HEMT避免相对大的反向传导损耗。第二，当GaN HEMT仍接通时，所有的Si MOSFET是关断的。因此，不存在针对Si MOSFET的关断损耗。第三，所有的开关是ZVS接通的。因此，所有的Si MOSFET不具有任何开关损耗，而是最多仅具有传导损耗。第四，所有的GaN HEMT将利用很小的正向/反向传导损耗和零接通损耗而仅承担关断损耗。因此，所有的传导损耗由Si MOSFET承担。所有的关断损耗由GaN HEMT承担。前述的混合开关装置完全利用了Si MOSFET器件以及GaN HEMT器件两者的优势。
应当理解：如本文中描述的电子控制单元可以包括能够执行被存储在关联的存储器中的预编程指令的本领域中已知的常规处理装置、所有执行根据本文中描述的功能性。就本文中描述的方法被体现在软件中的程度，得到的软件可以被存储在关联的存储器中并且还可以构成用于执行此类方法的装置。鉴于前文的使能描述，在软件中这样被完成的某些实施例的实现将需要不超过通过本领域中技术人员的编程技能的常规（routine）应用。这种电子控制单元还可以是具有ROM、RAM两者、非易失性和易失性（可修改的）存储器的组合的类型，使得任何软件可以被存储并且还允许动态产生的数据和/或信号的存储和处理。
虽然已经以一定程度的特殊性在上面描述了仅某些实施例，但是本领域中的技术人员可以在不脱离本公开的范围的情况下对公开的实施例做出许多改变。意图是：被包含在上面描述中或者在附图中被示出的所有事物应当被解释为仅是说明性而不是限制性的。在不脱离如所附的权利要求书中限定的本发明的情况下可以做出细节或结构的改变。
声称通过引用被合并于本文中的全部或部分的任何专利、出版物或其他公开材料仅被合并于此到合并的材料不与本公开中记载的现有定义、声明或其他公开材料相冲突的程度。这样，并且到必要的程度，如在本文中明确记载的本公开取代了通过引用被合并入本文中的任何冲突材料。声称通过引用被合并于本文中但是与本公开中记载的现有定义、声明或其他公开材料相冲突的任何材料或其部分仅将被合并到在合并的材料与现有的公开材料之间不出现冲突的程度。
虽然已经示出和描述了一个或多个特定的实施例，但是本领域中的技术人员将理解，可以在不脱离本教导的精神和范围的情况下做出各种改变和修改。

Claims (12)

1.一种装置，包括：
栅极驱动电路，其具有被配置为在所述栅极驱动输出上产生栅极驱动信号的至少一个栅极驱动输出；
宽带隙（WBG）开关器件，其具有第一栅极、第一漏极和第一源极；
半导体开关，其具有第二栅极、第二漏极和第二源极，所述WBG开关器件和所述半导体开关以并联布置被连接，其中（i）所述第一漏极和所述第二漏极被电连接，并且（ii）所述第一源极和所述第二源极被电连接，所述第二栅极被连接到所述栅极驱动电路输出以接收所述栅极驱动信号；以及
延迟块，其具有被连接到所述栅极驱动电路输出的输入和被配置为产生延迟的栅极驱动信号的输出，所述WBG开关器件的所述第一栅极被连接到所述延迟块输出，以接收所述延迟的栅极驱动信号。
2.根据权利要求1所述的装置，其中所述WBG开关器件包括高电子迁移率晶体管（HEMT）。
3.根据权利要求2所述的装置，其中所述HEMT包括GaN高电子迁移率晶体管（HEMT）器件。
4.根据权利要求1所述的装置，其中所述半导体开关包括硅（Si）MOSFET器件。
5. 根据权利要求4所述的装置，其中所述Si MOSFET包括在所述第二源极和所述第二漏极之间的体二极管。
6.根据权利要求1所述的装置，其中所述延迟块包括电阻器-电容器（RC）电路。
7.根据权利要求1所述的装置，其中所述栅极驱动信号包括接通状态和关断状态，并且其中当所述栅极驱动信号从所述关断状态转变到所述接通状态时，所述延迟块延迟所述延迟的栅极驱动信号从所述关断状态到所述接通状态的转变。
8.根据权利要求7所述的装置，还包括电子控制单元，其被配置为根据零电压开关（ZVS）策略来控制所述栅极驱动电路。
9.根据权利要求8所述的装置，其中所述电子控制单元被配置为控制所述栅极驱动电路，以输出处于所述接通状态或所述关断状态中的所述栅极驱动信号。
10.根据权利要求8所述的装置，其中所述电子控制单元被配置为当将所述栅极驱动信号从所述关断状态转变到所述接通状态时根据所述ZVS策略来控制所述栅极驱动电路。
11.根据权利要求2所述的装置，其中所述HEMT和所述半导体开关形成第一混合开关布置，所述装置还包括复制所述第一混合开关布置的第二混合开关布置，并且其中所述第一混合开关布置的所述第一源极和所述第二源极在公共节点处被连接到所述第二混合开关布置的所述第一漏极和所述第二漏极。
12.根据权利要求11所述的装置，其中在桥电路中使用所述第一布置和所述第二布置。
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