CN109643707A - 电力用半导体装置 - Google Patents
电力用半导体装置 Download PDFInfo
- Publication number
- CN109643707A CN109643707A CN201780052663.XA CN201780052663A CN109643707A CN 109643707 A CN109643707 A CN 109643707A CN 201780052663 A CN201780052663 A CN 201780052663A CN 109643707 A CN109643707 A CN 109643707A
- Authority
- CN
- China
- Prior art keywords
- power semiconductor
- signal terminal
- semiconductor device
- welding disk
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
- 238000003466 welding Methods 0.000 claims abstract description 63
- 239000000463 material Substances 0.000 claims abstract description 40
- 239000011347 resin Substances 0.000 claims abstract description 36
- 229920005989 resin Polymers 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 11
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 description 9
- 238000009413 insulation Methods 0.000 description 6
- 229920000106 Liquid crystal polymer Polymers 0.000 description 4
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 4
- 230000004913 activation Effects 0.000 description 4
- 239000000523 sample Substances 0.000 description 4
- 239000004734 Polyphenylene sulfide Substances 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 229920000069 polyphenylene sulfide Polymers 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910001369 Brass Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 239000010951 brass Substances 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/049—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being perpendicular to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/115—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
- Wire Bonding (AREA)
Abstract
电力用半导体装置具备信号端子以及电力用半导体元件,电力用半导体元件配置于基板之上,信号端子具有主体部和接合部,其一部分由端子台保持,接合部具有前端部和基部,在前端部具有焊盘部,该焊盘部从端子台露出,连接信号布线,基部具有上下方向的厚度比焊盘部薄的薄型部,薄型部的上表面设置于比焊盘部的上表面低的位置,由形成端子台的树脂材料覆盖。
Description
技术领域
本发明涉及电力用半导体装置的信号端子。
背景技术
进行引线键合的电力用半导体装置在搭载于散热部件的基板上搭载半导体元件,在其一部分处以覆盖基板的方式配置端子台。多个信号端子设置于端子台。信号端子是用于将电力用半导体装置的外部与半导体元件进行电连接的端子。这样的信号端子通过内嵌成形或者压入固定于由树脂材料构成的端子台(例如参照专利文献1的图6)。
在此,在用信号布线将半导体元件的图案部与信号端子的焊盘部进行连接的引线键合工序中,为了施加超声波信号,牢固地保持信号端子是不可缺少的。然而,仅凭使信号端子简单地内嵌成形于端子台,或者进行压入,有时由于超声波振动而信号端子共振,无法施加所期望的超声波。因此,在专利文献1中,将使信号端子的焊盘部的一部分露出的圆锥状的开口部设置于端子台,用树脂材料按压露出面的整个周部,从而防止焊盘部的上浮。
现有技术文献
专利文献
专利文献1:日本特开2003-142515号公报
发明内容
然而,在专利文献1所记载的技术中,只是使信号端子的焊盘部和开口部的树脂材料在铅垂方向上密合。因而,无法抑制焊盘部的水平方向的振动。
本发明是为了解决如上所述的课题而完成的,其目的在于提供能够抑制信号端子的焊盘部的振动的电力用半导体装置。
本发明的电力用半导体装置具备:基板;电力用半导体元件,配置于基板上;端子台,配置于基板上;信号端子,由形成端子台的树脂材料保持;以及信号布线,连接于信号端子以及电力用半导体元件,信号端子具有主体部和接合部,接合部具有前端部和基部,在前端部设置焊盘部,该焊盘部从端子台露出,连接信号布线,在基部设置上下方向的厚度比焊盘部薄的薄型部,薄型部的上表面设置于比焊盘部的上表面低的位置,由形成端子台的树脂材料覆盖。
根据本发明的电力用半导体装置,无需改变邻接的端子间的沿面绝缘距离,就能够提高信号端子的焊盘部的保持力。由此,能够提供能够抑制信号端子的焊盘部的振动的电力用半导体装置。
附图说明
图1是将多个本发明中的实施方式1的电力用半导体装置安装于散热部件的示意图。
图2是实施方式1的电力用半导体装置的立体图。
图3A是实施方式1的电力用半导体装置中的信号端子的侧视图。
图3B是实施方式1的电力用半导体装置中的信号端子的俯视图。
图3C是实施方式1的电力用半导体装置中的信号端子的立体图。
图4是沿着图1的IV-IV线的电力用半导体装置的剖视图。
图5A是实施方式2的电力用半导体装置中的信号端子的侧视图。
图5B是实施方式2的电力用半导体装置中的信号端子的俯视图。
图5C是实施方式2的电力用半导体装置中的信号端子的立体图。
图6是实施方式2的电力用半导体装置的剖视图。
图7是示出实施方式2的电力用半导体装置中的信号端子的变形例的俯视图。
图8是实施方式3的电力用半导体装置的立体图。
图9A是实施方式3的电力用半导体装置中的信号端子的侧视图。
图9B是实施方式3的电力用半导体装置中的信号端子的俯视图。
图9C是实施方式3的电力用半导体装置中的信号端子的立体图。
图10是实施方式3的电力用半导体装置的剖视图。
图11A是实施方式4的电力用半导体装置中的信号端子的侧视图。
图11B是实施方式4的电力用半导体装置中的信号端子的俯视图。
图11C是实施方式4的电力用半导体装置中的信号端子的立体图。
图12A是实施方式5的电力用半导体装置中的信号端子的侧视图。
图12B是实施方式5的电力用半导体装置中的信号端子的俯视图。
图12C是实施方式5的电力用半导体装置中的信号端子的立体图。
图13A是实施方式6的电力用半导体装置中的信号端子的侧视图。
图13B是实施方式6的电力用半导体装置中的信号端子的俯视图。
图13C是实施方式6的电力用半导体装置中的信号端子的立体图。
图14A是实施方式7的电力用半导体装置中的信号端子的侧视图。
图14B是实施方式7的电力用半导体装置中的信号端子的俯视图。
图14C是实施方式7的电力用半导体装置中的信号端子的立体图。
图15A是示出在信号端子的引线键合工序中将超声波工具加压到信号布线的状态的图。
图15B是示出在信号端子的引线键合工序中对超声波工具进行激振的状态的图。
图15C是示出在信号端子的引线键合工序中卸载超声波工具的状态的图。
图15D是示出在信号端子的引线键合工序中使超声波工具移动的状态的图。
图15E是示出在信号端子的引线键合工序中使刀具进入到信号布线的状态的图。
图15F是示出在信号端子的引线键合工序中使刀具后退的状态的图。
图15G是示出在信号端子的引线键合工序中切断信号布线的状态的图。
图16A是示出在覆盖信号端子的薄型部的上表面的树脂材料比焊盘部的上表面高的情况下使刀具后退的状态的图。
图16B是示出在覆盖信号端子的薄型部的上表面的树脂材料比焊盘部的上表面高的情况下切断信号布线的状态的图。
图17A是示出在覆盖信号端子的薄型部的上表面的树脂材料比焊盘部的上表面低的情况下使刀具后退的状态的图。
图17B是示出在覆盖信号端子的薄型部的上表面的树脂材料比焊盘部的上表面低的情况下切断信号布线的状态的图。
(附图标记说明)
1:电力用半导体装置;10a~10i:信号端子;101:主体部;102:接合部;12:焊盘部;12a:上表面;14:薄型部;14a:上表面;16:窄幅部;18:贯通孔;20:露出面;22:宽幅部;24:缺口部;30:信号布线;40:电力用半导体元件;50:端子台;60:基板;70:树脂材料;A:前端部;B:基部。
具体实施方式
以下,使用附图,说明本发明的电力用半导体装置的优选的实施方式。
实施方式1.
图1是将多个本发明中的电力用半导体装置1安装于散热部件100的示意图。图2是本发明的实施方式1中的、电力用半导体装置1的立体图。如图2所示,电力用半导体装置1具有基板60、端子台50、电力用半导体元件40、信号端子10a以及信号布线30。在信号布线30的引线键合工序中,如图2那样使焊盘部12朝上露出而接合信号布线30。因此,在此,将信号端子10a侧作为朝上而进行说明。
电力用半导体元件40由IGBT(绝缘栅极型双极晶体管)与二极管的组合构成。电力用半导体元件40使用管芯键合材料固定于基板60的布线图案上。电力用半导体元件40的厚度在IGBT为Si(硅)的情况下,根据所需的耐电压而为60~200μm左右。端子台50利用粘接剂固定于基板60上。端子台50由以具有耐热性的树脂为主要成分的树脂材料70形成,以能够承受后工序的焊接。
图3A~图3C分别是示出电力用半导体装置1的信号端子10a的侧视图、俯视图以及立体图。图4是沿着图1的IV-IV线的电力用半导体装置1的剖视图。如图3A所示,信号端子10a具有柱状的主体部101和板状的接合部102。信号端子10a在端子台50形成时内嵌成形。信号端子10a的主体部101的一部分以及接合部102的一部分被形成端子台50的树脂材料70覆盖,该信号端子10a保持于端子台50。接合部102包括由树脂材料70覆盖的基部B、以及具有焊盘部12的前端部A。焊盘部12的上表面12a从端子台50露出,接合信号布线30。关于信号端子10a,考虑耐振动性以及后工序中的热的影响,由铜或者黄铜形成。另外,关于信号端子10a,以防止氧化为目的,被实施Sn镀敷、Ni镀敷等表面处理。
信号布线30连接电力用半导体元件40的5个种类的低压系的端子、和信号端子10a。5个种类的低压系的端子为电力用半导体元件40的IGBT元件的、栅极端子以及发射极端子、内置于电力用半导体元件40的感温二极管的、阳极端子以及阴极端子、以及内置于电力用半导体元件40的电流传感器端子。信号布线30通过引线键合接合于形成于电力用半导体元件40的表面的图案部、以及信号端子10a的焊盘部12。
在引线键合中,针对电力用半导体元件40的图案部、和信号端子10a的焊盘部12,按压信号布线30,施加向图3B所示的Y方向的超声波振动。然后,在图案部以及焊盘部12与信号布线30之间使新生面产生并凝结,从而进行接合。
此时,当信号端子10a向端子台50的保持不充分时,通过超声波振动,焊盘部12与信号布线30在Y方向上共振,不产生新生面,而成为接合不良。因而需要保持信号端子10a,以避免焊盘部12振动。
如图3B所示,在实施方式1的信号端子10a的接合部102的前端部A设置有缩窄图1以及图2所示的X方向的宽度的窄幅部16。而且,在窄幅部16处的、缩窄宽度的部位填充形成端子台50的树脂材料70。由此,抑制焊盘部12的、Y方向的振动。进而,在信号端子10a的接合部102的基部B设置有使上下方向的厚度比焊盘部12薄的薄型部14。然后,由形成端子台50的树脂材料70将薄型部14的上表面14a以比焊盘部12的上表面12a低的方式进行覆盖,从而提高焊盘部12的、Y方向的振动的抑制力。
在此,说明使覆盖薄型部14的上表面14a的树脂材料70的上表面比焊盘部12的上表面12a低的理由。
使用具有刀具201的超声波工具200来进行信号布线30的引线键合。图15A至图15G依次示出了进行信号布线30的引线键合的一连串的工序。图15A至图15G所示的各工序的内容如下。
(图15A)使用超声波工具200,一边对信号布线30进行加压,一边使其与信号端子10a的焊盘部12的上表面12a接触。
(图15B)施加超声波工具200所产生的超声波振动,将焊盘部12的上表面12a与信号布线30进行接合。
(图15C)卸载由超声波工具200进行的加压。
(图15D)使超声波工具200移动到信号端子10a侧。
(图15E)使刀具201触碰到信号布线30。刀具201的刀刃以信号布线30的直径的一半至70%左右为目标而进入。
(图15F)使刀具201退回。刀具201进入的部分的信号布线30发生变形,在信号端子10a侧的下部产生微小的毛刺状的突起。
(图15G)使超声波工具200向上方移动。然后,上拉信号布线30而切断。
图16A和图16B示出了覆盖薄型部14的上表面14a的树脂材料70的上表面比焊盘部12的上表面12a高的情况下的、图15F的工序和图15G的工序。另一方面,图17A和图17B示出了覆盖薄型部14的上表面14a的树脂材料70的上表面比焊盘部12的上表面12a低的情况下的、图15F的工序和图15G的工序。
在如图16A以及图16B那样,树脂材料70的上表面比焊盘部12的上表面12a高的情况下,有时信号布线30所产生的突起与树脂材料70的角部接触。于是,有时树脂材料70被切除而飞散。当被切除的树脂材料70飞散时,以后的引线键合工序中的接合有可能会被阻碍。另外,在薄型部14,还有可能无法保持所需的绝缘距离。
另一方面,如果如图17A以及图17B那样使树脂材料70的上表面比焊盘部12的上表面12a低,则能够防止信号布线30所产生的突起与树脂材料70接触。由此,能够防止被切除的树脂材料70飞散。因而,以后的引线键合工序中的接合不会被阻碍。另外,在薄型部14,不会无法保持所需的绝缘距离。以上是使覆盖薄型部14的上表面14a的树脂材料70的上表面比焊盘部12的上表面12a低的理由。
此外,最好是对从焊盘部12的上表面12a至薄型部14的上表面14a的角部实施C面加工,使得使端子台50成形的模具的端部比焊盘部12的上表面12a更靠近薄型部14的上表面14a。由此,能够使覆盖薄型部14的树脂材料70的上表面可靠地比焊盘部12的上表面12a低。
窄幅部16的宽度形成为比焊盘部12的宽度窄。窄幅部16的宽度最好为焊盘部12的宽度的一半以下。薄型部14的厚度成为焊盘部12的85%以下,由树脂材料70覆盖上表面14a。薄型部14的厚度更好为焊盘部12的50~70%。这样,根据实施方式1中的电力用半导体装置1,无需改变邻接的信号端子10a间的沿面绝缘距离,就能够抑制信号端子10a的Y方向的振动。此外,在实施方式1中,在信号端子10a的接合部102设置有窄幅部16和薄型部14这两方,但也可以仅为薄型部14。
在此,引线键合的稳定性对形成端子台50的树脂材料70与信号端子10a的密合力做出贡献。因而,作为树脂材料70的种类以及信号端子10a的材质,考虑使用电力用半导体装置的环境的最高温度、以及引线键合后的加热工艺,必须选择具备足够的耐热性的材质。
例如,作为树脂材料70,可举出PPS(聚苯硫醚)、LCP(液晶聚合物)等。考虑耐热性,LCP是有利的,但LCP与PPS相比,有时无法得到足够的与信号端子10a的密合度。在实施方式1的电力用半导体装置1中,信号端子10a设置有薄型部14,所以能够提高树脂材料70与信号端子10a的密合度。
另外,也可以设置薄型部14,并且在引线键合的设备侧设置按压爪,用按压爪按压引线键合部的附近。由此,能够得到更加稳定的引线键合状态。
实施方式2.
图5A~图5C分别是示出实施方式2的信号端子10b的侧视图、俯视图以及立体图。图6是使用了信号端子10b的电力用半导体装置1的剖视图。实施方式2的电力用半导体装置1除了信号端子10b的形状不同之外,与实施方式1相同。
如图5A所示,实施方式2中的信号端子10b具有柱状的主体部101和板状的接合部102。而且,在接合部102的前端部A,如图5B所示设置有窄幅部16,在基部B设置有薄型部14。
在实施方式2的信号端子10b的薄型部14设置有在Z方向上贯通的贯通孔18。该贯通孔18的内部由形成端子台50的树脂材料70填充,从而信号端子10b的基部B的XY平面内的移动被阻止。因而,信号端子10b的焊盘部12向XY平面内的所有的方向的振动被抑制。
在此,关于将电力用半导体元件40上的各接合部与各信号端子10的焊盘部12进行连接的各信号布线30的角度,考虑制造装置以及产品质量的稳定性,优选如图2所示相同。然而,在要求小型化的电力用半导体装置1中,当使信号布线30的角度成为相同时,在小型化方面产生尺寸上的制约,所以有时使各信号布线30的角度不同。在各信号布线30的角度不同的情况下,基于引线键合的激振方向针对每个信号布线30而不同。因而,对每个焊盘部12施加不同的方向的振动。这样,根据实施方式2的信号端子10b,即使在各信号布线30的角度不同的情况下,也能够抑制XY平面内的、焊盘部12的所有的方向的振动。因而,能够降低引线键合的接合不良。
此外,在实施方式2中,使贯通孔18的形状形成为圆形,但并不限于此。例如,贯通孔18的形状也可以形成为椭圆形状、长孔形状、三角形、四边形等多边形。在使贯通孔18的形状形成为椭圆形状或者长孔形状的情况下,当如图7所示形成为作为引线键合的激振方向的Y方向和贯通孔18的长轴方向具有任意的角度θ时,能够得到进一步的振动抑制效果。
实施方式3.
图8是实施方式3的电力用半导体装置1的示意图。图9A~图9C分别是图8的信号端子10c的侧视图、俯视图以及立体图。图10是实施方式3的电力用半导体装置1的剖视图。实施方式3的电力用半导体装置1除了信号端子10c的形状不同之外,与实施方式1相同。
如图9A所示,信号端子10c具有柱状的主体部101和板状的接合部102。而且,在接合部102,如图9B所示,设置有窄幅部16、薄型部14以及贯通孔18。
在电力用半导体装置1的制造工序中,使用检查用的探头来进行电力用半导体元件40的各布线的导通检查。然而,在进行导通检查时,使探头从Z方向或者Y方向与信号端子10a以及信号端子10b的主体部101接触,所以在如实施方式1以及2那样的电力用半导体装置1的情况下,有可能会使主体部101弯曲。
因而,在实施方式3的电力用半导体装置1中,在信号端子10c的基部B设置从端子台50露出的露出面20,能够使探头与露出面20接触而进行检查。由此,无需使探头与信号端子10c的主体部101接触,就能够进行检查。另外,探头向露出面20的接近方向和探头向电力用半导体元件40的图案面40a的接近方向都为Z方向,所以能够简化检查设备。因而,能够实现检查工序的高效化。
实施方式4.
图11A~图11C分别是示出实施方式4中的信号端子10d的侧视图、俯视图以及立体图。如图11A以及图11B所示,在信号端子10d的接合部102设置有窄幅部16和薄型部14。另外,如图11B所示,在信号端子10d的薄型部14设置有宽幅部22,该宽幅部22使X方向的宽度比焊盘部12的宽度宽。
宽幅部22设置于薄型部14,所以由形成端子台50的树脂材料70覆盖其周围。作为电力用半导体装置1的外观与图2所示的、使用了信号端子10a的电力用半导体装置1相同。因而,邻接的信号端子10d间的沿面绝缘距离不改变。由此,无需改变邻接的信号端子10d间的沿面绝缘距离,就能够进一步抑制信号端子10d的焊盘部12的Y方向的振动。此外,宽幅部22的宽度优选形成为焊盘部12的宽度的1.1倍以上。
实施方式5.
图12A~图12C分别是示出实施方式5中的信号端子10e的侧视图、俯视图以及立体图。在实施方式5中的信号端子10e的接合部102设置有窄幅部16、薄型部14以及贯通孔18。而且,如图12B所示,在信号端子10e的薄型部14设置有宽幅部22,该宽幅部22使X方向的宽度比焊盘部12的宽度宽。
实施方式6.
图13A~图13C分别是示出实施方式6中的信号端子10f的侧视图、俯视图以及立体图。在信号端子10f的接合部102设置有窄幅部16、薄型部14、在Z方向上贯通的贯通孔18、以及一部分从端子台50露出的露出面20。而且,如图12B所示,在信号端子10f的薄型部14设置有使X方向的宽度比焊盘部12的宽度宽的宽幅部22。
实施方式7.
图14A~图14C分别是示出实施方式7中的信号端子10g~10i的立体图。信号端子10g~10i替换实施方式2中的信号端子10b的贯通孔18而在薄型部14的两侧面分别设置有半圆、三角形、四边形的缺口部24。信号端子10g~10i通过设置缺口部24,使薄型部14的宽度部分地变窄。
此外,在实施方式7中,替换实施方式2中的信号端子10b的贯通孔18而设置有缺口部24,但也可以除了设置贯通孔18之外还设置缺口部24。进而,在实施方式7中,在水平方向(Y方向)的宽度与焊盘部12相等的薄型部14设置有缺口部24,但也可以在图11B所示的信号端子10d的宽幅部22设置缺口部24。
Claims (6)
1.一种电力用半导体装置,具备信号端子以及电力用半导体元件,其中,
所述电力用半导体元件配置于基板之上,
所述信号端子具有主体部和接合部,其一部分由端子台保持,
所述接合部具有前端部和基部,
所述前端部具有焊盘部,该焊盘部从所述端子台露出而连接信号布线,
所述基部具有厚度比所述焊盘部薄的薄型部,
所述薄型部的上表面设置于比所述焊盘部的上表面低的位置,由形成所述端子台的树脂材料覆盖至比所述焊盘部的上表面低的位置。
2.根据权利要求1所述的电力用半导体装置,其中,
在所述前端部具备水平方向的宽度比所述焊盘部窄的窄幅部。
3.根据权利要求1或者2所述的电力用半导体装置,其中,
在所述薄型部设置有在上下方向上贯通的贯通孔,
所述贯通孔由形成所述端子台的树脂材料填充。
4.根据权利要求1至3中的任意一项所述的电力用半导体装置,其中,
在所述薄型部具备水平方向的宽度比所述焊盘部宽的宽幅部。
5.根据权利要求1至4中的任意一项所述的电力用半导体装置,其中,
在所述薄型部具有缺口部,
所述缺口部由形成所述端子台的树脂材料填充。
6.根据权利要求1至5中的任意一项所述的电力用半导体装置,其中,
在所述基部具备使所述信号端子的一部分露出的露出面。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016174352 | 2016-09-07 | ||
JP2016-174352 | 2016-09-07 | ||
PCT/JP2017/030762 WO2018047659A1 (ja) | 2016-09-07 | 2017-08-28 | 電力用半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN109643707A true CN109643707A (zh) | 2019-04-16 |
CN109643707B CN109643707B (zh) | 2022-07-05 |
Family
ID=61562303
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201780052663.XA Active CN109643707B (zh) | 2016-09-07 | 2017-08-28 | 电力用半导体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10727189B2 (zh) |
JP (1) | JP6584679B2 (zh) |
CN (1) | CN109643707B (zh) |
DE (1) | DE112017004495T5 (zh) |
WO (1) | WO2018047659A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN117712049A (zh) * | 2020-10-14 | 2024-03-15 | 罗姆股份有限公司 | 半导体模块 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7005469B2 (ja) | 2018-11-07 | 2022-02-04 | 三菱電機株式会社 | 半導体装置 |
CN109585397A (zh) * | 2018-11-16 | 2019-04-05 | 北京遥感设备研究所 | 一种平面功率合成结构电源馈电装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6060772A (en) * | 1997-06-30 | 2000-05-09 | Kabushiki Kaisha Toshiba | Power semiconductor module with a plurality of semiconductor chips |
JP2000332179A (ja) * | 1999-05-18 | 2000-11-30 | Fujitsu Ten Ltd | 端子の固定構造 |
JP2000349219A (ja) * | 1999-06-03 | 2000-12-15 | Mitsubishi Electric Corp | 引き出し端子、電力用半導体装置用ケース及び電力用半導体装置 |
JP2006310377A (ja) * | 2005-04-26 | 2006-11-09 | Nissan Motor Co Ltd | 半導体装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2578530Y2 (ja) * | 1992-06-08 | 1998-08-13 | サンケン電気株式会社 | 端子接続構造 |
JPH1084009A (ja) | 1996-09-09 | 1998-03-31 | Toshiba Corp | 半導体装置 |
JP2003142515A (ja) | 2001-11-02 | 2003-05-16 | Toyota Industries Corp | 回路装置 |
JP3715590B2 (ja) * | 2002-06-17 | 2005-11-09 | 三菱電機株式会社 | インサート成形ケース及び半導体装置 |
JP2005243697A (ja) * | 2004-02-24 | 2005-09-08 | Nissan Motor Co Ltd | 半導体装置 |
JP2006108306A (ja) | 2004-10-04 | 2006-04-20 | Yamaha Corp | リードフレームおよびそれを用いた半導体パッケージ |
JP6451257B2 (ja) * | 2014-11-21 | 2019-01-16 | 富士電機株式会社 | 半導体装置 |
JP6413709B2 (ja) * | 2014-12-02 | 2018-10-31 | 富士電機株式会社 | 半導体装置およびその製造方法 |
-
2017
- 2017-08-28 WO PCT/JP2017/030762 patent/WO2018047659A1/ja active Application Filing
- 2017-08-28 DE DE112017004495.2T patent/DE112017004495T5/de active Pending
- 2017-08-28 US US16/324,161 patent/US10727189B2/en active Active
- 2017-08-28 CN CN201780052663.XA patent/CN109643707B/zh active Active
- 2017-08-28 JP JP2018538360A patent/JP6584679B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6060772A (en) * | 1997-06-30 | 2000-05-09 | Kabushiki Kaisha Toshiba | Power semiconductor module with a plurality of semiconductor chips |
JP2000332179A (ja) * | 1999-05-18 | 2000-11-30 | Fujitsu Ten Ltd | 端子の固定構造 |
JP2000349219A (ja) * | 1999-06-03 | 2000-12-15 | Mitsubishi Electric Corp | 引き出し端子、電力用半導体装置用ケース及び電力用半導体装置 |
JP2006310377A (ja) * | 2005-04-26 | 2006-11-09 | Nissan Motor Co Ltd | 半導体装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN117712049A (zh) * | 2020-10-14 | 2024-03-15 | 罗姆股份有限公司 | 半导体模块 |
CN117712049B (zh) * | 2020-10-14 | 2024-06-07 | 罗姆股份有限公司 | 半导体模块 |
Also Published As
Publication number | Publication date |
---|---|
US20190206811A1 (en) | 2019-07-04 |
JPWO2018047659A1 (ja) | 2018-11-22 |
US10727189B2 (en) | 2020-07-28 |
CN109643707B (zh) | 2022-07-05 |
JP6584679B2 (ja) | 2019-10-02 |
WO2018047659A1 (ja) | 2018-03-15 |
DE112017004495T5 (de) | 2019-07-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5011388B2 (ja) | コンタクタ、プローブカード及びコンタクタの実装方法。 | |
TWI441297B (zh) | 具有阻抗控制引線接合及參考引線接合之微電子總成 | |
TWI517326B (zh) | 具有引線之基板 | |
JP4691112B2 (ja) | 接点装置およびその製造方法 | |
JP2000502812A (ja) | ウエハ・レベルのテストおよびバーンインのための集積化コンプライアント・プローブ | |
JP2006518944A (ja) | バンプを有するボールグリッドアレー | |
CN109643707A (zh) | 电力用半导体装置 | |
US20130221504A1 (en) | Semiconductor module and method of manufacturing a semiconductor module | |
CN110383464A (zh) | 半导体装置 | |
CN107873080A (zh) | 半导体装置评价用工具、半导体装置评价装置及半导体装置评价方法 | |
US8922234B2 (en) | Probe card and method for manufacturing probe card | |
JP4384724B2 (ja) | プローブカードの製造方法 | |
JP2015010980A (ja) | プローブ装置 | |
EP3364194B1 (en) | Kelvin test probe, kelvin test probe module, and manufacturing method therefor | |
US9476913B2 (en) | Probe card | |
JP2017517863A (ja) | 高周波デバイスのテスト用両方向導電性ソケット、高周波デバイスのテスト用両方向導電性モジュール及びその製造方法 | |
KR101745884B1 (ko) | 초정밀 레이저를 활용한 소켓 및 그 제조방법 | |
JP6208486B2 (ja) | プローブカード及びその製造方法 | |
JP2005311043A (ja) | 半導体装置とこの検査方法および検査装置 | |
KR20140011991A (ko) | 수직으로 위치된 기판들을 전기적으로 접속시키는 방법 | |
JP2017181477A (ja) | コンタクトプローブ装置 | |
JP2007285980A (ja) | プローブ装置 | |
KR101720300B1 (ko) | 접촉성이 개선된 범프를 포함하는 테스트 소켓용 mems 필름 | |
KR20230019926A (ko) | 반도체 장치 및 반도체 장치의 제조 방법 | |
JP2005164480A (ja) | プローブカード及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |