CN109585288B - 具有温度稳定特性的scr部件及其制作方法 - Google Patents

具有温度稳定特性的scr部件及其制作方法 Download PDF

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CN109585288B
CN109585288B CN201811209506.8A CN201811209506A CN109585288B CN 109585288 B CN109585288 B CN 109585288B CN 201811209506 A CN201811209506 A CN 201811209506A CN 109585288 B CN109585288 B CN 109585288B
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S·梅纳德
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STMicroelectronics International NV
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Abstract

本公开涉及一种具有温度稳定特性的SCR部件。垂直结构的SCR型部件具有形成在第一导电类型的硅区域上、自身形成在第二导电类型的硅层中的主上部电极，其中所述区域中断在其中硅层的材料与上部电极接触的第一部位中，以及在采用延伸在硅层和电极之间的电阻性多孔硅填充的第二部位中。

Description

具有温度稳定特性的SCR部件及其制作方法
相关申请的交叉引用
本申请是申请日为2014年9月12日、国家申请号为 201410464352.2、发明名称为“具有温度稳定特性的SCR部件”的中国发明专利申请的分案申请。
本申请要求享有2013年9月26日提交的法国专利申请号 13/59295的优先权权益，该申请在此通过引用在法律许可的最大范围并入本文。
技术领域
本公开涉及一种垂直结构的SCR型部件及其制造方法。
背景技术
可控硅(SCR)型部件是具有包括交替导电类型的至少四个半导体层和/或区域的堆叠的结构的部件。这些部件例如是晶闸管、三端双向可控硅开关元件、单向或双向肖特基二极管。
图1A和图1B分别是晶闸管的剖视图。图1B是沿着图1A的破折线B-B获取的剖视图。这些附图示意性示出了晶闸管，该晶闸管包括具有分别为PNPN的、交替导电类型的四个半导体层和/或区域 3、5、7和9的垂直堆叠。
在P型掺杂层7中形成重掺杂N型区域9(N+)。阴极金属化结构11覆盖区域9。栅极金属化结构13覆盖了层7的中心部分14。阳极金属化层15覆盖了层3的下表面。金属化结构11、13和15分别形成了阴极电极K、栅极电极G和阳极电极A。
区域9中断在区域17中，其中阴极金属化结构11与层7接触。区域17当前称作发射极短路或发射极短路开孔。已知这些发射极短路17改进了晶闸管的dV/dt行为，因此增大了由电压峰值给晶闸管带来的不合时宜导通的风险。
在图2中，两个曲线20和22分别示出了参照图1A和图1B所述类型的晶闸管中导通电流IGT与保持电流IH的温度相关性T。电流的数值示出为相对于在25℃下它们数值的归一化数值。
曲线20和22示出了电流IH和IGT的数值随着温度T增大而减小。特别地，在－40℃下IGT的数值两倍大于在25℃下的数值，并且在 140℃下IGT的数值近似两倍小于在25℃下的数值。
除了IH和IGT之外，晶闸管的导通时dI/dt特性以及dV/dt导通特性也取决于工作温度。
需要具有尽可能在部件的整个工作温度范围之上尽可能保持恒定特性的SCR型部件。
发明内容
因此，一个实施例提供了一种垂直结构的SCR型部件，其具有在第一导电类型的硅区域上形成的、其自身在第二导电类型的硅层中形成的主上部电极，其中所述区域在如下部位(area)中中断：在其中所述层的材料与所述电极接触的第一部位中，以及在由延伸在所述层和所述电极之间的电阻性多孔硅制成的第二部位中。
根据一个实施例，第二多孔硅部位的厚度大于区域的厚度。
根据一个实施例，多孔硅的在25℃下的电阻率在从103至 104Ω.cm的范围内。
根据一个实施例，第一部位和第二部位规则地分布在区域的表面之上。
根据一个实施例，第一部位的数目等于第二部位的数目。
一个实施例提供了一种在具有阱的SCR型部件中制造多孔硅部位的方法，包括以下相继步骤：提供半导体结构，包括在第二导电类型的硅层中形成的第一导电类型的硅区域，所述区域在部位中被中断，该结构被第二导电类型的外围硅壁横向地定界；通过使得所述区域和外围壁的上表面暴露，在结构的上表面上沉积掩模层；将组件浸入电解液浴剂中，第一浴剂与结构的上表面接触，第二浴剂与结构的下表面接触，正电极和负电极分别浸入第二浴剂和第一浴剂中；以及在正电极和负电极之间施加电压以具有在外围壁中流动的电流，电流的一部分在所述层和部位中流动，以在所述部位中形成多孔硅。
根据一个实施例，电解浴剂由包括水、氢氟酸、乙醇或乙酸的混合物制成。
以下结合附图在对具体实施例的以下非限定性描述中详细讨论前述和其他特征以及优点。
附图说明
图1A和图1B如之前所述分别是晶闸管示例的顶视图和剖视图，
图2如前所述地示出了晶闸管中电流IGT和IH的温度相关性，
图3A和图3B分别是晶闸管的一个实施例的顶视图和剖视图，
图4示出了不同晶闸管中电流IGT的根据温度的变化，
图5A和图5B是示出了制造多孔硅部位的方法的剖视图。
为了简明，在各个附图中采用相同附图标记标识相同元件，并且此外照常在对电子部件的描述中，各个附图并未按照比例绘制。
具体实施方式
图3A和图3B分别是晶闸管的一个实施例的顶视图和简化剖视图。图3B是沿着图3A的破折线B-B获取的剖视图。在图3A和图 3B中，采用与图1A和图1B中相同附图标记标识相同元件。
在图1A和图1B的晶闸管中，由P型掺杂硅的层7的材料形成发射极短路17。然而，在图3A和图3B所示晶闸管中，初始由P型掺杂硅制成的一些发射极短路17替换为由轻导电多孔硅形成的发射极短路，记做30。发射极短路30的多孔硅从阴极金属化结构11一直延伸至层7，优选地穿过区域9的整个厚度，并且可以部分地延伸在区域7中。特别地，发射极短路30的多孔硅是电阻性的，以使得电流在阴极金属化结构11和层7之间流过。作为示例，发射极短路 30的多孔硅在25℃下的电阻率被选择为在从103至104Ω.cm的范围内。
在所述实施例中，具有相同数目的硅发射极短路17以及多孔硅发射极短路30。发射极短路17和30可以规则地设置在区域9的表面之上。例如，在从区域9的中心的每个给定距离处具有相同数目的硅发射极短路17和多孔硅发射极短路30。
作为示例，在实现诸如待由硅制成的晶闸管之类的集成功率部件的技术工艺中，不同层和/或区域的厚度将为：
－从5至20μm，例如10μm，对于区域9，
－从10至30μm，例如20μm，对于层3和7，以及
－从50至100μm，例如70μm，对于层5。
掺杂浓度将例如是：
－在从1014至1016原子/cm3的范围内，对于轻掺杂N型层5(N －)，
－处于1020原子/cm3的量级，对于重掺杂N型区域9(N+)，以及
－在从5×1017至5×1018原子/cm3的范围内，对于P型掺杂区域3和7。
图4示出了在不同晶闸管中电流IGT的温度相关性。
曲线40示出了对于参照附图1A和图1B描述类型的晶闸管电流 IGT根据温度的变化。在包括硅发射极短路17的这种晶闸管中，如已经参照图2所述，电流IGT随着温度增大而急剧减小。在所考虑的示例中，与在140℃下仅具有1mA的数值相比，电流IGT在0℃下具有4.4mA的数值。
曲线42示出了在与对应于曲线40的晶闸管具有相同尺寸和掺杂水平、但是包括多孔硅发射极短路30的晶闸管中电流IGT的温度相关性。电流IGT在0℃下为2.3mA，以及在140℃下为1mA。
曲线44示出了与对应于曲线的42晶闸管类似、但是已经减小了区域9的厚度的晶闸管中电流IGT的温度相关性。电流IGT在0℃下为3.3mA，以及在140℃下为2mA。
这些曲线示出：与发射极短路17相关联的多孔硅发射极短路30 在晶闸管工作温度范围期间提供了电流IGT的更稳定数值。例如，在曲线40中，电流IGT以在0℃与140℃之间4.3的比例减小，而对于曲线42和44，该比例分别是2.3和1.6。
晶闸管的电流IGT反比于栅极金属化结构13和阴极金属化结构 11之间的电阻RGK的数值。在发射极短路17的情形下，电阻RGK的数值主要取决于层7的掺杂硅的电阻率。因为硅的电阻率显著依赖于温度并且随着温度增大而增大，电阻RGK随着温度而增大，并且可以理解为电流IGT的数值随着温度而减小。
在图3A和图3B的晶闸管中，电阻RGK不仅取决于P型掺杂硅的电阻率，而且还取决于发射极短路30的电阻性多孔硅的电阻率。至少在可以介于-40至150℃之间的、晶闸管的工作温度范围内，与单晶硅的电阻率相反，多孔硅的电阻率随着温度增大而减小。当温度变化时这两种材料的电阻率以相反方式变化，电阻RGK和电流IGT较少具有温度相关性。
参照图3B，考虑了穿过多孔硅发射极短路30的、在附图右手侧的、从栅极金属化结构13至阴极金属化结构11的电流路径I1，以及在附图左手侧的从栅极金属化结构13至阴极金属化结构11的电流路径I2。总的栅极电流IGT共用在路径I1和I2之间，并且变得较少依赖于温度。
此外，尽管与掺杂硅发射极短路17相关联的多孔硅发射极短路 30改进了电流IGT的温度稳定性，但是多孔硅发射极短路30也改进了例如晶闸管的SCR型部件的dV/dt导通和切换dI/dt的保持电流IH的温度稳定性。
图5A和图5B是示出了在具有发射极短路的诸如晶闸管之类的 SCR部件中制造多晶硅部位的方法的实施例的剖视图。晶闸管是具有由P型掺杂外围壁50横向定界的阱的类型。
图5A示出了包括分别为PNPN的、具有交替导电类型的四个半导体区域和/或层3、5、7和9的堆叠的晶闸管结构，诸如参照附图 1A、图1B、图3A和图3B所述。
重掺杂N型区域9(N+)在中心部分14以及部位17和17’中中断。在部位17和17’中，P型掺杂层7的材料与结构的上表面接触。
电绝缘掩模层52覆盖了结构的整个上表面，除了外围壁50和部位17’之外。作为示例，层52可以由Si3N4制成。
电解浴剂54和56分别与晶闸管的上表面以及下表面接触。正电极和负电极分别浸入浴剂56和浴剂54中。作为示例，浴剂54和 56可以由包括水、氢氟酸、乙醇或乙酸的混合物制成。
当在正电极和负电极之间施加电压时，电流58从正电极穿过浴剂56、横向区域50以及浴剂54而流至负电极。
因为部位17’并未被掩模层52覆盖，因此电流58的一部分60 流过层7和部位17’。
图5B示出了处理之后获得的晶闸管。多孔硅绝缘区域62已经在电流58流动期间形成在外围壁50的上部部分中。区域62在壁50 的整个上部分中延伸，并且具有大于层7的厚度的厚度。
在电流58的一部分60在部位17’中的流动期间，已经从晶闸管上表面穿过区域9的整个厚度直至层7而形成电阻性多孔硅30，并且可以部分地延伸进入层7中。
本领域技术人员可以通过选择电解浴剂的种类和浓度、电流58 的数值、电流流动时间以及层7的掺杂层而调整发射极短路30的多孔硅的厚度、电阻率和多孔性。如果对于壁50选择掺杂水平小于层 7的掺杂水平，例如分别从1016至1017原子/cm3以及大于1018原子 /cm3，则多孔硅部位62将比区域30更具有电阻性。
已经描述了具体实施例。对于本领域技术人员而言将发生各种改变、修改和改进。特别地，尽管在上述实施例中晶闸管具有八个发射极短路开孔，该数目可以变化，并且可以更小或者远远更大。
此外，尽管实施例中硅发射极短路17的数目与多孔硅发射极短路30的数目相同，但是多孔硅发射极短路30的数目、与硅发射极短路17的数目之间的比例可以不同于1。
在如前所述实施例中，已经示出了具有中心栅极的结构。实施例可以适用于其他栅极配置结构，并且甚至如下文所述适用于无栅极结构。
最后，尽管已经对于晶闸管型部件示出了在SCR型部件中多孔硅发射极短路对于获得温度稳定特性的优点，发射极短路可以由本领域技术人员容易地适用于对于部件的温度稳定性特性具有相同结果的任何类型SCR部件，例如三端双向可控硅开关元件、或者单向或双向肖特基二极管。在双向部件中，可以提供在它们每个表面上包括两个如前所述类型的发射极短路的对称结构。
这些改变、修改和改进意在作为本公开的一部分，并且意在落入本发明的精神和范围内。因此，前述说明仅是借由示例、但是并非意在限定的方式。本发明仅由以下权利要求及其等价方式所限定。

Claims (8)

1.一种用于电子集成部件的方法，包括：
在第二导电类型的硅层中形成第一导电类型的硅区域，其中所述硅区域在多个部位中被中断；
形成所述第二导电类型的外围硅壁；
在上表面上沉积掩模层，所述掩模层包括开口，所述开口暴露出中断的所述部位和所述外围硅壁中的至少一个；
浸入接触所述上表面的第一电解液浴剂中；
浸入接触与所述上表面相对的下表面的第二电解液浴剂中；
其中正电极和负电极分别浸入所述第一电解液浴剂和所述第二电解液浴剂中；以及
在所述正电极和所述负电极之间施加电压，以便在所述外围硅壁中具有电流，所述电流的一部分在所述硅层中流动并且通过所述部位，以在中断的所述部位中将所述硅层转换为电阻性多孔硅区域。
2.根据权利要求1所述的方法，其中所述第一电解液浴剂和所述第二电解液浴剂由包括水、氢氟酸、乙醇或乙酸的混合物制成。
3.一种电子集成部件，包括：
多层半导体衬底，包括具有第一导电类型并且具有上表面的顶部半导体层；
形成在所述顶部半导体层中的具有第二导电类型的区域，所述区域从所述上表面延伸到所述顶部半导体层中；
在所述第二导电类型的所述区域中形成的发射极短路区域，所述发射极短路区域包括：
多个第一发射极短路区域，其包括所述顶部半导体层的部分，所述顶部半导体层的部分延伸到所述第二导电类型的所述区域内的第一开口中；以及
多个第二发射极短路区域，其包括多孔硅，所述多孔硅延伸到所述第二导电类型的所述区域内的第二开口中至足以与所述顶部半导体层接触的深度。
4.根据权利要求3所述的电子集成部件，其中包括多孔硅的所述多个第二发射极短路区域的厚度大于具有所述第二导电类型的所述区域的厚度。
5.根据权利要求3所述的电子集成部件，其中所述多孔硅在25℃的电阻率在从103至104Ω.cm的范围内。
6.根据权利要求3所述的电子集成部件，还包括：
第一电极，形成在所述上表面上，并且与具有所述第二导电类型的所述区域以及所述第一发射极短路区域和所述第二发射极短路区域两者接触；
第二电极，形成在所述上表面上并且仅与所述顶部半导体层接触；以及
第三电极，形成在所述多层半导体衬底的底表面上。
7.根据权利要求6所述的电子集成部件，其中所述集成部件是可控硅整流器(SCR)类型的。
8.根据权利要求3所述的电子集成部件，还包括由以下各项形成的外围结构：
与所述顶部半导体层横向相邻的多孔硅区域；以及
所述第一导电类型的下部区域。
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