JP6053415B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6053415B2 JP6053415B2 JP2012205543A JP2012205543A JP6053415B2 JP 6053415 B2 JP6053415 B2 JP 6053415B2 JP 2012205543 A JP2012205543 A JP 2012205543A JP 2012205543 A JP2012205543 A JP 2012205543A JP 6053415 B2 JP6053415 B2 JP 6053415B2
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- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Description
本発明に係る他の半導体装置は、第1導電型の半導体基板と素子形成領域と電界緩和領域と絶縁性の保護膜とを有している。第1導電型の半導体基板は、互いに対向する第1主表面および第2主表面を有する。素子形成領域は、半導体基板の第1主表面側における所定の領域に形成され、第1主表面の側と第2主表面の側との間で電流の導通を図る所定の半導体素子が配置される。電界緩和領域は、半導体基板の第1主表面側における、素子形成領域の側方に、素子形成領域に接する態様で形成されている。絶縁性の保護膜は、第1主表面側を覆うように形成され、所定の誘電率を有する。電界緩和領域は、絶縁領域と第1導電型のチャネルストッパ領域と複数のフローティング電極と第2導電型の領域とを備えている。絶縁領域は、第1主表面から所定の深さにわたり形成され、所定の誘電率よりも低い誘電率を有する。第1導電型のチャネルストッパ領域は、絶縁領域に対して素子形成領域が位置する側とは反対側に距離を隔てられるように形成されている。複数のフローティング電極は、素子形成領域とチャネルストッパ領域との間を結ぶ方向に結合容量の成分を有する態様で配置されている。第2導電型の領域は、絶縁領域からさらに深い領域にわたり形成されている。絶縁領域は、素子形成領域の側に位置する部分よりもチャネルストッパ領域の側に位置する部分の方が深くなるように形成されている。
本発明の実施の形態1に係る半導体装置について説明する。図1に示すように、半導体装置1では、半導体基板2の一方の表面から所定の深さにわたりn−層3が形成されている。n−層3における所定の領域には、主電流が流れる活性領域10が形成されている。活性領域10は素子形成領域とされ、活性領域10には、スイッチング素子の一例として、IGBT11が形成されている。
ここで、単結晶シリコンの密度が約2.3g/cm3であることから、多孔質シリコンの密度は1.0g/cm3程度であれば、Rの値は1となり、酸化の前後において体積を一定に維持することができる。
実施の形態1に係る半導体装置の変形例1として、終端構造部に耐圧層としてリサーフ層を備えたリサーフ構造の半導体装置について説明する。図7に示すように、半導体装置1では、多孔質酸化膜領域26を側方と下方とから取り囲むように、p型のリサーフ層23が形成されている。リサーフ層23は、活性領域10のpベース層13に接するように形成されている。なお、これ以外の構成については、図1に示す半導体装置1と同様なので、同一部材には同一符号を付しその説明を繰り返さないこととする。
実施の形態1に係る半導体装置の変形例2として、終端構造部にトレンチ構造を備えた半導体装置について説明する。
実施の形態1に係る半導体装置の変形例3として、終端構造部にトレンチ構造を備えた他の半導体装置について説明する。
本発明の実施の形態2に係る半導体装置について説明する。図13に示すように、半導体装置1では、多孔質酸化膜領域26が、pベース層13の側からチャネルストッパ領域22の側に向かって、階段状(段階的)に徐々に深い位置にまで形成されている。なお、これ以外の構成については、図1に示す半導体装置と同様なので、同一部材には同一符号を付しその説明を繰り返さないこととする。
実施の形態2に係る半導体装置の変形例1として、終端構造部に耐圧層としてリサーフ層を備えたリサーフ構造の半導体装置について説明する。図15に示すように、半導体装置1では、段階的に厚くなるように形成された多孔質酸化膜領域26を側方と下方とから取り囲むように、耐圧層としてp型のリサーフ層23が形成されている。リサーフ層23は、活性領域10のpベース層13に接するように形成されている。なお、これ以外の構成については、図13に示す半導体装置と同様なので、同一部材には同一符号を付しその説明を繰り返さないこととする。
実施の形態2に係る半導体装置の変形例2として、終端構造部にトレンチ構造を備えた半導体装置について説明する。図17に示すように、半導体装置1では、段階的に厚くなるように形成された多孔質酸化膜領域26を貫通するように、複数のトレンチ28が形成されている。複数のトレンチ28は、活性領域10とチャネルストッパ領域22との間を結ぶ方向に互いに間隔を隔てて配置されている。多孔質酸化膜領域26から下方へ突出したトレンチ28の部分を側方と下方とから取り囲むように、耐圧層としてガードリング領域21が形成されている。
Claims (8)
- 互いに対向する第1主表面および第2主表面を有する第1導電型の半導体基板と、
前記半導体基板の前記第1主表面側における所定の領域に形成され、前記第1主表面の側と前記第2主表面の側との間で電流の導通を図る所定の半導体素子が配置される素子形成領域と、
前記半導体基板の前記第1主表面側における、前記素子形成領域の側方に、前記素子形成領域に接する態様で形成された電界緩和領域と、
前記第1主表面側を覆うように形成され、所定の誘電率を有する絶縁性の保護膜と
を有し、
前記電界緩和領域は、
前記第1主表面から所定の深さにわたり形成され、前記誘電率よりも低い誘電率を有する絶縁領域と、
前記絶縁領域に対して前記素子形成領域が位置する側とは反対側に距離を隔てられるように形成された第1導電型のチャネルストッパ領域と、
前記素子形成領域と前記チャネルストッパ領域との間を結ぶ方向に結合容量の成分を有する態様で配置された複数のフローティング電極と、
前記絶縁領域からさらに深い領域にわたり形成された第2導電型の領域と、
前記方向にそれぞれ間隔を隔てられるとともに、前記絶縁領域を貫通して前記第2導電型の領域にそれぞれ達するように形成された複数のトレンチと
を備え、
複数の前記フローティング電極は、複数の前記トレンチのそれぞれの内壁に位置する部分を含む態様で形成された、半導体装置。 - 複数の前記フローティング電極のそれぞれは、複数の前記トレンチのそれぞれの内壁を覆うように形成された、請求項1記載の半導体装置。
- 複数の前記フローティング電極は、
相対的に下側に配置された第1フローティング電極と、
相対的に上側に配置された第2フローティング電極と
を含み、
前記第1フローティング電極および前記第2フローティング電極は、前記第1フローティング電極と前記第2フローティング電極とによる容量結合が、前記方向に結合容量の成分を有する態様で配置され、
前記第1フローティング電極は、複数の前記トレンチのそれぞれの内壁の部分に形成され、
前記第2フローティング電極は、前記トレンチの開口端における前記絶縁領域の部分に形成された、請求項1記載の半導体装置。 - 互いに対向する第1主表面および第2主表面を有する第1導電型の半導体基板と、
前記半導体基板の前記第1主表面側における所定の領域に形成され、前記第1主表面の側と前記第2主表面の側との間で電流の導通を図る所定の半導体素子が配置される素子形成領域と、
前記半導体基板の前記第1主表面側における、前記素子形成領域の側方に、前記素子形成領域に接する態様で形成された電界緩和領域と、
前記第1主表面側を覆うように形成され、所定の誘電率を有する絶縁性の保護膜と
を有し、
前記電界緩和領域は、
前記第1主表面から所定の深さにわたり形成され、前記誘電率よりも低い誘電率を有する絶縁領域と、
前記絶縁領域に対して前記素子形成領域が位置する側とは反対側に距離を隔てられるように形成された第1導電型のチャネルストッパ領域と、
前記素子形成領域と前記チャネルストッパ領域との間を結ぶ方向に結合容量の成分を有する態様で配置された複数のフローティング電極と、
前記絶縁領域からさらに深い領域にわたり形成された第2導電型の領域と
を備え、
前記絶縁領域は、前記素子形成領域の側に位置する部分よりも前記チャネルストッパ領域の側に位置する部分の方が深くなるように形成された、半導体装置。 - 前記方向にそれぞれ間隔を隔てられるとともに、前記絶縁領域を貫通して前記第2導電型の領域にそれぞれ達するように形成された複数のトレンチを備え、
複数の戦記フローティング電極は、複数の前記トレンチのそれぞれの内壁を覆うように形成された、請求項4記載の半導体装置。 - 前記第2導電型の領域は、前記方向に間隔を隔てて形成されたガードリング領域である、請求項1〜5のいずれか1項に記載の半導体装置。
- 前記第2導電型の領域は、前記絶縁領域を側方と下方とから取り囲むように形成されたリサーフ領域である、請求項4記載の半導体装置。
- 前記絶縁領域は多孔質酸化膜領域である、請求項1〜7のいずれか1項に記載の半導体装置。
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