CN109545742A - 半导体装置的制造方法及半导体装置 - Google Patents

半导体装置的制造方法及半导体装置 Download PDF

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Publication number
CN109545742A
CN109545742A CN201810161545.9A CN201810161545A CN109545742A CN 109545742 A CN109545742 A CN 109545742A CN 201810161545 A CN201810161545 A CN 201810161545A CN 109545742 A CN109545742 A CN 109545742A
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semiconductor
crystal wafer
semiconductor chip
lamination
semiconductor crystal
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CN201810161545.9A
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CN109545742B (zh
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黑泽哲也
大野天颂
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

实施方式提供一种缩短半导体芯片的积层所耗费的时间且能够抑制异物侵入到半导体芯片间的半导体装置的制造方法及半导体装置。实施方式的半导体装置的制造方法为如下：对具有大致相同的构成且包含多个半导体芯片的第1及第2半导体晶圆的切割区域照射激光，在第1及第2半导体晶圆的各自的半导体结晶形成具有应变的改质层。将第2半导体晶圆以向第1方向偏移的方式积层在第1半导体晶圆上，所述第1方向是从第1半导体晶圆的多个半导体芯片的各自的第1边朝向该第1边的对边的方向。将第1及第2半导体晶圆劈裂。

Description

半导体装置的制造方法及半导体装置
[相关申请案]
本申请享有日本专利申请2017-180375号(申请日期：2017年9月20日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本实施方式涉及一种半导体装置的制造方法及半导体装置。
背景技术
半导体晶圆在利用切割而单片化为半导体芯片后，在裸片接合(die boning)步骤中以半导体芯片的形式搭载在框架或安装基板上。此时，存在将多个半导体芯片积层在安装基板上而制成大容量或高功能的半导体装置的情况。在将半导体芯片积层时，各半导体芯片在相对于其正下方的其它半导体芯片或安装基板位置对准后，粘接在该其它半导体芯片或安装基板上。因此，有半导体芯片的积层步骤耗费较长时间且异物进入半导体芯片间的担忧。
发明内容
实施方式是提供一种缩短半导体芯片的积层所耗费的时间且能够抑制异物侵入到半导体芯片间的半导体装置的制造方法及半导体装置。
实施方式的半导体装置的制造方法是对具有大致相同的构成且包含多个半导体芯片的第1及第2半导体晶圆的切割区域照射激光，而在第1及第2半导体晶圆的各自的半导体结晶上形成具有应变的改质层。将第2半导体晶圆以向第1方向偏移的方式积层在第1半导体晶圆上，该第1方向是从第1半导体晶圆的多个半导体芯片的各自的第1边朝向该第1边的对边的方向。将第1及第2半导体晶圆劈裂。
附图说明
图1(A)及(B)是表示第1实施方式的半导体装置的制造方法的一例的图。
图2是继图1之后，表示半导体装置的制造方法的一例的图。
图3是沿图2的切割线的局部剖视图。
图4是继图2之后，表示半导体装置的制造方法的一例的图。
图5是继图4之后，表示半导体装置的制造方法的一例的图。
图6是表示第1半导体晶圆的构成的一例的俯视图。
图7是将1个半导体芯片抽出表示的立体图。
图8是沿图5的D1方向的剖视图。
图9是继图5之后，表示半导体装置的制造方法的一例的图。
图10是继图9之后，表示半导体装置的制造方法的一例的图。
图11是表示积层体11的构成例的剖视图。
图12是表示第2实施方式的半导体装置2的构成例的剖视图。
图13是表示第2实施方式的积层体11的构成例的剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。本实施方式并不对本发明进行限定。在以下的实施方式中，半导体基板的上下方向表示将设置着半导体元件的表面或其相反的背面设为上时的相对方向，有时与按照重力加速度的上下方向不同。
(第1实施方式)
图1(A)～图10是表示第1实施方式的半导体装置的制造方法的一例的概略图。本实施方式的半导体装置利用激光切割在多个半导体晶圆的各自的切割线的硅的内部形成改质层。然后，将多个半导体晶圆以晶圆状态积层，且在树脂片上延伸，并在积层状态下将半导体芯片单片化。多个半导体芯片以积层的状态安装在安装基板上。半导体装置例如可以是NAND(Not-AND，与非)型EEPROM(Electrically Erasable Programmable Read-OnlyMemory，电可擦可编程只读存储器)等半导体存储器，但并不限定于此，可以是将相同构成的多个半导体芯片积层而构成的任意的半导体装置。
首先，如图1(A)所示，在第1半导体晶圆100上形成半导体元件101。半导体元件101形成在每个半导体芯片(第1半导体芯片)10。多个半导体芯片10间具有切割线DL，之后将通过切断该切割线DL而将半导体芯片10单片化。多个半导体芯片10分别具有大致相同的图案，且具有大致相同构成的半导体集成电路。
在第1半导体晶圆100的多个半导体芯片10的表面形成着接合垫BP。对于接合垫BP，例如使用Cu、Al、Aa、Au等导电性金属。接合垫BP设置在各半导体芯片10的第1边S1的附近，且沿该第1边S1排列。
其次，为了清洁第1半导体晶圆100的表面而进行等离子体处理。接下来，如图1(B)所示，将保护片103贴附在第1半导体晶圆100的表面。在第1半导体晶圆100上设置着感光性粘接剂(图6的110)作为保护膜及粘接剂。感光性粘接剂是例如像感光性聚酰亚胺等那样，可利用光刻法技术进行加工且通过加热产生粘附性的保护材料。此外，对于感光性粘接剂的涂布区域，之后将参照图6进行说明。
接下来，如图2所示，使用激光振荡器105对第1半导体晶圆100的背面的与切割线(切割区域)对应的部分照射激光。由此，如图3所示，在第1半导体晶圆100的内部(硅基板的内部)形成改质层(非晶层或多晶硅层)121。图3是沿图2的切割线的局部剖视图。激光振荡器105使激光在硅基板的任意深度位置处聚焦。激光为了能够将硅单晶改质，优选具有800nm以上且3000nm以下的波长。在为低于800nm的波长的情况下，被硅内部吸收的概率增加，而变得难以形成改质层。在为超过3000nm的波长的情况下，透过硅的概率增加，而变得难以形成改质层。通过对硅基板照射这种激光，在激光的聚焦位置加热硅单晶，而改质成非晶硅或多晶硅。
激光是每隔某间距P1的间隔而照射的。由此，在改质层121中，改质部分122是以某间距P1的间隔而形成。改质层121对半导体晶圆内的周围的半导体结晶(例如硅单晶)具有应变。因此，在改质层121的周围生成劈裂区域(未图示)。当间距P1较窄时，改质部分122的周围的劈裂区域相连，成为层状(带状)的改质层121。
接下来，如图4那样，利用研磨石107从第1半导体晶圆100的背面对硅基板进行研磨。此时，将第1半导体晶圆100研磨到比图3的改质层121浅的位置，而使改质层121残留在第1半导体晶圆100内。由此，第1半导体晶圆100得以薄膜化。
第2～第n半导体晶圆(n为2以上的整数)也与第1半导体晶圆100同样地形成。第2～第n半导体晶圆具有与第1半导体晶圆100大致相同的构成，且包含大致相同的多个半导体芯片。另外，也与第1半导体晶圆100同样地，在第2～第n半导体晶圆沿切割线形成着改质层。以下，将第1～第n半导体晶圆表示为100_1～100_n。
接下来，如图5所示，将第1半导体晶圆100_1的背面贴附到在晶圆环130内延展的柔性的粘附性片131。将第2半导体晶圆100_2积层在第1半导体晶圆100_1上，并将第3半导体晶圆100_3积层在第2半导体晶圆100_2上。对于第4～第n半导体晶圆(未图示)，也可同样地积层。
此处，第2半导体晶圆100_2以向第1方向D1偏移的方式积层，该第1方向D1是从第1半导体晶圆100_1的多个半导体芯片10的各自的第1边S1朝向该第1边S1的对边S2的方向。
例如，图6是表示第1半导体晶圆100_1的构成的一例的俯视图。第2～第n半导体晶圆100_2～100_n的构成可与第1半导体晶圆100_1的构成相同。因此，此处对第1半导体晶圆100_1的构成进行说明，省略第2～第n半导体晶圆100_2～100_n的构成的说明。
第1半导体晶圆100_1具有多个半导体芯片10。在多个半导体芯片10间设置着切割线DL。虽然在图6中并未图示，但在切割线DL形成着改质层。在多个半导体芯片10分别设置着半导体元件101，且在各第1半导体芯片10的第1边S1的附近，沿第1边S1排列着接合垫BP。
作为第1粘接剂的感光性粘接剂110在多个半导体芯片10的各自的表面，被覆从边S2到接合垫BP近前的第1边界B1为止。而且，感光性粘接剂110不被覆从第1边界B1到第1边S1为止的接合垫BP的区域。
感光性粘接剂110在图1(A)所示的步骤之前，涂布在第1半导体晶圆100_1上，并利用光刻法技术以如下方式图案化，即，被覆从多个半导体芯片10的第1边S1的对边S2到接合垫BP近前的第1边界B1为止，且不被覆从该第1边界B1到第1边S1为止。
图7是将1个半导体芯片10抽出表示的立体图。如果参照图7，那么可知，感光性粘接剂110被覆从边S2到接合垫BP近前的第1边界B1为止，并且，露出从第1边界B1到第1边S1为止的接合垫BP的区域。
图8是沿图5的D1方向的剖视图。在树脂片131上积层着第1～第3半导体晶圆100_1～100_3。第2半导体晶圆100_2从第1半导体晶圆100_1的多个半导体芯片10的各自的第1边S1偏移到第1边界B1为止。第3半导体晶圆100_3从第2半导体晶圆100_2的多个半导体芯片10的各自的第1边S1偏移到第1边界B1为止。从第1边S1到第1边界B1为止的偏移宽度在下文中也称为接合垫BP的区域Rbp。
此外，积层的半导体晶圆的数量并无限定。因此，在第2半导体晶圆上也可以积层具有与第1及第2半导体晶圆大致相同构成的第3～第n半导体晶圆(n为3以上)。在这种情况下，第2～第n半导体晶圆100_2～100_n分别相对于正下方的半导体晶圆向第1方向D1偏移地积层。该偏移宽度等于从第1边S1到第1边界B1为止的宽度(接合垫BP的区域Rbp的宽度)。
在将第1～第n半导体晶圆100_1～100_n积层时，也可以利用某压力对积层的第1～第n半导体晶圆100_1～100_n只按压1次。由此，将第1～第n半导体晶圆100_1～100_n压接。或者，也可以在利用第1压力对积层的第1～第n半导体晶圆100_1～100_n进行按压后，再用高于第1压力的第2压力进行按压。也就是说，也可用不同的压力对积层的第1～第n半导体晶圆100_1～100_n进行多次按压。在这种情况下，也可以在用第1压力进行按压后，利用不同的压缩装置以第2压力进行按压。
接下来，一边对积层的第1～第n半导体晶圆100_1～100_n加热一边进行按压，从而使感光性粘接剂110回焊。由此，将第1～第n半导体晶圆100_1～100_n粘接。
接下来，如图9所示，通过利用上推部件132从下方将树脂片131上推，而将树脂片131拉伸(延伸)。由此，第1～第3半导体晶圆100_1～100_3与树脂片131一起被拉伸。此时，将第1～第3半导体晶圆100_1～100_3沿各自的改质层(图8的虚线L)劈裂，而单片化为积层的多个半导体芯片10。下文中也将积层的多个半导体芯片10称为积层体11。
接下来，如图10所示，将积层体11安装(裸片接合)在安装基板120上。此时，对树脂片131照射UV(ultraviolet，紫外线)光，使树脂片131的粘附性降低。利用导线125将设置在半导体芯片10上的接合垫BP与安装基板120接合。进而，利用树脂129将半导体芯片10及导线125密封。由此，本实施方式的半导体装置1完成。
根据本实施方式，在利用激光在多个半导体晶圆100_1、100_2的各自的切割线DL处形成改质层121后，将半导体晶圆100_1、100_2错开接合垫BP的区域地进行积层。然后，将积层的多个半导体晶圆100_1、100_2同时劈裂。也就是说，本实施方式并非是在将各半导体晶圆单片化为半导体芯片后再将半导体芯片积层，而是在将多个半导体晶圆劈裂前进行积层，然后在积层状态下对多个半导体晶圆进行一次劈裂。
如果在将半导体晶圆单片化为半导体芯片后再将半导体芯片积层的情况下，那么在将半导体芯片安装在安装基板上时，必须将各半导体芯片逐个位置对准。因此，半导体芯片的积层耗费时间，生产性变差。另外，在将半导体芯片积层在其它半导体芯片上时，污物或微粒等异物侵入到半导体芯片与其它半导体芯片之间的可能性变高。
相对于此，根据本实施方式的制造方法，半导体晶圆是以晶圆状态进行积层，因此不需要将半导体芯片逐个位置对准，能够大幅度减少积层时位置对准的次数。这将牵涉到半导体芯片的积层时间的缩短。另外，半导体晶圆的劈裂的次数也减少，因此劈裂时产生的微粒也减少。进而，由于将多个半导体芯片(也就是积层体11)以积层状态安装在安装基板120上，所以异物侵入到半导体芯片与其它半导体芯片之间的可能性变低。这将牵涉到半导体装置1的良率提高。
进而，将半导体晶圆以晶圆状态位置对准，而不将半导体芯片逐个位置对准。因此，在半导体封装内，积层的半导体芯片间的位置稳定，这些半导体芯片的位置的偏差减少。如果积层体11的半导体芯片间的位置的偏差减少，那么能够减少考虑了该偏差的容限。因此，能够实质上减少积层体11内的多个半导体芯片10的偏移宽度，结果，能够减小半导体装置1的封装尺寸。
根据本实施方式，如图7所示，在半导体晶圆100_1～100_n所包含的多个半导体芯片10的各自的表面，感光性粘接剂110被覆从边S2到接合垫BP近前的第1边界B1为止，且不被覆从该第1边界B1到第1边S1为止。并且，如图8所示，积层的半导体晶圆100_2～100_n分别相对于它们正下方的半导体晶圆100_1～100_n－1以从第1边界B1偏移到第1边S1为止的方式积层。也就是说，在接合垫BP的区域并未设置感光性粘接剂110，半导体芯片10的感光性粘接剂110几乎不与位于接合垫BP的上方的其它半导体芯片10的背面接触。由此，能够容易地将积层的半导体晶圆100_1～100_n劈裂，并且，相互相邻的积层体11在劈裂后不会附着，而容易被单片化。
(半导体装置)
接下来，参照图10及图11，对本实施方式的半导体装置1的构成进行说明。图10是表示第1实施方式的半导体装置1的构成例的剖视图。图11是表示积层体11的构成例的剖视图。
本实施方式的半导体装置1具备安装基板120、第1～第3半导体芯片10_1～10_3、感光性粘接剂110、接合导线125、及树脂129。
安装基板120在它表面及背面设置着配线层128。在安装基板120的表面上设置着积层的第1～第3半导体芯片10_1～10_3(积层体11)。在安装基板120的背面设置着凸块127。安装基板120例如以玻璃环氧树脂等绝缘体作为基体，且在该基体的表面及背面具备配线层128。对于配线层128，例如使用铜等导电性金属。
第1～第3半导体芯片10_1～10_3设置在安装基板120上，且具有沿表面的第1边S1配置的接合垫BP。第1～第3半导体芯片10_1～10_3的各构成如参照图1及图7所说明的那样。因此，在第1～第3半导体芯片10_1～10_3的各自的第1边S1的附近，沿第1边S1排列着接合垫BP。感光性粘接剂110被覆从边S2到接合垫BP近前的第1边界B1为止，并且，不被覆从第1边界B1到第1边S1为止的接合垫BP的区域。
第2半导体芯片10_2向第1方向D1偏移地积层，该第1方向是从第1半导体芯片10_1的第1边S1朝向第1边界B1的方向。第2半导体芯片100_2相对于第1半导体芯片10_1的偏移宽度与从第1半导体芯片10_1的第1边界B1到第1边S1为止的接合垫BP的区域Rbp的宽度大致相等。第2半导体芯片10_2与第3半导体芯片10_3之间的感光性粘接剂110(第2粘接剂)在第2半导体芯片10_2中，被覆从边S2到接合垫BP近前的第1边界B1为止，并且，不被覆从第1边界B1到第1边S1为止的接合垫BP的区域Rbp。
第3半导体芯片100_3也相对于第2半导体芯片10_2向第1方向D1偏移地积层。第3半导体芯片10_3相对于第2半导体芯片10_2的偏移宽度也与从第2半导体芯片10_2的第1边界B1到第1边S1为止的接合垫BP的区域Rbp的宽度大致相等。第3半导体芯片10_3上的感光性粘接剂110在第3半导体芯片10_3，也被覆从边S2到接合垫BP近前的第1边界B1为止，并且，不被覆从第1边界B1到第1边S1为止的接合垫BP的区域Rbp。
接合导线125连接在接合垫BP与安装基板120上的配线层128之间。接合垫BP经由接合导线125而与配线层128或凸块127电连接。对于接合导线125，例如使用金等导电性金属。
树脂129被覆并保护第1～第3半导体芯片10_1～10_3及接合导线125。
此外，在图10及图11中，示出了第1～第3半导体芯片10_1～10_3。但是，积层的半导体芯片的数量并不限定为3个。因此，也可以积层着半导体芯片10_1～10_n(n为2以上的整数)。
根据本实施方式，感光性粘接剂110在半导体晶圆100_1～100_3各自所包含的多个半导体芯片10_1～10_3的表面，被覆从边S2到接合垫BP近前的第1边界B1为止，且不被覆从该第1边界B1到第1边S1为止。也就是说，感光性粘接剂110不被覆接合垫BP的区域Rbp，而被覆除此之外的半导体芯片10_1～10_3的表面。由此，能够在将经激光切割的半导体晶圆100_1～100_3以晶圆状态错开接合垫BP的区域Rbp地积层，然后，将半导体晶圆100_1～100_3劈裂。感光性粘接剂110与位于接合垫BP上方的其它半导体芯片10的背面几乎不接触。由此，能够容易地将半导体晶圆100_1～100_n劈裂，而能够容易地将相互相邻的积层体11单片化。
(第2实施方式)
图12是表示第2实施方式的半导体装置2的构成例的剖视图。在第2实施方式中，第1～第k半导体芯片(3≦k≦n－1)向第1方向D1偏移地积层。第k+1半导体芯片～第n半导体芯片向与第1方向D1相反的第2方向D2偏移地积层。此外，此处将n设为2以上的整数。在n为2时，第2半导体芯片相对于第1半导体芯片向第1方向D1偏移地积层。在n为3时，第2半导体芯片相对于第1半导体芯片向第1方向D1偏移地积层，且第3半导体芯片相对于第2半导体芯片向第2方向D2偏移地积层。
例如，在图12中，第1～第4半导体芯片10_1～10_4向第1方向D1偏移地积层。第1～第4半导体芯片10_1～10_4的各自的偏移宽度可以与第1实施方式的第2半导体芯片10_2相对于第1半导体芯片10_1的偏移宽度大致相等。也就是说，第1～第4半导体芯片10_1～10_4的各自的偏移宽度与接合垫BP的区域Rbp的D1方向的宽度大致相等。第1～第4半导体芯片10_1～10_4是具有大致相同构成的半导体芯片。另一方面，第5～第8半导体芯片10_5～10_8向第2方向D2偏移地积层。第5～第8半导体芯片10_5～10_8的各自的偏移宽度也可以与第1实施方式的第2半导体芯片10_2相对于第1半导体芯片10_1的偏移宽度大致相等。第5～第8半导体芯片10_5～10_8是具有大致相同构成的半导体芯片。这样，多个半导体芯片在第1方向D1上偏移地积层后，也可以在中途向相反方向D2偏移地积层。
图13是表示第2实施方式的积层体11的构成例的剖视图。第1～第4半导体芯片10_1～10_4的接合垫BP设置在第1边S1的附近，且沿第1边S1配置。另一方面，第5～第8半导体芯片10_5～10_8向与第1～第4半导体芯片10_1～10_4相反的方向偏移，因此，第5～第8半导体芯片10_5～10_8的接合垫BP设置在第2边S2的附近，且沿第2边S2配置。由此，能够将接合导线125与第1～第8半导体芯片10_1～10_8的所有接合垫BP连接。
感光性粘接剂110分别设置在第1～第8半导体芯片10_1～10_8间，且未设置在第1～第8半导体芯片的各自的接合垫BP上。也就是说，和第1半导体芯片10_1与第2半导体芯片10_2之间的感光性粘接剂110(第1粘接剂)同样地，在第2～第8半导体芯片10_2～10_8间也设置着感光性粘接剂110(第2粘接剂)。第2～第8半导体芯片10_2～10_8的感光性粘接剂110分别与第1半导体芯片10_1的感光性粘接剂110同样地，不被覆接合垫BP的区域Rbp，而被覆除此之外的半导体芯片10_2～10_8的表面。
第2实施方式的其它构成可与第1实施方式的对应的构成相同。这样，即便第1～第8半导体芯片10_1～10_8以在中途向相反方向偏移的方式积层，也能够获得与第1实施方式同样的效果。
对第2实施方式的半导体装置2的制造方法进行说明。首先，将分别包含第1～第4半导体芯片10_1～10_4的4片半导体晶圆(未图示)在第1方向D1上错开地积层。其次，如所述那样，将积层的半导体晶圆劈裂，而将第1～第4半导体芯片10_1～10_4单片化为1个积层体。
另一方面，将分别包含第5～第8半导体芯片10_5～10_8的4片半导体晶圆(未图示)在第2方向D2上错开地积层。其次，如所述那样，将积层的半导体晶圆劈裂，而将第5～第8半导体芯片10_5～10_8单片化为1个积层体。
接下来，将第1～第4半导体芯片10_1～10_4的积层体搭载在安装基板120上。然后，将第5～第8半导体芯片10_5～10_8的积层体搭载在第1～第4半导体芯片10_1～10_4的积层体上。
这样，在第2实施方式中，第1～第4半导体芯片10_1～10_4被单片化为1个积层体，第5～第8半导体芯片10_5～10_8被单片化为与第1～第4半导体芯片10_1～10_4不同的积层体。然后，只要将第1～第4半导体芯片10_1～10_4的积层体搭载安装基板120上，再将第5～第8半导体芯片10_5～10_8的积层体搭载在第1～第4半导体芯片10_1～10_4的积层体上即可。由此，能够在安装基板120上形成第1～第8半导体芯片10_1～10_8的积层体。
第2实施方式的其它制造步骤可与第1实施方式的对应的制造步骤相同。由此，第2实施方式的制造方法能够获得与第1实施方式的制造方法同样的效果。
此外，在图12及图13中，示出了积层着第1～第8半导体芯片10_1～10_8的状态。然而，积层的半导体芯片的数量并不限定于8个。因此，也可以积层着半导体芯片10_1～10_n(n为2以上的整数)。
另外，偏移方向的变更可以在半导体芯片10_1～10_n中任意的半导体芯片10_k(2≦k≦n－1)进行变更。也就是说，也可以将半导体芯片10_1～10_k在第1方向D1上错开地积层，将半导体芯片10_k+1+1～10_n在第2方向D2上错开地积层。
对本发明的若干个实施方式进行了说明，但这些实施方式是作为示例而提出的，并不意欲对发明的范围进行限定。这些实施方式可以通过其他各种方式进行实施，在不脱离发明的主旨的范围内，可进行各种省略、置换、变更。该等实施方式及其变化包含在发明的范围或主旨内，同时包含在权利要求书所记载的发明及其等同的范围内。
[符号的说明]
100 第1半导体晶圆
101 半导体元件
10 半导体芯片
11 积层体
110 光性粘接剂
120 安装基板
130 树脂
122 改质部分
125 导线
127 凸块
128 配线层
S1、S2 边
B1 第1边界
BP 接合垫
Rbp 区域
DL 切割线
D1 第1方向
D2 第2方向

Claims (13)

1.一种半导体装置的制造方法，其特征在于具备：
对具有大致相同构成且包含多个半导体芯片的第1及第2半导体晶圆的切割区域照射激光，在所述第1及第2半导体晶圆的各自的半导体结晶形成具有应变的改质层；
将第2半导体晶圆以向第1方向偏移的方式积层在所述第1半导体晶圆上，所述第1方向是从所述第1半导体晶圆的所述多个半导体芯片的各自的第1边朝向该第1边的对边的方向；
将所述第1及第2半导体晶圆劈裂。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于还具备：以如下方式形成第1粘接剂，即，在所述第1半导体晶圆所包含的多个半导体芯片的各自的表面，被覆从所述多个半导体芯片的第1边的对边到设置在该多个半导体芯片的接合垫近前的第1边界为止，且不被覆从该第1边界到所述第1边为止；
将第2半导体晶圆以从所述第1半导体晶圆的所述多个半导体芯片的各自的第1边偏移到所述第1边界为止的方式，积层在所述第1半导体晶圆上。
3.根据权利要求1或2所述的半导体装置的制造方法，其特征在于还具备：
将具有与第1及第2半导体晶圆大致相同构成的第3～第n半导体晶圆(n为3以上)积层在所述第2半导体晶圆上；
将积层的所述第1～第n半导体晶圆劈裂；
所述第2～第n半导体晶圆分别相对于正下方的半导体晶圆向所述第1方向偏移地积层。
4.根据权利要求2所述的半导体装置的制造方法，其特征在于：
所述第1粘接剂是感光性粘接剂，
在所述第1粘接剂的形成中，在将所述第1粘接剂设置在所述第1半导体晶圆上后，利用光刻法技术以如下方式加工第1粘接剂，即，被覆从所述多个半导体芯片的第1边的对边到设置在该多个半导体芯片的接合垫近前的第1边界为止，且不被覆从该第1边界到所述第1边为止。
5.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：
在将所述第2半导体晶圆积层在所述第1半导体晶圆上时，以第1压力按压该第1及第2半导体晶圆，之后，以高于所述第1压力的第2压力进行按压。
6.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：
所述第1及第2半导体晶圆的各自的所述多个半导体芯片具有大致相同构成。
7.根据权利要求1或2所述的半导体装置的制造方法，其特征在于还具备：
在将所述第1及第2半导体晶圆劈裂后，
将积层的所述多个半导体芯片安装在安装基板上；
利用导线将设置在所述多个半导体芯片上的接合垫与所述安装基板接合；
利用树脂被覆所述多个半导体芯片及所述导线。
8.一种半导体装置，其特征在于具备：
安装基板；
第1半导体芯片，设置在所述安装基板上，且具有沿表面的第1边配置的接合垫；
第1粘接剂，在所述第1半导体芯片的表面，被覆从所述第1边的对边到所述接合垫近前的第1边界为止，且不被覆从该第1边界到所述第1边为止；
第2半导体芯片，向第1方向偏移地积层在所述第1半导体芯片上，所述第1方向是从所述第1边朝向所述第1边界的方向；
导线，连接所述接合垫与所述安装基板；及
树脂，被覆所述第1半导体芯片、所述第2半导体芯片及所述导线。
9.根据权利要求8所述的半导体装置，其特征在于：
还具备积层在所述第2半导体芯片上的第3～第n半导体芯片(n为4以上)，
所述第1～第k半导体芯片(3≤k≤n－1)向所述第1方向偏移地积层，且
所述第k+1半导体芯片～第n半导体芯片向与所述第1方向相反的第2方向偏移地积层。
10.根据权利要求9所述的半导体装置，其特征在于：
所述第2～第k半导体芯片分别具有沿与所述第1边为相同侧的边配置的接合垫，
所述第k+1～第n半导体芯片分别具有沿与所述第1边为相反侧的边配置的接合垫。
11.根据权利要求10所述的半导体装置，其特征在于：
还具有第2粘接剂，所述第2粘接剂设置在所述第2～所述第n半导体芯片间，且未设置在所述第2～所述第n半导体芯片的各自的接合垫上。
12.根据权利要求8所述的半导体装置，其特征在于：
所述第1及第2粘接剂是感光性粘接剂。
13.根据权利要求8至11中任一项所述的半导体装置，其特征在于：
所述第1～第k半导体芯片是大致相同的半导体芯片，
所述第k+1～第n半导体芯片是大致相同的半导体芯片。
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