CN109427815A - 用于降低三维nor存储器阵列中的干扰的交错的字线架构 - Google Patents

用于降低三维nor存储器阵列中的干扰的交错的字线架构 Download PDF

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CN109427815A
CN109427815A CN201810988432.6A CN201810988432A CN109427815A CN 109427815 A CN109427815 A CN 109427815A CN 201810988432 A CN201810988432 A CN 201810988432A CN 109427815 A CN109427815 A CN 109427815A
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S.B.赫纳
E.哈拉里
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Sunrise Storage Co
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    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
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    • G—PHYSICS
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    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923—Programmable transistors with more than two possible different levels of programmation

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Abstract

一种交错的存储器单元架构，其在共用位线的相对侧上的交错存储器单元以维持存储器单元密度，同时增大这样的存储器单元之间的距离，由此降低干扰的可能性。在一个实施方式中，沿着共用的位线的第一侧的存储器单元连接到提供在存储器结构之下的全局字线的集合，且共用的位线的另一侧上的存储器单元——其相对于第一侧上的存储器单元交错——连接到存储器结构上方的全局字线。

Description

用于降低三维NOR存储器阵列中的干扰的交错的字线架构
相关申请的交叉引用
本申请涉及提交于2017年8月28日的题为“Staggered Word Line Architecturefor Reduced Disturb in 3-Dimensional NOR Memory Arrays”的美国临时专利申请(“母案申请”)no.62/551,110并要求其优先权。本申请涉及提交于2016年8月26日的题为“Capacitive-Coupled Non-Volatile Thin-film Transistor Strings in Three-Dimensional Arrays”的美国专利申请(“非临时申请”)no.15/248,420。该非临时申请通过引用以其整体并入本文。该非临时申请已经公布为U.S.2017/0092371。本文通过该公开文本的段落号对该非临时申请进行引用。本申请还涉及(i)提交于2017年6月20日的题为“Replacement Metal and Strut for 3D memory Array”的美国临时申请(“临时申请I”)no.62/522,666；提交于2017年6月20日的题为“3-Dimensional NOR String Arrays inSegmented Stacks”的美国临时申请(“临时申请II”)no.62/522,661；以及(iii)提交于2017年6月20日的题为“3-Dimensional NOR String Arrays in Segmented Shared StoreRegions”的美国临时申请(“临时申请III”)no.62/522,665。该母案申请、该非临时申请，以及该临时申请I、II以及III通过引用以其整体并入本文。
技术领域
本申请涉及一种非易失性NOR型存储器串。特别地，本发明涉及一种用于三维存储器阵列的架构。
背景技术
在高密度三维存储器结构中，诸如在非临时申请中所公开的那些中，期望将存储器单元保持彼此分开至少某一距离，以避免由一个存储器单元中的电荷引起的弥散场(fringing field)的效应干扰另一存储器单元中储存的电荷，同时维持期望的高密度。在诸如图1a和图1b所图示的现有技术中，NOR型存储器阵列包含存储器单元1和2，其共用单个位线108。如图1a中所示，单元1和2提供为共用的位线108的彼此直接相对的相对侧上的电荷储存层107和栅电极109(“局部字线”)。存储器单元1和2的电荷储存层107分开小于它们的共用的位线108的宽度。然而，在特征尺寸缩小的情况下，存储器单元1和2足够接近，使得每个存储器单元在编程、擦除，或读取操作期间可能干扰另一存储器单元。
图1b示出了完整的存储器结构100，其具有以图1a中所示的方式对准的字线。如图1b中所示，三维存储器结构100包含存储器单元的规则阵列，存储器单元各自由存储器单元120图示。(存储器单元120以三维示出单元1和2中的每一个。)在图1b中，存储器单元120包含沟道区域112，其提供在源极区域110、漏极区域或位线108之间。此外，存储器单元120包含(i)提供在字线109与沟道区域112之间的电荷捕获材料107，以及(ii)导体层113，提供在漏极区域或位线108附近并与之接触，以降低漏极区域或位线108中的电阻。存储器结构100的每列中的存储器单元彼此由电介质层114隔离。
图1c重现了Peng的美国专利申请公布2016/0086970的图9b，其中对相邻位线(但不相对于单个共用的位线)以交错方式提供形成在存储器结构上方的字线(“全局字线”)(即，交错的局部字线服务不同的位线)。换而言之，相邻全局字线这样的布置不缩小最接近存储器单元的距离。这些方法也牺牲了存储器阵列密度。
发明内容
本发明在不牺牲存储器单元密度的情况下避免紧密相邻的存储器单元之间的潜在干扰。根据本发明的一个实施例，交错的存储器单元架构在共用的位线的相对侧上将存储器单元交错，维持存储器单元密度，同时增大这样的存储器单元之间的距离，由此降低干扰的可能性。沿着共用的位线的第一侧的存储器单元连接到提供在存储器结构之下的全局字线的集合，而共用的位线的另一侧上的存储器单元——其相对于第一侧上的存储器单元交错——连接到存储器结构上方的全局字线。
结合附图，考虑以下的详细描述，将更好地理解本发明。
附图说明
图1a以俯视平面图示出了存储器结构100中的NOR型存储器阵列，其中存储器单元1和2共用单个位线108。
图1b示出了具有以图1a所示的方式对准的字线109的完整的三维存储器结构100。
图1c示出了现有技术NOR型存储器结构，其具有交错地并排定位在奇数列与偶数列之间的阵列顶部上的交替的字线(重现自Peng的美国专利申请公布2016/0086970的图9b)。
图2a示出了根据本发明的一个实施例的共用的位线108的相对侧上的存储器结构200的存储器单元201和202，其相对于彼此在位置上偏移或“交错”。
图2b示出了本发明的完整的三维存储器结构200，其具有以图2a所示的方式交错的字线。
图3a示出了具有互连(“全局字线”)的存储器结构300，互连在存储器结构上方和下方将信号路由，互连彼此平行，但偏移以相对于彼此交错。
图3b以平面图示出了，顶部全局字线的导体从底部全局字线的平行导体偏移大约一个半间距(pitch)。
为了便于附图间的交叉引用并简化以下的详细描述，附图中的相同元件用相同附图标记指代。
具体实施方式
图2a示出了根据本发明的一个实施例的在共用的位线108的相对侧上的存储器结构200的存储器单元201和202，其在位置上相对于彼此偏移或“交错”。
图2b示出了完整的存储器结构200，其具有以图2a中所示的方式交错的字线。如图1a的存储器结构100中，图1b示出了完整的存储器结构200，其具有以图2a中所示的方式对准的字线。如图2b中所示，三维存储器结构200包含存储器单元的规则阵列，其各自由存储器单元220图示。(存储器单元220以三维示出了存储器单元201和202中的每一个。)在图2b中，存储器单元220包含沟道区域112，其提供在源极区域110、漏极区域或位线108之间。此外，存储器单元220包含(i)提供在字线109与沟道区域112之间的电荷捕获材料107，以及(ii)导体层113，提供在与漏极区域或位线108相邻并与之接触，以降低漏极区域或位线108中的电阻。存储器结构200的每列中的存储器单元由电介质层114彼此隔离。
与图1a和图1b的最接近的存储器单元的直接相对布置不同，图2a和2b的存储器结构200使其在共用的位线108的相对侧上的最接近的存储器单元的字线109相对于彼此偏移或交错。偏移在整个位线108的长度之上维持。由于共用的位线108的相对侧上的任意对的最接近的存储器单元现在彼此偏移，与图1a中所示的最接近存储器单元的直接相对布置不同，与图1a的对准的字线的情况下的存储器单元相比，净结果是这些存储器单元中的电荷储存层之间的最接近距离上的可观增大。最接近距离上的增大帮助降低最接近存储器单元之间的编程干扰。
字线到全局互连的连接可以通过若干方法中的任意方法完成。图3a示出了具有互连层(“全局字线”)301和302的存储器结构300，互连层301和302在存储器阵列上方和下方将信号路由(分别称为“顶部全局字线”301和“底部全局字线”302)。例如，存储器结构300中的存储器阵列可以是图2b的存储器结构200中的存储器阵列。在图3a中，顶部全局字线301和底部全局字线302的导体可以彼此平行地行进，其具有实质上相同的导体间隔。图3b示出了一种布置，其中全局字线301和302的导体彼此偏移大约一个半间距，如俯视平面图中所示。图3b也示出了共用的位线108的位置，示出了实现具有交错的字线的紧密存储器阵列不需要附加的硅区域。
在此布置下，如图3b中所示，共用的位线108的一侧上的局部字线109可以直接接触底部全局字线302(经由“X”标记的位置)，而它们的共用的位线108的相对侧上的局部字线109可以直接接触顶部全局字线301(经由标记的位置307)。以此方式，实现了最高存储器单元密度，同时也使交错(例如，图2a的存储器单元201和202)之间的寄生干扰显著降低。
单元到单元干扰的不利影响由图1a的存储器单元1和2上的以下示例说明：假设相邻存储器单元1和2初始处于它们的擦除状态。存储器单元1接下来被编程为其期望的阈值电压Vpg1。然而，当存储器单元2随后也被编程为其期望的阈值电压Vpg2时，存储器单元1的阈值电压可以从其之前编程的阈值电压Vpg1漂移。存储器单元1中阈值电压漂移的量取决于存储器单元1和2之间的寄生耦合。相对于背对背存储器单元(例如，图1a的存储器单元1和2)，本发明的交错的存储器单元(例如，图2a的存储器单元201和202)已经可观地降低了寄生耦合。当存储器单元在多级单元(MLC)操作模式下储存多于一个二进制位的信息时(其中每个存储器单元可以被编程为若干阈值电压中的任意一个)，不期望的单元到单元干扰是尤其有问题的。相对于单个二进制位操作模式，阈值电压之间要求的电压分隔相应地更小。使图2a的存储器单元201和202相对于彼此交错实质上降低了这样的干扰，由此使得MLC成为可行的操作模式。
提供以上详细描述，以阐述本发明的具体实施例，并且不意图限制。本发明的范围内的各种修改和变化是可能的。本发明在所附权利要求中提出。

Claims (8)

1.一种存储器结构，包括：
半导体基板，所述半导体基板具有平坦表面；
存储器单元的阵列，所述存储器单元的阵列共用公共位线，所述公共位线沿着实质上平行于所述半导体基板的平坦表面的第一方向延伸，其中所述存储器单元的第一组提供在所述公共位线的第一侧上，并且其中所述存储器单元的第二组提供在所述公共位线的与所述第一侧相对的第二侧上，并且其中每个存储器单元包括储存层；
第一多个导体，所述第一多个导体提供在所述半导体基板上方且在所述存储器单元的阵列下方，所述第一多个导体中的每个导体沿着第二方向延伸，所述第二方向平行于所述平坦表面并且实质上垂直于所述第一方向，其中所述第一多个导体中的导体彼此分开第一距离；
第二多个导体，所述第二多个导体提供在所述存储器单元的阵列上方，所述第二多个导体中的每个导体沿着所述第二方向延伸，其中所述第二多个导体中的导体彼此分开所述第一距离，并且其中所述第二多个导体沿着所述第一方向从所述导体的第一集合偏移所述第一距离的实质上一半；
导体的第三集合，所述导体的第三集合各自沿着第三方向延伸，所述第三方向实质上垂直于所述平坦表面，其中所述第三多个导体的第一组各自接触所述第一多个导体中的导体，并且其中所述第三多个导体的第二组各自接触所述第二多个导体中的导体，其中所述第三多个导体的第一组和第二组中的每个导体提供为与所述存储器单元的第一组或第二组中的存储器单元的储存层接触，充当所述存储器单元的栅电极。
2.如权利要求1所述的存储器结构，其中所述存储器单元共用公共源极线。
3.如权利要求1所述的存储器结构，其中电路形成在所述半导体基板中或上，其中所述第一多个导体和所述第二多个导体中的每一个和所述公共位线电连接到所述电路。
4.如权利要求1所述的存储器结构，其中所述第一多个导体和所述第二多个导体中的导体包括金属导体。
5.如权利要求1所述的存储器结构，其中所述第三多个导体中的导体包括多晶硅。
6.如权利要求2所述的存储器结构，其中所述公共源极线除当通过所述公共位线被预充电到预定的电压时之外与所述电路隔离。
7.如权利要求1所述的存储器结构，其中每个存储器单元储存多于一位的信息。
8.如权利要求6所述的存储器结构，其中每个存储器单元储存多于一位的信息。
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