IT201700061469A1 - Dispositivo di memoria 3d con stringhe di celle di memoria ad “u” - Google Patents

Dispositivo di memoria 3d con stringhe di celle di memoria ad “u”

Info

Publication number
IT201700061469A1
IT201700061469A1 IT102017000061469A IT201700061469A IT201700061469A1 IT 201700061469 A1 IT201700061469 A1 IT 201700061469A1 IT 102017000061469 A IT102017000061469 A IT 102017000061469A IT 201700061469 A IT201700061469 A IT 201700061469A IT 201700061469 A1 IT201700061469 A1 IT 201700061469A1
Authority
IT
Italy
Prior art keywords
cell strings
memory
memory cell
memory device
strings
Prior art date
Application number
IT102017000061469A
Other languages
English (en)
Inventor
Sabrina Barbato
Original Assignee
Sabrina Barbato
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sabrina Barbato filed Critical Sabrina Barbato
Priority to IT102017000061469A priority Critical patent/IT201700061469A1/it
Priority to US15/991,181 priority patent/US10510768B2/en
Publication of IT201700061469A1 publication Critical patent/IT201700061469A1/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
IT102017000061469A 2017-06-06 2017-06-06 Dispositivo di memoria 3d con stringhe di celle di memoria ad “u” IT201700061469A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT102017000061469A IT201700061469A1 (it) 2017-06-06 2017-06-06 Dispositivo di memoria 3d con stringhe di celle di memoria ad “u”
US15/991,181 US10510768B2 (en) 2017-06-06 2018-05-29 3D memory device with U-shaped memory cell strings

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT102017000061469A IT201700061469A1 (it) 2017-06-06 2017-06-06 Dispositivo di memoria 3d con stringhe di celle di memoria ad “u”

Publications (1)

Publication Number Publication Date
IT201700061469A1 true IT201700061469A1 (it) 2018-12-06

Family

ID=60202289

Family Applications (1)

Application Number Title Priority Date Filing Date
IT102017000061469A IT201700061469A1 (it) 2017-06-06 2017-06-06 Dispositivo di memoria 3d con stringhe di celle di memoria ad “u”

Country Status (2)

Country Link
US (1) US10510768B2 (it)
IT (1) IT201700061469A1 (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10431596B2 (en) * 2017-08-28 2019-10-01 Sunrise Memory Corporation Staggered word line architecture for reduced disturb in 3-dimensional NOR memory arrays
US10593730B1 (en) * 2018-10-10 2020-03-17 Micron Technology, Inc. Three-dimensional memory array
US11037947B2 (en) * 2019-04-15 2021-06-15 Macronix International Co., Ltd. Array of pillars located in a uniform pattern
JP2021034529A (ja) 2019-08-22 2021-03-01 キオクシア株式会社 不揮発性半導体記憶装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090296476A1 (en) * 2008-05-28 2009-12-03 Hynix Semiconductor Inc. Flash Memory Device and Method for Manufacturing the Same
US20130100741A1 (en) * 2011-10-24 2013-04-25 Sang Moo Choi 3-d nonvolatile memory device and method of manufacturing the same, and memory system including the 3-d nonvolatile memory device
US20130153978A1 (en) * 2011-12-20 2013-06-20 Ki Hong Lee 3d non-volatile memory device and method of manufacturing the same
US20140264525A1 (en) * 2013-03-12 2014-09-18 SanDisk Technologies, Inc. Vertical nand and method of making thereof using sequential stack etching and landing pad
US20140273373A1 (en) * 2013-03-12 2014-09-18 SanDisk Technologies, Inc. Method of making a vertical nand device using sequential etching of multilayer stacks
US20160020221A1 (en) * 2014-07-21 2016-01-21 SK Hynix Inc. Three-dimensional (3d) non-volatile memory device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013004778A (ja) 2011-06-17 2013-01-07 Toshiba Corp 半導体記憶装置
US8897070B2 (en) * 2011-11-02 2014-11-25 Sandisk Technologies Inc. Selective word line erase in 3D non-volatile memory
JP6139370B2 (ja) * 2013-10-17 2017-05-31 株式会社東芝 不揮発性半導体記憶装置
US9218874B1 (en) 2014-08-11 2015-12-22 Sandisk Technologies Inc. Multi-pulse programming cycle of non-volatile memory for enhanced de-trapping
US9406693B1 (en) * 2015-04-20 2016-08-02 Sandisk Technologies Llc Selective removal of charge-trapping layer for select gate transistors and dummy memory cells in 3D stacked memory
KR20170028731A (ko) * 2015-09-04 2017-03-14 에스케이하이닉스 주식회사 비휘발성 메모리 소자 및 그 제조방법
US10223004B2 (en) * 2016-04-07 2019-03-05 International Business Machines Corporation Parallel read and writes in 3D flash memory

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090296476A1 (en) * 2008-05-28 2009-12-03 Hynix Semiconductor Inc. Flash Memory Device and Method for Manufacturing the Same
US20130100741A1 (en) * 2011-10-24 2013-04-25 Sang Moo Choi 3-d nonvolatile memory device and method of manufacturing the same, and memory system including the 3-d nonvolatile memory device
US20130153978A1 (en) * 2011-12-20 2013-06-20 Ki Hong Lee 3d non-volatile memory device and method of manufacturing the same
US20140264525A1 (en) * 2013-03-12 2014-09-18 SanDisk Technologies, Inc. Vertical nand and method of making thereof using sequential stack etching and landing pad
US20140273373A1 (en) * 2013-03-12 2014-09-18 SanDisk Technologies, Inc. Method of making a vertical nand device using sequential etching of multilayer stacks
US20160020221A1 (en) * 2014-07-21 2016-01-21 SK Hynix Inc. Three-dimensional (3d) non-volatile memory device

Also Published As

Publication number Publication date
US10510768B2 (en) 2019-12-17
US20180350832A1 (en) 2018-12-06

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